add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/mach-exynos/suspend.c
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@@ -3,7 +3,7 @@
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 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
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 //		http://www.samsung.com
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 //
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-// EXYNOS - Suspend support
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+// Exynos - Suspend support
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 //
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 // Based on arch/arm/mach-s3c2410/pm.c
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 // Copyright (c) 2006 Simtec Electronics
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@@ -30,9 +30,8 @@
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 #include <asm/smp_scu.h>
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 #include <asm/suspend.h>
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32
 
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-#include <plat/pm-common.h>
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-
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 #include "common.h"
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+#include "smc.h"
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35
 
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 #define REG_TABLE_END (-1U)
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@@ -59,10 +58,17 @@
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 	int (*cpu_suspend)(unsigned long);
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 };
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60
 
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-static const struct exynos_pm_data *pm_data __ro_after_init;
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+/* Used only on Exynos542x/5800 */
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+struct exynos_pm_state {
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+	int cpu_state;
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+	unsigned int pmu_spare3;
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+	void __iomem *sysram_base;
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+	phys_addr_t sysram_phys;
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+	bool secure_firmware;
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+};
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-static int exynos5420_cpu_state;
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-static unsigned int exynos_pmu_spare3;
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+static const struct exynos_pm_data *pm_data __ro_after_init;
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+static struct exynos_pm_state pm_state;
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 /*
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  * GIC wake-up support
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@@ -87,6 +93,11 @@
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 	{ 44, BIT(2) }, /* RTC tick */
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 	{ /* sentinel */ },
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 };
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+
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+static u32 exynos_read_eint_wakeup_mask(void)
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+{
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+	return pmu_raw_readl(EXYNOS_EINT_WAKEUP_MASK);
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+}
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 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
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 {
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@@ -257,9 +268,7 @@
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 	unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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 	unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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-	writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
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-
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-	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
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+	if (IS_ENABLED(CONFIG_EXYNOS_MCPM)) {
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 		mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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 		mcpm_cpu_suspend();
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 	}
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@@ -272,9 +281,11 @@
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 static void exynos_pm_set_wakeup_mask(void)
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 {
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-	/* Set wake-up mask registers */
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-	pmu_raw_writel(exynos_get_eint_wake_mask(), EXYNOS_EINT_WAKEUP_MASK);
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-	pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
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+	/*
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+	 * Set wake-up mask registers
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+	 * EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
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+	 */
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+	pmu_raw_writel(exynos_irqwake_intmask & ~BIT(31), S5P_WAKEUP_MASK);
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 }
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 static void exynos_pm_enter_sleep_mode(void)
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@@ -321,7 +332,7 @@
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 	/* Set wake-up mask registers */
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 	exynos_pm_set_wakeup_mask();
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-	exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
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+	pm_state.pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
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 	/*
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 	 * The cpu state needs to be saved and restored so that the
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 	 * secondary CPUs will enter low power start. Though the U-Boot
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@@ -329,13 +340,18 @@
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 	 * needs to restore it back in case, the primary cpu fails to
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 	 * suspend for any reason.
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 	 */
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-	exynos5420_cpu_state = readl_relaxed(sysram_base_addr +
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-					     EXYNOS5420_CPU_STATE);
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+	pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +
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+					   EXYNOS5420_CPU_STATE);
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+	writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
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+	if (pm_state.secure_firmware)
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+		exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(pm_state.sysram_phys +
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+							 EXYNOS5420_CPU_STATE),
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+			   0, 0);
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 	exynos_pm_enter_sleep_mode();
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 	/* ensure at least INFORM0 has the resume address */
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-	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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+	if (IS_ENABLED(CONFIG_EXYNOS_MCPM))
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 		pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
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 	tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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@@ -439,7 +455,7 @@
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 	mpidr = read_cpuid_mpidr();
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 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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-	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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+	if (IS_ENABLED(CONFIG_EXYNOS_MCPM))
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 		WARN_ON(mcpm_cpu_powered_up());
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 	if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
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@@ -467,8 +483,13 @@
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 		       EXYNOS5_ARM_CORE0_SYS_PWR_REG);
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 	/* Restore the sysram cpu state register */
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-	writel_relaxed(exynos5420_cpu_state,
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-		       sysram_base_addr + EXYNOS5420_CPU_STATE);
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+	writel_relaxed(pm_state.cpu_state,
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+		       pm_state.sysram_base + EXYNOS5420_CPU_STATE);
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+	if (pm_state.secure_firmware)
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+		exynos_smc(SMC_CMD_REG,
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+			   SMC_REG_ID_SFR_W(pm_state.sysram_phys +
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+					    EXYNOS5420_CPU_STATE),
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+			   EXYNOS_AFTR_MAGIC, 0);
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 	pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
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 			S5P_CENTRAL_SEQ_OPTION);
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@@ -476,7 +497,7 @@
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 	if (exynos_pm_central_resume())
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 		goto early_wakeup;
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-	pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
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+	pmu_raw_writel(pm_state.pmu_spare3, S5P_PMU_SPARE3);
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 early_wakeup:
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@@ -502,27 +523,24 @@
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 static int exynos_suspend_enter(suspend_state_t state)
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 {
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+	u32 eint_wakeup_mask = exynos_read_eint_wakeup_mask();
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 	int ret;
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-	s3c_pm_debug_init();
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+	pr_debug("%s: suspending the system...\n", __func__);
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-	S3C_PMDBG("%s: suspending the system...\n", __func__);
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-
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-	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
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-			exynos_irqwake_intmask, exynos_get_eint_wake_mask());
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+	pr_debug("%s: wakeup masks: %08x,%08x\n", __func__,
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+		  exynos_irqwake_intmask, eint_wakeup_mask);
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 	if (exynos_irqwake_intmask == -1U
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-	    && exynos_get_eint_wake_mask() == -1U) {
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+	    && eint_wakeup_mask == EXYNOS_EINT_WAKEUP_MASK_DISABLED) {
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 		pr_err("%s: No wake-up sources!\n", __func__);
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 		pr_err("%s: Aborting sleep\n", __func__);
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 		return -EINVAL;
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 	}
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-	s3c_pm_save_uarts();
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 	if (pm_data->pm_prepare)
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 		pm_data->pm_prepare();
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 	flush_cache_all();
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-	s3c_pm_check_store();
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 	ret = call_firmware_op(suspend);
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 	if (ret == -ENOSYS)
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@@ -532,14 +550,11 @@
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 	if (pm_data->pm_resume_prepare)
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 		pm_data->pm_resume_prepare();
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-	s3c_pm_restore_uarts();
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-	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
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+	pr_debug("%s: wakeup stat: %08x\n", __func__,
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 			pmu_raw_readl(S5P_WAKEUP_STAT));
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-	s3c_pm_check_restore();
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-
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-	S3C_PMDBG("%s: resuming the system...\n", __func__);
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+	pr_debug("%s: resuming the system...\n", __func__);
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 	return 0;
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 }
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@@ -562,16 +577,12 @@
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 		return ret;
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 	}
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579
 
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-	s3c_pm_check_prepare();
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-
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 	return 0;
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 }
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 static void exynos_suspend_finish(void)
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 {
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 	int ret;
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-
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-	s3c_pm_check_cleanup();
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 	ret = regulator_suspend_finish();
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 	if (ret)
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@@ -675,4 +686,16 @@
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 	register_syscore_ops(&exynos_pm_syscore_ops);
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 	suspend_set_ops(&exynos_suspend_ops);
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+
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+	/*
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+	 * Applicable as of now only to Exynos542x. If booted under secure
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+	 * firmware, the non-secure region of sysram should be used.
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+	 */
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+	if (exynos_secure_firmware_available()) {
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+		pm_state.sysram_phys = sysram_base_phys;
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+		pm_state.sysram_base = sysram_ns_base_addr;
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+		pm_state.secure_firmware = true;
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+	} else {
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+		pm_state.sysram_base = sysram_base_addr;
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+	}
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 }