add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/include/asm/arch_timer.h
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@@ -4,6 +4,7 @@
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 #include <asm/barrier.h>
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 #include <asm/errno.h>
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+#include <asm/hwcap.h>
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 #include <linux/clocksource.h>
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 #include <linux/init.h>
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 #include <linux/types.h>
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@@ -11,6 +12,10 @@
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 #include <clocksource/arm_arch_timer.h>
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 #ifdef CONFIG_ARM_ARCH_TIMER
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+/* 32bit ARM doesn't know anything about timer errata... */
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+#define has_erratum_handler(h)		(false)
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+#define erratum_handler(h)		(arch_timer_##h)
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+
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 int arch_timer_arch_init(void);
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 /*
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@@ -79,7 +84,7 @@
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 	return val;
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 }
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-static inline u64 arch_counter_get_cntpct(void)
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+static inline u64 __arch_counter_get_cntpct(void)
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 {
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 	u64 cval;
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@@ -88,13 +93,23 @@
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 	return cval;
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 }
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-static inline u64 arch_counter_get_cntvct(void)
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+static inline u64 __arch_counter_get_cntpct_stable(void)
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+{
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+	return __arch_counter_get_cntpct();
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+}
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+
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+static inline u64 __arch_counter_get_cntvct(void)
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 {
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 	u64 cval;
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 	isb();
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 	asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
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 	return cval;
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+}
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+
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+static inline u64 __arch_counter_get_cntvct_stable(void)
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+{
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+	return __arch_counter_get_cntvct();
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 }
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 static inline u32 arch_timer_get_cntkctl(void)
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@@ -110,6 +125,15 @@
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 	isb();
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 }
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+static inline void arch_timer_set_evtstrm_feature(void)
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+{
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+	elf_hwcap |= HWCAP_EVTSTRM;
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+}
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+
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+static inline bool arch_timer_have_evtstrm_feature(void)
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+{
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+	return elf_hwcap & HWCAP_EVTSTRM;
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+}
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 #endif
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 #endif