add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/crypto/sha512-core.S_shipped
..
..
@@ -12,7 +12,7 @@
12
12
 @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
13
13
 @ project. The module is, however, dual licensed under OpenSSL and
14
14
 @ CRYPTOGAMS licenses depending on where you obtain it. For further
15
-@ details see http://www.openssl.org/~appro/cryptogams/.
15
+@ details see https://www.openssl.org/~appro/cryptogams/.
16
16
 @ ====================================================================
17
17
 
18
18
 @ SHA512 block procedure for ARMv4. September 2007.
..
..
@@ -42,7 +42,7 @@
42
42
 @ terms it's 22.6 cycles per byte, which is disappointing result.
43
43
 @ Technical writers asserted that 3-way S4 pipeline can sustain
44
44
 @ multiple NEON instructions per cycle, but dual NEON issue could
45
-@ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
45
+@ not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
46
46
 @ for further details. On side note Cortex-A15 processes one byte in
47
47
 @ 16 cycles.
48
48
 
..
..
@@ -79,7 +79,6 @@
79
79
 #else
80
80
 .syntax unified
81
81
 # ifdef __thumb2__
82
-#  define adrl adr
83
82
 .thumb
84
83
 # else
85
84
 .code   32
..
..
@@ -543,7 +542,8 @@
543
542
 	dmb				@ errata #451034 on early Cortex A8
544
543
 	add	r2,r1,r2,lsl#7	@ len to point at the end of inp
545
544
 	VFP_ABI_PUSH
546
-	adrl	r3,K512
545
+	adr	r3,.Lsha512_block_data_order
546
+	sub	r3,r3,.Lsha512_block_data_order-K512
547
547
 	vldmia	r0,{d16-d23}		@ load context
548
548
 .Loop_neon:
549
549
 	vshr.u64	d24,d20,#14	@ 0