add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/boot/dts/vf610-zii-dev.dtsi
..
..
@@ -50,6 +50,7 @@
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 	};
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51
 
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 	memory@80000000 {
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+		device_type = "memory";
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 		reg = <0x80000000 0x20000000>;
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 	};
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..
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@@ -82,6 +83,14 @@
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 		regulator-always-on;
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 		regulator-boot-on;
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 		gpio = <&gpio0 6 0>;
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+	};
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+
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+	supply-voltage-monitor {
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+		compatible = "iio-hwmon";
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+		io-channels = <&adc0 8>, /* VCC_1V5 */
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+			      <&adc0 9>, /* VCC_1V8 */
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+			      <&adc1 8>, /* VCC_1V0 */
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+			      <&adc1 9>; /* VCC_1V2 */
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 	};
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 };
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..
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@@ -128,6 +137,8 @@
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 	mdio1: mdio {
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 		#address-cells = <1>;
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 		#size-cells = <0>;
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+		clock-frequency = <12500000>;
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+		suppress-preamble;
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 		status = "okay";
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 	};
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 };
..
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@@ -137,7 +148,7 @@
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 	pinctrl-names = "default", "gpio";
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 	pinctrl-0 = <&pinctrl_i2c0>;
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 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
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-	scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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+	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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 	sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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 	status = "okay";
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@@ -146,12 +157,12 @@
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 		reg = <0x48>;
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 	};
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-	at24c04@50 {
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+	eeprom@50 {
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 		compatible = "atmel,24c04";
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 		reg = <0x50>;
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 	};
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-	at24c04@52 {
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+	eeprom@52 {
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 		compatible = "atmel,24c04";
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 		reg = <0x52>;
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 	};
..
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@@ -174,6 +185,36 @@
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&pinctrl_i2c2>;
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 	status = "okay";
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+};
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+
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+&qspi0 {
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+	pinctrl-names = "default";
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+	pinctrl-0 = <&pinctrl_qspi0>;
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+	status = "okay";
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+
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+	/*
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+	 * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
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+	 * modes, so, spi-max-frequency is limited to 90MHz
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+	 */
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+	flash@0 {
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+		compatible = "jedec,spi-nor";
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+		#address-cells = <1>;
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+		#size-cells = <1>;
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+		spi-max-frequency = <90000000>;
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+		spi-rx-bus-width = <4>;
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+		reg = <0>;
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+		m25p,fast-read;
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+	};
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+
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+	flash@2 {
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+		compatible = "jedec,spi-nor";
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+		#address-cells = <1>;
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+		#size-cells = <1>;
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+		spi-max-frequency = <90000000>;
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+		spi-rx-bus-width = <4>;
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+		reg = <2>;
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+		m25p,fast-read;
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+	};
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 };
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 &uart0 {
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@@ -359,12 +400,18 @@
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 	pinctrl_qspi0: qspi0grp {
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 		fsl,pins = <
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-			VF610_PAD_PTD7__QSPI0_B_QSCK	0x31c3
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-			VF610_PAD_PTD8__QSPI0_B_CS0	0x31ff
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-			VF610_PAD_PTD9__QSPI0_B_DATA3	0x31c3
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-			VF610_PAD_PTD10__QSPI0_B_DATA2	0x31c3
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-			VF610_PAD_PTD11__QSPI0_B_DATA1	0x31c3
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-			VF610_PAD_PTD12__QSPI0_B_DATA0	0x31c3
403
+			VF610_PAD_PTD0__QSPI0_A_QSCK	0x38c2
404
+			VF610_PAD_PTD1__QSPI0_A_CS0	0x38c2
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+			VF610_PAD_PTD2__QSPI0_A_DATA3	0x38c3
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+			VF610_PAD_PTD3__QSPI0_A_DATA2	0x38c3
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+			VF610_PAD_PTD4__QSPI0_A_DATA1	0x38c3
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+			VF610_PAD_PTD5__QSPI0_A_DATA0	0x38c3
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+			VF610_PAD_PTD7__QSPI0_B_QSCK	0x38c2
410
+			VF610_PAD_PTD8__QSPI0_B_CS0	0x38c2
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+			VF610_PAD_PTD9__QSPI0_B_DATA3	0x38c3
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+			VF610_PAD_PTD10__QSPI0_B_DATA2	0x38c3
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+			VF610_PAD_PTD11__QSPI0_B_DATA1	0x38c3
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+			VF610_PAD_PTD12__QSPI0_B_DATA0	0x38c3
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 		>;
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 	};
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..
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@@ -384,8 +431,8 @@
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 	pinctrl_uart2: uart2grp {
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 		fsl,pins = <
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-			VF610_PAD_PTD0__UART2_TX	0x21a2
388
-			VF610_PAD_PTD1__UART2_RX	0x21a1
434
+			VF610_PAD_PTD23__UART2_TX	0x21a2
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+			VF610_PAD_PTD22__UART2_RX	0x21a1
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 		>;
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 	};
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