.. | .. |
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51 | 51 | ranges; |
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52 | 52 | interrupt-parent = <&intc>; |
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53 | 53 | |
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54 | | - l2: l2-cache@500c0000 { |
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| 54 | + l2: cache-controller@500c0000 { |
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55 | 55 | compatible = "socionext,uniphier-system-cache"; |
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56 | 56 | reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, |
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57 | 57 | <0x506c0000 0x400>; |
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.. | .. |
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61 | 61 | cache-sets = <256>; |
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62 | 62 | cache-line-size = <128>; |
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63 | 63 | cache-level = <2>; |
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| 64 | + }; |
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| 65 | + |
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| 66 | + spi: spi@54006000 { |
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| 67 | + compatible = "socionext,uniphier-scssi"; |
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| 68 | + status = "disabled"; |
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| 69 | + reg = <0x54006000 0x100>; |
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| 70 | + #address-cells = <1>; |
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| 71 | + #size-cells = <0>; |
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| 72 | + interrupts = <0 39 4>; |
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| 73 | + pinctrl-names = "default"; |
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| 74 | + pinctrl-0 = <&pinctrl_spi0>; |
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| 75 | + clocks = <&peri_clk 11>; |
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| 76 | + resets = <&peri_rst 11>; |
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64 | 77 | }; |
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65 | 78 | |
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66 | 79 | serial0: serial@54006800 { |
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.. | .. |
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224 | 237 | }; |
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225 | 238 | }; |
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226 | 239 | |
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| 240 | + dmac: dma-controller@5a000000 { |
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| 241 | + compatible = "socionext,uniphier-mio-dmac"; |
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| 242 | + reg = <0x5a000000 0x1000>; |
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| 243 | + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, |
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| 244 | + <0 71 4>, <0 72 4>, <0 73 4>; |
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| 245 | + clocks = <&mio_clk 7>; |
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| 246 | + resets = <&mio_rst 7>; |
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| 247 | + #dma-cells = <1>; |
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| 248 | + }; |
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| 249 | + |
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| 250 | + sd: mmc@5a400000 { |
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| 251 | + compatible = "socionext,uniphier-sd-v2.91"; |
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| 252 | + status = "disabled"; |
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| 253 | + reg = <0x5a400000 0x200>; |
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| 254 | + interrupts = <0 76 4>; |
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| 255 | + pinctrl-names = "default", "uhs"; |
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| 256 | + pinctrl-0 = <&pinctrl_sd>; |
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| 257 | + pinctrl-1 = <&pinctrl_sd_uhs>; |
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| 258 | + clocks = <&mio_clk 0>; |
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| 259 | + reset-names = "host", "bridge"; |
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| 260 | + resets = <&mio_rst 0>, <&mio_rst 3>; |
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| 261 | + dma-names = "rx-tx"; |
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| 262 | + dmas = <&dmac 4>; |
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| 263 | + bus-width = <4>; |
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| 264 | + cap-sd-highspeed; |
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| 265 | + sd-uhs-sdr12; |
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| 266 | + sd-uhs-sdr25; |
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| 267 | + sd-uhs-sdr50; |
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| 268 | + }; |
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| 269 | + |
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| 270 | + emmc: mmc@5a500000 { |
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| 271 | + compatible = "socionext,uniphier-sd-v2.91"; |
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| 272 | + status = "disabled"; |
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| 273 | + reg = <0x5a500000 0x200>; |
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| 274 | + interrupts = <0 78 4>; |
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| 275 | + pinctrl-names = "default"; |
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| 276 | + pinctrl-0 = <&pinctrl_emmc>; |
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| 277 | + clocks = <&mio_clk 1>; |
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| 278 | + reset-names = "host", "bridge", "hw"; |
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| 279 | + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; |
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| 280 | + dma-names = "rx-tx"; |
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| 281 | + dmas = <&dmac 6>; |
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| 282 | + bus-width = <8>; |
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| 283 | + cap-mmc-highspeed; |
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| 284 | + cap-mmc-hw-reset; |
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| 285 | + non-removable; |
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| 286 | + }; |
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| 287 | + |
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227 | 288 | usb0: usb@5a800100 { |
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228 | 289 | compatible = "socionext,uniphier-ehci", "generic-ehci"; |
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229 | 290 | status = "disabled"; |
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.. | .. |
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316 | 377 | interrupt-controller; |
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317 | 378 | }; |
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318 | 379 | |
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319 | | - aidet: aidet@61830000 { |
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| 380 | + aidet: interrupt-controller@61830000 { |
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320 | 381 | compatible = "socionext,uniphier-ld4-aidet"; |
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321 | 382 | reg = <0x61830000 0x200>; |
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322 | 383 | interrupt-controller; |
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.. | .. |
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339 | 400 | }; |
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340 | 401 | }; |
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341 | 402 | |
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342 | | - nand: nand@68000000 { |
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| 403 | + nand: nand-controller@68000000 { |
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343 | 404 | compatible = "socionext,uniphier-denali-nand-v5a"; |
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344 | 405 | status = "disabled"; |
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345 | 406 | reg-names = "nand_data", "denali_reg"; |
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346 | 407 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; |
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| 408 | + #address-cells = <1>; |
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| 409 | + #size-cells = <0>; |
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347 | 410 | interrupts = <0 65 4>; |
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348 | 411 | pinctrl-names = "default"; |
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349 | | - pinctrl-0 = <&pinctrl_nand2cs>; |
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350 | | - clocks = <&sys_clk 2>; |
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351 | | - resets = <&sys_rst 2>; |
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| 412 | + pinctrl-0 = <&pinctrl_nand>; |
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| 413 | + clock-names = "nand", "nand_x", "ecc"; |
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| 414 | + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; |
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| 415 | + reset-names = "nand", "reg"; |
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| 416 | + resets = <&sys_rst 2>, <&sys_rst 2>; |
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352 | 417 | }; |
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353 | 418 | }; |
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354 | 419 | }; |
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