forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2
kernel/arch/arm/boot/dts/uniphier-ld4.dtsi
....@@ -51,7 +51,7 @@
5151 ranges;
5252 interrupt-parent = <&intc>;
5353
54
- l2: l2-cache@500c0000 {
54
+ l2: cache-controller@500c0000 {
5555 compatible = "socionext,uniphier-system-cache";
5656 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
5757 <0x506c0000 0x400>;
....@@ -61,6 +61,19 @@
6161 cache-sets = <256>;
6262 cache-line-size = <128>;
6363 cache-level = <2>;
64
+ };
65
+
66
+ spi: spi@54006000 {
67
+ compatible = "socionext,uniphier-scssi";
68
+ status = "disabled";
69
+ reg = <0x54006000 0x100>;
70
+ #address-cells = <1>;
71
+ #size-cells = <0>;
72
+ interrupts = <0 39 4>;
73
+ pinctrl-names = "default";
74
+ pinctrl-0 = <&pinctrl_spi0>;
75
+ clocks = <&peri_clk 11>;
76
+ resets = <&peri_rst 11>;
6477 };
6578
6679 serial0: serial@54006800 {
....@@ -224,6 +237,54 @@
224237 };
225238 };
226239
240
+ dmac: dma-controller@5a000000 {
241
+ compatible = "socionext,uniphier-mio-dmac";
242
+ reg = <0x5a000000 0x1000>;
243
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
244
+ <0 71 4>, <0 72 4>, <0 73 4>;
245
+ clocks = <&mio_clk 7>;
246
+ resets = <&mio_rst 7>;
247
+ #dma-cells = <1>;
248
+ };
249
+
250
+ sd: mmc@5a400000 {
251
+ compatible = "socionext,uniphier-sd-v2.91";
252
+ status = "disabled";
253
+ reg = <0x5a400000 0x200>;
254
+ interrupts = <0 76 4>;
255
+ pinctrl-names = "default", "uhs";
256
+ pinctrl-0 = <&pinctrl_sd>;
257
+ pinctrl-1 = <&pinctrl_sd_uhs>;
258
+ clocks = <&mio_clk 0>;
259
+ reset-names = "host", "bridge";
260
+ resets = <&mio_rst 0>, <&mio_rst 3>;
261
+ dma-names = "rx-tx";
262
+ dmas = <&dmac 4>;
263
+ bus-width = <4>;
264
+ cap-sd-highspeed;
265
+ sd-uhs-sdr12;
266
+ sd-uhs-sdr25;
267
+ sd-uhs-sdr50;
268
+ };
269
+
270
+ emmc: mmc@5a500000 {
271
+ compatible = "socionext,uniphier-sd-v2.91";
272
+ status = "disabled";
273
+ reg = <0x5a500000 0x200>;
274
+ interrupts = <0 78 4>;
275
+ pinctrl-names = "default";
276
+ pinctrl-0 = <&pinctrl_emmc>;
277
+ clocks = <&mio_clk 1>;
278
+ reset-names = "host", "bridge", "hw";
279
+ resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
280
+ dma-names = "rx-tx";
281
+ dmas = <&dmac 6>;
282
+ bus-width = <8>;
283
+ cap-mmc-highspeed;
284
+ cap-mmc-hw-reset;
285
+ non-removable;
286
+ };
287
+
227288 usb0: usb@5a800100 {
228289 compatible = "socionext,uniphier-ehci", "generic-ehci";
229290 status = "disabled";
....@@ -316,7 +377,7 @@
316377 interrupt-controller;
317378 };
318379
319
- aidet: aidet@61830000 {
380
+ aidet: interrupt-controller@61830000 {
320381 compatible = "socionext,uniphier-ld4-aidet";
321382 reg = <0x61830000 0x200>;
322383 interrupt-controller;
....@@ -339,16 +400,20 @@
339400 };
340401 };
341402
342
- nand: nand@68000000 {
403
+ nand: nand-controller@68000000 {
343404 compatible = "socionext,uniphier-denali-nand-v5a";
344405 status = "disabled";
345406 reg-names = "nand_data", "denali_reg";
346407 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
408
+ #address-cells = <1>;
409
+ #size-cells = <0>;
347410 interrupts = <0 65 4>;
348411 pinctrl-names = "default";
349
- pinctrl-0 = <&pinctrl_nand2cs>;
350
- clocks = <&sys_clk 2>;
351
- resets = <&sys_rst 2>;
412
+ pinctrl-0 = <&pinctrl_nand>;
413
+ clock-names = "nand", "nand_x", "ecc";
414
+ clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
415
+ reset-names = "nand", "reg";
416
+ resets = <&sys_rst 2>, <&sys_rst 2>;
352417 };
353418 };
354419 };