add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/boot/dts/tegra114.dtsi
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@@ -4,6 +4,7 @@
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 #include <dt-bindings/memory/tegra114-mc.h>
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 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/soc/tegra-pmc.h>
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 / {
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 	compatible = "nvidia,tegra114";
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@@ -17,11 +18,13 @@
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 	};
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 	host1x@50000000 {
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-		compatible = "nvidia,tegra114-host1x", "simple-bus";
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+		compatible = "nvidia,tegra114-host1x";
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 		reg = <0x50000000 0x00028000>;
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 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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+		interrupt-names = "syncpt", "host1x";
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 		clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
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+		clock-names = "host1x";
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 		resets = <&tegra_car 28>;
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 		reset-names = "host1x";
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 		iommus = <&mc TEGRA_SWGROUP_HC>;
..
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@@ -32,7 +35,7 @@
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 		ranges = <0x54000000 0x54000000 0x01000000>;
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 		gr2d@54140000 {
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-			compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
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+			compatible = "nvidia,tegra114-gr2d";
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 			reg = <0x54140000 0x00040000>;
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 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&tegra_car TEGRA114_CLK_GR2D>;
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@@ -43,7 +46,7 @@
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 		};
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 		gr3d@54180000 {
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-			compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
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+			compatible = "nvidia,tegra114-gr3d";
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 			reg = <0x54180000 0x00040000>;
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 			clocks = <&tegra_car TEGRA114_CLK_GR3D>;
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 			resets = <&tegra_car 24>;
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@@ -53,7 +56,7 @@
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 		};
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 		dc@54200000 {
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-			compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
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+			compatible = "nvidia,tegra114-dc";
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 			reg = <0x54200000 0x00040000>;
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 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&tegra_car TEGRA114_CLK_DISP1>,
..
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@@ -72,7 +75,7 @@
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 		};
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 		dc@54240000 {
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-			compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
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+			compatible = "nvidia,tegra114-dc";
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 			reg = <0x54240000 0x00040000>;
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 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&tegra_car TEGRA114_CLK_DISP2>,
..
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@@ -252,14 +255,14 @@
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 	apbmisc@70000800 {
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 		compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
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-		reg = <0x70000800 0x64   /* Chip revision */
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-		       0x70000008 0x04>; /* Strapping options */
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+		reg = <0x70000800 0x64>, /* Chip revision */
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+		      <0x70000008 0x04>; /* Strapping options */
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 	};
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 	pinmux: pinmux@70000868 {
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 		compatible = "nvidia,tegra114-pinmux";
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-		reg = <0x70000868 0x148		/* Pad control registers */
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-		       0x70003000 0x40c>;	/* Mux registers */
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+		reg = <0x70000868 0x148>, /* Pad control registers */
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+		      <0x70003000 0x40c>; /* Mux registers */
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 	};
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 	/*
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@@ -514,11 +517,12 @@
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 		status = "disabled";
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 	};
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-	pmc@7000e400 {
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+	tegra_pmc: pmc@7000e400 {
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 		compatible = "nvidia,tegra114-pmc";
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 		reg = <0x7000e400 0x400>;
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 		clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
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 		clock-names = "pclk", "clk32k_in";
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+		#clock-cells = <1>;
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 	};
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 	fuse@7000f800 {
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@@ -642,41 +646,45 @@
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 		#nvidia,mipi-calibrate-cells = <1>;
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 	};
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-	sdhci@78000000 {
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-		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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+	mmc@78000000 {
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+		compatible = "nvidia,tegra114-sdhci";
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 		reg = <0x78000000 0x200>;
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 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 14>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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-	sdhci@78000200 {
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-		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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+	mmc@78000200 {
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+		compatible = "nvidia,tegra114-sdhci";
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 		reg = <0x78000200 0x200>;
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 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 9>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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-	sdhci@78000400 {
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-		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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+	mmc@78000400 {
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+		compatible = "nvidia,tegra114-sdhci";
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 		reg = <0x78000400 0x200>;
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 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 69>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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-	sdhci@78000600 {
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-		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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+	mmc@78000600 {
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+		compatible = "nvidia,tegra114-sdhci";
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 		reg = <0x78000600 0x200>;
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 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 15>;
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 		reset-names = "sdhci";
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 		status = "disabled";
..
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@@ -696,7 +704,8 @@
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 	phy1: usb-phy@7d000000 {
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 		compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
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-		reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
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+		reg = <0x7d000000 0x4000>,
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+		      <0x7d000000 0x4000>;
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 		phy_type = "utmi";
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 		clocks = <&tegra_car TEGRA114_CLK_USBD>,
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 			 <&tegra_car TEGRA114_CLK_PLL_U>,
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@@ -704,6 +713,7 @@
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 		clock-names = "reg", "pll_u", "utmi-pads";
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 		resets = <&tegra_car 22>, <&tegra_car 22>;
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 		reset-names = "usb", "utmi-pads";
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+		#phy-cells = <0>;
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 		nvidia,hssync-start-delay = <0>;
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 		nvidia,idle-wait-delay = <17>;
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 		nvidia,elastic-limit = <16>;
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@@ -732,7 +742,8 @@
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 	phy3: usb-phy@7d008000 {
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 		compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
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-		reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
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+		reg = <0x7d008000 0x4000>,
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+		      <0x7d000000 0x4000>;
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 		phy_type = "utmi";
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 		clocks = <&tegra_car TEGRA114_CLK_USB3>,
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 			 <&tegra_car TEGRA114_CLK_PLL_U>,
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@@ -740,6 +751,7 @@
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 		clock-names = "reg", "pll_u", "utmi-pads";
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 		resets = <&tegra_car 59>, <&tegra_car 22>;
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 		reset-names = "usb", "utmi-pads";
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+		#phy-cells = <0>;
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 		nvidia,hssync-start-delay = <0>;
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 		nvidia,idle-wait-delay = <17>;
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 		nvidia,elastic-limit = <16>;