~hc/RK356X_SDK_RELEASE.git

..	..	@@ -9,7 +9,6 @@
9	9	#include <dt-bindings/thermal/thermal.h>
10	10	#include <dt-bindings/soc/rockchip,boot-mode.h>
11	11	#include <dt-bindings/suspend/rockchip-rk3288.h>
12		-#include <dt-bindings/display/drm_mipi_dsi.h>
13	12
14	13	/ {
15	14	#address-cells = <2>;
..	..	@@ -20,7 +19,18 @@
20	19	interrupt-parent = <&gic>;
21	20
22	21	aliases {
	22	+ dsi0 = &dsi0;
	23	+ dsi1 = &dsi1;
23	24	ethernet0 = &gmac;
	25	+ gpio0 = &gpio0;
	26	+ gpio1 = &gpio1;
	27	+ gpio2 = &gpio2;
	28	+ gpio3 = &gpio3;
	29	+ gpio4 = &gpio4;
	30	+ gpio5 = &gpio5;
	31	+ gpio6 = &gpio6;
	32	+ gpio7 = &gpio7;
	33	+ gpio8 = &gpio8;
24	34	i2c0 = &i2c0;
25	35	i2c1 = &i2c1;
26	36	i2c2 = &i2c2;
..	..	@@ -39,8 +49,6 @@
39	49	spi0 = &spi0;
40	50	spi1 = &spi1;
41	51	spi2 = &spi2;
42		- dsi0 = &dsi0;
43		- dsi1 = &dsi1;
44	52	};
45	53
46	54	arm-pmu {
..	..	@@ -50,6 +58,11 @@
50	58	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
51	59	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
52	60	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	61	+ };
	62	+
	63	+ psci {
	64	+ compatible = "arm,psci-1.0";
	65	+ method = "smc";
53	66	};
54	67
55	68	cpus {
..	..	@@ -62,36 +75,53 @@
62	75	device_type = "cpu";
63	76	compatible = "arm,cortex-a12";
64	77	reg = <0x500>;
	78	+ enable-method = "psci";
65	79	resets = <&cru SRST_CORE0>;
66	80	operating-points-v2 = <&cpu_opp_table>;
67	81	#cooling-cells = <2>; /* min followed by max */
68		- dynamic-power-coefficient = <322>;
	82	+ clock-latency = <40000>;
69	83	clocks = <&cru ARMCLK>;
	84	+ dynamic-power-coefficient = <370>;
70	85	};
71	86	cpu1: cpu@501 {
72	87	device_type = "cpu";
73	88	compatible = "arm,cortex-a12";
74	89	reg = <0x501>;
	90	+ enable-method = "psci";
75	91	resets = <&cru SRST_CORE1>;
76	92	operating-points-v2 = <&cpu_opp_table>;
	93	+ #cooling-cells = <2>; /* min followed by max */
	94	+ clock-latency = <40000>;
	95	+ clocks = <&cru ARMCLK>;
	96	+ dynamic-power-coefficient = <370>;
77	97	};
78	98	cpu2: cpu@502 {
79	99	device_type = "cpu";
80	100	compatible = "arm,cortex-a12";
81	101	reg = <0x502>;
	102	+ enable-method = "psci";
82	103	resets = <&cru SRST_CORE2>;
83	104	operating-points-v2 = <&cpu_opp_table>;
	105	+ #cooling-cells = <2>; /* min followed by max */
	106	+ clock-latency = <40000>;
	107	+ clocks = <&cru ARMCLK>;
	108	+ dynamic-power-coefficient = <370>;
84	109	};
85	110	cpu3: cpu@503 {
86	111	device_type = "cpu";
87	112	compatible = "arm,cortex-a12";
88	113	reg = <0x503>;
	114	+ enable-method = "psci";
89	115	resets = <&cru SRST_CORE3>;
90	116	operating-points-v2 = <&cpu_opp_table>;
	117	+ #cooling-cells = <2>; /* min followed by max */
	118	+ clock-latency = <40000>;
	119	+ clocks = <&cru ARMCLK>;
	120	+ dynamic-power-coefficient = <370>;
91	121	};
92	122	};
93	123
94		- cpu_opp_table: opp_table0 {
	124	+ cpu_opp_table: cpu-opp-table {
95	125	compatible = "operating-points-v2";
96	126	opp-shared;
97	127
..	..	@@ -124,7 +154,7 @@
124	154	rockchip,pvtm-error = <1000>;
125	155	rockchip,pvtm-ref-temp = <35>;
126	156	rockchip,pvtm-temp-prop = <(-18) (-18)>;
127		- rockchip,thermal-zone = "soc-thermal";
	157	+ rockchip,thermal-zone = "cpu-thermal";
128	158
129	159	opp-126000000 {
130	160	opp-hz = /bits/ 64 <126000000>;
..	..	@@ -228,7 +258,7 @@
228	258	};
229	259	};
230	260
231		- amba {
	261	+ amba: bus {
232	262	compatible = "simple-bus";
233	263	#address-cells = <2>;
234	264	#size-cells = <2>;
..	..	@@ -322,7 +352,7 @@
322	352	ports = <&vopl_out>, <&vopb_out>;
323	353	};
324	354
325		- sdmmc: dwmmc@ff0c0000 {
	355	+ sdmmc: mmc@ff0c0000 {
326	356	compatible = "rockchip,rk3288-dw-mshc";
327	357	max-frequency = <150000000>;
328	358	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
..	..	@@ -336,7 +366,7 @@
336	366	status = "disabled";
337	367	};
338	368
339		- sdio0: dwmmc@ff0d0000 {
	369	+ sdio0: mmc@ff0d0000 {
340	370	compatible = "rockchip,rk3288-dw-mshc";
341	371	max-frequency = <150000000>;
342	372	clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
..	..	@@ -350,7 +380,7 @@
350	380	status = "disabled";
351	381	};
352	382
353		- sdio1: dwmmc@ff0e0000 {
	383	+ sdio1: mmc@ff0e0000 {
354	384	compatible = "rockchip,rk3288-dw-mshc";
355	385	max-frequency = <150000000>;
356	386	clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
..	..	@@ -364,7 +394,7 @@
364	394	status = "disabled";
365	395	};
366	396
367		- emmc: dwmmc@ff0f0000 {
	397	+ emmc: mmc@ff0f0000 {
368	398	compatible = "rockchip,rk3288-dw-mshc";
369	399	max-frequency = <150000000>;
370	400	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
..	..	@@ -376,7 +406,6 @@
376	406	resets = <&cru SRST_EMMC>;
377	407	reset-names = "reset";
378	408	status = "disabled";
379		- supports-emmc;
380	409	};
381	410
382	411	saradc: saradc@ff100000 {
..	..	@@ -509,6 +538,8 @@
509	538	reg-io-width = <4>;
510	539	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
511	540	clock-names = "baudclk", "apb_pclk";
	541	+ dmas = <&dmac_peri 1>, <&dmac_peri 2>;
	542	+ dma-names = "tx", "rx";
512	543	pinctrl-names = "default";
513	544	pinctrl-0 = <&uart0_xfer>;
514	545	status = "disabled";
..	..	@@ -522,6 +553,8 @@
522	553	reg-io-width = <4>;
523	554	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
524	555	clock-names = "baudclk", "apb_pclk";
	556	+ dmas = <&dmac_peri 3>, <&dmac_peri 4>;
	557	+ dma-names = "tx", "rx";
525	558	pinctrl-names = "default";
526	559	pinctrl-0 = <&uart1_xfer>;
527	560	status = "disabled";
..	..	@@ -548,6 +581,8 @@
548	581	reg-io-width = <4>;
549	582	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
550	583	clock-names = "baudclk", "apb_pclk";
	584	+ dmas = <&dmac_peri 7>, <&dmac_peri 8>;
	585	+ dma-names = "tx", "rx";
551	586	pinctrl-names = "default";
552	587	pinctrl-0 = <&uart3_xfer>;
553	588	status = "disabled";
..	..	@@ -561,31 +596,40 @@
561	596	reg-io-width = <4>;
562	597	clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
563	598	clock-names = "baudclk", "apb_pclk";
	599	+ dmas = <&dmac_peri 9>, <&dmac_peri 10>;
	600	+ dma-names = "tx", "rx";
564	601	pinctrl-names = "default";
565	602	pinctrl-0 = <&uart4_xfer>;
566	603	status = "disabled";
567	604	};
568	605
569		- thermal_zones: thermal-zones {
570		- cpu_thermal: soc-thermal {
571		- polling-delay-passive = <200>; /* milliseconds */
572		- polling-delay = <1000>; /* milliseconds */
573		- sustainable-power = <1200>; /* milliwatts */
	606	+ thermal-zones {
	607	+ reserve_thermal: reserve_thermal {
	608	+ polling-delay-passive = <1000>; /* milliseconds */
	609	+ polling-delay = <5000>; /* milliseconds */
	610	+
	611	+ thermal-sensors = <&tsadc 0>;
	612	+ };
	613	+
	614	+ cpu_thermal: cpu-thermal {
	615	+ polling-delay-passive = <100>; /* milliseconds */
	616	+ polling-delay = <5000>; /* milliseconds */
574	617
575	618	thermal-sensors = <&tsadc 1>;
	619	+
576	620	trips {
577		- cpu_alert0: trip-point@0 {
	621	+ cpu_alert0: cpu_alert0 {
	622	+ temperature = <70000>; /* millicelsius */
	623	+ hysteresis = <2000>; /* millicelsius */
	624	+ type = "passive";
	625	+ };
	626	+ cpu_alert1: cpu_alert1 {
578	627	temperature = <75000>; /* millicelsius */
579	628	hysteresis = <2000>; /* millicelsius */
580	629	type = "passive";
581	630	};
582		- cpu_alert1: trip-point@1 {
583		- temperature = <85000>; /* millicelsius */
584		- hysteresis = <2000>; /* millicelsius */
585		- type = "passive";
586		- };
587		- soc_crit: soc-crit {
588		- temperature = <115000>; /* millicelsius */
	631	+ cpu_crit: cpu_crit {
	632	+ temperature = <90000>; /* millicelsius */
589	633	hysteresis = <2000>; /* millicelsius */
590	634	type = "critical";
591	635	};
..	..	@@ -593,24 +637,50 @@
593	637
594	638	cooling-maps {
595	639	map0 {
596		- trip = <&cpu_alert1>;
	640	+ trip = <&cpu_alert0>;
597	641	cooling-device =
598		- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
599		- contribution = <1024>;
	642	+ <&cpu0 THERMAL_NO_LIMIT 6>,
	643	+ <&cpu1 THERMAL_NO_LIMIT 6>,
	644	+ <&cpu2 THERMAL_NO_LIMIT 6>,
	645	+ <&cpu3 THERMAL_NO_LIMIT 6>;
600	646	};
601	647	map1 {
602	648	trip = <&cpu_alert1>;
603	649	cooling-device =
604		- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
605		- contribution = <1024>;
	650	+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	651	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	652	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	653	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
606	654	};
607	655	};
608	656	};
609	657
610	658	gpu_thermal: gpu-thermal {
611		- polling-delay-passive = <200>; /* milliseconds */
612		- polling-delay = <1000>; /* milliseconds */
	659	+ polling-delay-passive = <100>; /* milliseconds */
	660	+ polling-delay = <5000>; /* milliseconds */
	661	+
613	662	thermal-sensors = <&tsadc 2>;
	663	+
	664	+ trips {
	665	+ gpu_alert0: gpu_alert0 {
	666	+ temperature = <70000>; /* millicelsius */
	667	+ hysteresis = <2000>; /* millicelsius */
	668	+ type = "passive";
	669	+ };
	670	+ gpu_crit: gpu_crit {
	671	+ temperature = <90000>; /* millicelsius */
	672	+ hysteresis = <2000>; /* millicelsius */
	673	+ type = "critical";
	674	+ };
	675	+ };
	676	+
	677	+ cooling-maps {
	678	+ map0 {
	679	+ trip = <&gpu_alert0>;
	680	+ cooling-device =
	681	+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	682	+ };
	683	+ };
614	684	};
615	685	};
616	686
..	..	@@ -625,11 +695,11 @@
625	695	resets = <&cru SRST_TSADC>;
626	696	reset-names = "tsadc-apb";
627	697	pinctrl-names = "gpio", "otpout";
628		- pinctrl-0 = <&otp_gpio>;
629		- pinctrl-1 = <&otp_gpio>;
	698	+ pinctrl-0 = <&otp_pin>;
	699	+ pinctrl-1 = <&otp_out>;
630	700	#thermal-sensor-cells = <1>;
631		- rockchip,hw-tshut-temp = <120000>;
632		- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
	701	+ rockchip,grf = <&grf>;
	702	+ rockchip,hw-tshut-temp = <95000>;
633	703	status = "disabled";
634	704	};
635	705
..	..	@@ -655,7 +725,7 @@
655	725
656	726	usb_host0_ehci: usb@ff500000 {
657	727	compatible = "generic-ehci";
658		- reg = <0x0 0xff500000 0x0 0x20000>;
	728	+ reg = <0x0 0xff500000 0x0 0x100>;
659	729	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
660	730	clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
661	731	clock-names = "usbhost", "utmi";
..	..	@@ -664,13 +734,10 @@
664	734	status = "disabled";
665	735	};
666	736
667		- /*
668		- * NOTE: ohci@ff520000 doesn't actually work on rk3288
669		- * hardware, but can work on rk3288w hardware.
670		- */
	737	+ /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
671	738	usb_host0_ohci: usb@ff520000 {
672	739	compatible = "generic-ohci";
673		- reg = <0x0 0xff520000 0x0 0x20000>;
	740	+ reg = <0x0 0xff520000 0x0 0x100>;
674	741	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
675	742	clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
676	743	clock-names = "usbhost", "utmi";
..	..	@@ -689,6 +756,7 @@
689	756	dr_mode = "host";
690	757	phys = <&usbphy2>;
691	758	phy-names = "usb2-phy";
	759	+ snps,reset-phy-on-wake;
692	760	status = "disabled";
693	761	};
694	762
..	..	@@ -703,7 +771,6 @@
703	771	g-np-tx-fifo-size = <16>;
704	772	g-rx-fifo-size = <280>;
705	773	g-tx-fifo-size = <256 128 128 64 32 16>;
706		- g-use-dma;
707	774	phys = <&usbphy0>;
708	775	phy-names = "usb2-phy";
709	776	status = "disabled";
..	..	@@ -714,28 +781,7 @@
714	781	reg = <0x0 0xff5c0000 0x0 0x100>;
715	782	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
716	783	clocks = <&cru HCLK_HSIC>;
717		- clock-names = "usbhost";
718	784	status = "disabled";
719		- };
720		-
721		- dmc: dmc@ff610000 {
722		- compatible = "rockchip,rk3288-dmc", "syscon";
723		- rockchip,cru = <&cru>;
724		- rockchip,grf = <&grf>;
725		- rockchip,pmu = <&pmu>;
726		- rockchip,sgrf = <&sgrf>;
727		- rockchip,noc = <&noc>;
728		- reg = <0x0 0xff610000 0x0 0x3fc
729		- 0x0 0xff620000 0x0 0x294
730		- 0x0 0xff630000 0x0 0x3fc
731		- 0x0 0xff640000 0x0 0x294>;
732		- rockchip,sram = <&ddr_sram>;
733		- clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
734		- <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
735		- <&cru ARMCLK>, <&cru ACLK_DMAC1>;
736		- clock-names = "pclk_ddrupctl0", "pclk_publ0",
737		- "pclk_ddrupctl1", "pclk_publ1",
738		- "arm_clk", "aclk_dmac1";
739	785	};
740	786
741	787	i2c2: i2c@ff660000 {
..	..	@@ -757,7 +803,7 @@
757	803	#pwm-cells = <3>;
758	804	pinctrl-names = "active";
759	805	pinctrl-0 = <&pwm0_pin>;
760		- clocks = <&cru PCLK_PWM>;
	806	+ clocks = <&cru PCLK_RKPWM>;
761	807	clock-names = "pwm";
762	808	status = "disabled";
763	809	};
..	..	@@ -768,7 +814,7 @@
768	814	#pwm-cells = <3>;
769	815	pinctrl-names = "active";
770	816	pinctrl-0 = <&pwm1_pin>;
771		- clocks = <&cru PCLK_PWM>;
	817	+ clocks = <&cru PCLK_RKPWM>;
772	818	clock-names = "pwm";
773	819	status = "disabled";
774	820	};
..	..	@@ -779,7 +825,7 @@
779	825	#pwm-cells = <3>;
780	826	pinctrl-names = "active";
781	827	pinctrl-0 = <&pwm2_pin>;
782		- clocks = <&cru PCLK_PWM>;
	828	+ clocks = <&cru PCLK_RKPWM>;
783	829	clock-names = "pwm";
784	830	status = "disabled";
785	831	};
..	..	@@ -790,7 +836,7 @@
790	836	#pwm-cells = <3>;
791	837	pinctrl-names = "active";
792	838	pinctrl-0 = <&pwm3_pin>;
793		- clocks = <&cru PCLK_PWM>;
	839	+ clocks = <&cru PCLK_RKPWM>;
794	840	clock-names = "pwm";
795	841	status = "disabled";
796	842	};
..	..	@@ -803,7 +849,7 @@
803	849	clock-names = "pclk", "timer";
804	850	};
805	851
806		- bus_intmem@ff700000 {
	852	+ bus_intmem: sram@ff700000 {
807	853	compatible = "mmio-sram";
808	854	reg = <0x0 0xff700000 0x0 0x18000>;
809	855	#address-cells = <1>;
..	..	@@ -813,85 +859,11 @@
813	859	compatible = "rockchip,rk3066-smp-sram";
814	860	reg = <0x00 0x10>;
815	861	};
816		- ddr_sram: ddr-sram@1000 {
817		- compatible = "rockchip,rk3288-ddr-sram";
818		- reg = <0x1000 0x4000>;
819		- };
820	862	};
821	863
822		- sram@ff720000 {
	864	+ pmu_sram: sram@ff720000 {
823	865	compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
824	866	reg = <0x0 0xff720000 0x0 0x1000>;
825		- };
826		-
827		- qos_gpu_r: qos@ffaa0000 {
828		- compatible = "syscon";
829		- reg = <0x0 0xffaa0000 0x0 0x20>;
830		- };
831		-
832		- qos_gpu_w: qos@ffaa0080 {
833		- compatible = "syscon";
834		- reg = <0x0 0xffaa0080 0x0 0x20>;
835		- };
836		-
837		- qos_vio1_vop: qos@ffad0000 {
838		- compatible = "syscon";
839		- reg = <0x0 0xffad0000 0x0 0x20>;
840		- };
841		-
842		- qos_vio1_isp_w0: qos@ffad0100 {
843		- compatible = "syscon";
844		- reg = <0x0 0xffad0100 0x0 0x20>;
845		- };
846		-
847		- qos_vio1_isp_w1: qos@ffad0180 {
848		- compatible = "syscon";
849		- reg = <0x0 0xffad0180 0x0 0x20>;
850		- };
851		-
852		- qos_vio0_vop: qos@ffad0400 {
853		- compatible = "syscon";
854		- reg = <0x0 0xffad0400 0x0 0x20>;
855		- };
856		-
857		- qos_vio0_vip: qos@ffad0480 {
858		- compatible = "syscon";
859		- reg = <0x0 0xffad0480 0x0 0x20>;
860		- };
861		-
862		- qos_vio0_iep: qos@ffad0500 {
863		- compatible = "syscon";
864		- reg = <0x0 0xffad0500 0x0 0x20>;
865		- };
866		-
867		- qos_vio2_rga_r: qos@ffad0800 {
868		- compatible = "syscon";
869		- reg = <0x0 0xffad0800 0x0 0x20>;
870		- };
871		-
872		- qos_vio2_rga_w: qos@ffad0880 {
873		- compatible = "syscon";
874		- reg = <0x0 0xffad0880 0x0 0x20>;
875		- };
876		-
877		- qos_vio1_isp_r: qos@ffad0900 {
878		- compatible = "syscon";
879		- reg = <0x0 0xffad0900 0x0 0x20>;
880		- };
881		-
882		- qos_video: qos@ffae0000 {
883		- compatible = "syscon";
884		- reg = <0x0 0xffae0000 0x0 0x20>;
885		- };
886		-
887		- qos_hevc_r: qos@ffaf0000 {
888		- compatible = "syscon";
889		- reg = <0x0 0xffaf0000 0x0 0x20>;
890		- };
891		-
892		- qos_hevc_w: qos@ffaf0080 {
893		- compatible = "syscon";
894		- reg = <0x0 0xffaf0080 0x0 0x20>;
895	867	};
896	868
897	869	pmu: power-management@ff730000 {
..	..	@@ -903,6 +875,9 @@
903	875	#power-domain-cells = <1>;
904	876	#address-cells = <1>;
905	877	#size-cells = <0>;
	878	+
	879	+ assigned-clocks = <&cru SCLK_EDP_24M>;
	880	+ assigned-clock-parents = <&xin24m>;
906	881
907	882	/*
908	883	* Note: Although SCLK_* are the working clocks
..	..	@@ -927,7 +902,7 @@
927	902	* *_HDMI HDMI
928	903	* _MIPI_ MIPI
929	904	*/
930		- pd_vio@RK3288_PD_VIO {
	905	+ power-domain@RK3288_PD_VIO {
931	906	reg = <RK3288_PD_VIO>;
932	907	clocks = <&cru ACLK_IEP>,
933	908	<&cru ACLK_ISP>,
..	..	@@ -970,7 +945,7 @@
970	945	* Note: The following 3 are HEVC(H.265) clocks,
971	946	* and on the ACLK_HEVC_NIU (NOC).
972	947	*/
973		- pd_hevc@RK3288_PD_HEVC {
	948	+ power-domain@RK3288_PD_HEVC {
974	949	reg = <RK3288_PD_HEVC>;
975	950	clocks = <&cru ACLK_HEVC>,
976	951	<&cru SCLK_HEVC_CABAC>,
..	..	@@ -984,7 +959,7 @@
984	959	* (video endecoder & decoder) clocks that on the
985	960	* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
986	961	*/
987		- pd_video@RK3288_PD_VIDEO {
	962	+ power-domain@RK3288_PD_VIDEO {
988	963	reg = <RK3288_PD_VIDEO>;
989	964	clocks = <&cru ACLK_VCODEC>,
990	965	<&cru HCLK_VCODEC>;
..	..	@@ -995,7 +970,7 @@
995	970	* Note: ACLK_GPU is the GPU clock,
996	971	* and on the ACLK_GPU_NIU (NOC).
997	972	*/
998		- pd_gpu@RK3288_PD_GPU {
	973	+ power-domain@RK3288_PD_GPU {
999	974	reg = <RK3288_PD_GPU>;
1000	975	clocks = <&cru ACLK_GPU>;
1001	976	pm_qos = <&qos_gpu_r>,
..	..	@@ -1003,7 +978,7 @@
1003	978	};
1004	979	};
1005	980
1006		- reboot_mode: reboot-mode {
	981	+ reboot-mode {
1007	982	compatible = "syscon-reboot-mode";
1008	983	offset = <0x94>;
1009	984	mode-normal = <BOOT_NORMAL>;
..	..	@@ -1025,35 +1000,39 @@
1025	1000	rockchip,grf = <&grf>;
1026	1001	#clock-cells = <1>;
1027	1002	#reset-cells = <1>;
1028		- assigned-clocks =
1029		- <&cru PLL_GPLL>, <&cru PLL_NPLL>,
1030		- <&cru ACLK_CPU>, <&cru HCLK_CPU>,
1031		- <&cru PCLK_CPU>, <&cru ACLK_PERI>,
1032		- <&cru HCLK_PERI>, <&cru PCLK_PERI>,
1033		- <&cru ACLK_VIO0>, <&cru ACLK_VIO1>,
1034		- <&cru ACLK_GPU>;
1035		- assigned-clock-rates =
1036		- <594000000>, <500000000>,
1037		- <300000000>, <150000000>,
1038		- <75000000>, <300000000>,
1039		- <150000000>, <75000000>,
1040		- <594000000>, <297000000>,
1041		- <200000000>;
	1003	+ assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_NPLL>,
	1004	+ <&cru ACLK_CPU>, <&cru HCLK_CPU>,
	1005	+ <&cru PCLK_CPU>, <&cru ACLK_PERI>,
	1006	+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
	1007	+ <&cru ACLK_VIO0>, <&cru ACLK_VIO1>;
	1008	+ assigned-clock-rates = <594000000>, <500000000>,
	1009	+ <300000000>, <150000000>,
	1010	+ <75000000>, <300000000>,
	1011	+ <150000000>, <75000000>,
	1012	+ <594000000>, <297000000>;
1042	1013	};
1043	1014
1044	1015	grf: syscon@ff770000 {
1045	1016	compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
1046	1017	reg = <0x0 0xff770000 0x0 0x1000>;
1047	1018
1048		- mipi_phy_rx0: mipi-phy-rx0 {
1049		- compatible = "rockchip,rk3288-mipi-dphy";
1050		- clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
1051		- clock-names = "dphy-ref", "pclk";
	1019	+ edp_phy: edp-phy {
	1020	+ compatible = "rockchip,rk3288-dp-phy";
	1021	+ clocks = <&cru SCLK_EDP_24M>;
	1022	+ clock-names = "24m";
	1023	+ #phy-cells = <0>;
1052	1024	status = "disabled";
1053	1025	};
1054	1026
1055	1027	io_domains: io-domains {
1056	1028	compatible = "rockchip,rk3288-io-voltage-domain";
	1029	+ status = "disabled";
	1030	+ };
	1031	+
	1032	+ mipi_phy_rx0: mipi-phy-rx0 {
	1033	+ compatible = "rockchip,rk3288-mipi-dphy";
	1034	+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
	1035	+ clock-names = "dphy-ref", "pclk";
1057	1036	status = "disabled";
1058	1037	};
1059	1038
..	..	@@ -1140,6 +1119,8 @@
1140	1119	clocks = <&cru SCLK_OTGPHY1>;
1141	1120	clock-names = "phyclk";
1142	1121	#clock-cells = <0>;
	1122	+ resets = <&cru SRST_USBHOST0_PHY>;
	1123	+ reset-names = "phy-reset";
1143	1124	};
1144	1125
1145	1126	usbphy2: usb-phy@348 {
..	..	@@ -1188,8 +1169,8 @@
1188	1169	compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1189	1170	reg = <0x0 0xff880000 0x0 0x10000>;
1190	1171	#sound-dai-cells = <0>;
1191		- clock-names = "hclk", "mclk";
1192		- clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
	1172	+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
	1173	+ clock-names = "mclk", "hclk";
1193	1174	dmas = <&dmac_bus_s 2>;
1194	1175	dma-names = "tx";
1195	1176	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1204,14 +1185,12 @@
1204	1185	reg = <0x0 0xff890000 0x0 0x10000>;
1205	1186	#sound-dai-cells = <0>;
1206	1187	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1207		- #address-cells = <1>;
1208		- #size-cells = <0>;
1209		- dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1210		- dma-names = "tx", "rx";
1211		- clock-names = "i2s_hclk", "i2s_clk";
1212		- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	1188	+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
	1189	+ clock-names = "i2s_clk", "i2s_hclk";
1213	1190	assigned-clocks = <&cru SCLK_I2S_SRC>;
1214	1191	assigned-clock-parents = <&cru PLL_GPLL>;
	1192	+ dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
	1193	+ dma-names = "tx", "rx";
1215	1194	pinctrl-names = "default";
1216	1195	pinctrl-0 = <&i2s0_bus>;
1217	1196	resets = <&cru SRST_I2S0>;
..	..	@@ -1231,7 +1210,7 @@
1231	1210	status = "disabled";
1232	1211	};
1233	1212
1234		- crypto: cypto-controller@ff8a0000 {
	1213	+ crypto: crypto@ff8a0000 {
1235	1214	compatible = "rockchip,rk3288-crypto";
1236	1215	reg = <0x0 0xff8a0000 0x0 0x4000>;
1237	1216	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1247,8 +1226,8 @@
1247	1226	compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1248	1227	reg = <0x0 0xff8b0000 0x0 0x10000>;
1249	1228	#sound-dai-cells = <0>;
1250		- clock-names = "hclk", "mclk";
1251		- clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
	1229	+ clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
	1230	+ clock-names = "mclk", "hclk";
1252	1231	dmas = <&dmac_bus_s 3>;
1253	1232	dma-names = "tx";
1254	1233	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1280,29 +1259,6 @@
1280	1259	clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1281	1260	clock-names = "aclk", "iface";
1282	1261	#iommu-cells = <0>;
1283		- status = "disabled";
1284		- };
1285		-
1286		- cif_isp0: cif_isp@ff910000 {
1287		- compatible = "rockchip,rk3288-cif-isp";
1288		- rockchip,grf = <&grf>;
1289		- reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1290		- reg-names = "register", "csihost-register";
1291		- clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1292		- <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1293		- <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1294		- <&cru SCLK_MIPIDSI_24M>;
1295		- clock-names = "aclk_isp", "hclk_isp",
1296		- "sclk_isp", "sclk_isp_jpe",
1297		- "pclk_mipi_csi", "pclk_isp_in",
1298		- "sclk_mipidsi_24m";
1299		- resets = <&cru SRST_ISP>;
1300		- reset-names = "rst_isp";
1301		- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1302		- interrupt-names = "cif_isp10_irq";
1303		- power-domains = <&power RK3288_PD_VIO>;
1304		- rockchip,isp,iommu-enable = <1>;
1305		- iommus = <&isp_mmu>;
1306	1262	status = "disabled";
1307	1263	};
1308	1264
..	..	@@ -1420,14 +1376,14 @@
1420	1376	remote-endpoint = <&dsi0_in_vopb>;
1421	1377	};
1422	1378
1423		- vopb_out_lvds: endpoint@3 {
	1379	+ vopb_out_dsi1: endpoint@3 {
1424	1380	reg = <3>;
1425		- remote-endpoint = <&lvds_in_vopb>;
	1381	+ remote-endpoint = <&dsi1_in_vopb>;
1426	1382	};
1427	1383
1428		- vopb_out_dsi1: endpoint@4 {
	1384	+ vopb_out_lvds: endpoint@4 {
1429	1385	reg = <4>;
1430		- remote-endpoint = <&dsi1_in_vopb>;
	1386	+ remote-endpoint = <&lvds_in_vopb>;
1431	1387	};
1432	1388
1433	1389	vopb_out_rgb: endpoint@5 {
..	..	@@ -1482,14 +1438,14 @@
1482	1438	remote-endpoint = <&dsi0_in_vopl>;
1483	1439	};
1484	1440
1485		- vopl_out_lvds: endpoint@3 {
	1441	+ vopl_out_dsi1: endpoint@3 {
1486	1442	reg = <3>;
1487		- remote-endpoint = <&lvds_in_vopl>;
	1443	+ remote-endpoint = <&dsi1_in_vopl>;
1488	1444	};
1489	1445
1490		- vopl_out_dsi1: endpoint@4 {
	1446	+ vopl_out_lvds: endpoint@4 {
1491	1447	reg = <4>;
1492		- remote-endpoint = <&dsi1_in_vopl>;
	1448	+ remote-endpoint = <&lvds_in_vopl>;
1493	1449	};
1494	1450
1495	1451	vopl_out_rgb: endpoint@5 {
..	..	@@ -1606,7 +1562,7 @@
1606	1562	status = "disabled";
1607	1563	};
1608	1564
1609		- edp: edp@ff970000 {
	1565	+ edp: dp@ff970000 {
1610	1566	compatible = "rockchip,rk3288-dp";
1611	1567	reg = <0x0 0xff970000 0x0 0x4000>;
1612	1568	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1624,17 +1580,14 @@
1624	1580	ports {
1625	1581	#address-cells = <1>;
1626	1582	#size-cells = <0>;
1627		-
1628		- port@0 {
	1583	+ edp_in: port@0 {
1629	1584	reg = <0>;
1630	1585	#address-cells = <1>;
1631	1586	#size-cells = <0>;
1632		-
1633	1587	edp_in_vopb: endpoint@0 {
1634	1588	reg = <0>;
1635	1589	remote-endpoint = <&vopb_out_edp>;
1636	1590	};
1637		-
1638	1591	edp_in_vopl: endpoint@1 {
1639	1592	reg = <1>;
1640	1593	remote-endpoint = <&vopl_out_edp>;
..	..	@@ -1673,6 +1626,19 @@
1673	1626	};
1674	1627	};
1675	1628	};
	1629	+ };
	1630	+
	1631	+ vpu: video-codec@ff9a0000 {
	1632	+ compatible = "rockchip,rk3288-vpu";
	1633	+ reg = <0x0 0xff9a0000 0x0 0x800>;
	1634	+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	1635	+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	1636	+ interrupt-names = "vepu", "vdpu";
	1637	+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	1638	+ clock-names = "aclk", "hclk";
	1639	+ iommus = <&vpu_mmu>;
	1640	+ power-domains = <&power RK3288_PD_VIDEO>;
	1641	+ status = "disabled";
1676	1642	};
1677	1643
1678	1644	mpp_srv: mpp-srv {
..	..	@@ -1729,8 +1695,8 @@
1729	1695	interrupt-names = "vpu_mmu";
1730	1696	clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1731	1697	clock-names = "aclk", "iface";
1732		- power-domains = <&power RK3288_PD_VIDEO>;
1733	1698	#iommu-cells = <0>;
	1699	+ power-domains = <&power RK3288_PD_VIDEO>;
1734	1700	status = "disabled";
1735	1701	};
1736	1702
..	..	@@ -1770,8 +1736,7 @@
1770	1736
1771	1737	hevc_mmu: iommu@ff9c0440 {
1772	1738	compatible = "rockchip,iommu";
1773		- reg = <0x0 0xff9c0440 0x0 0x40>,
1774		- <0x0 0xff9c0480 0x0 0x40>;
	1739	+ reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1775	1740	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1776	1741	interrupt-names = "hevc_mmu";
1777	1742	clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
..	..	@@ -1782,15 +1747,14 @@
1782	1747	};
1783	1748
1784	1749	gpu: gpu@ffa30000 {
1785		- compatible = "arm,malit764",
1786		- "arm,malit76x",
1787		- "arm,malit7xx",
	1750	+ compatible = "rockchip,rk3288-mali", "arm,mali-t760",
	1751	+ "arm,malit764", "arm,malit76x", "arm,malit7xx",
1788	1752	"arm,mali-midgard";
1789	1753	reg = <0x0 0xffa30000 0x0 0x10000>;
1790	1754	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1791	1755	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1792	1756	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1793		- interrupt-names = "JOB", "MMU", "GPU";
	1757	+ interrupt-names = "job", "mmu", "gpu";
1794	1758	clocks = <&cru ACLK_GPU>;
1795	1759	clock-names = "clk_mali";
1796	1760	operating-points-v2 = <&gpu_opp_table>;
..	..	@@ -1810,7 +1774,7 @@
1810	1774	};
1811	1775	};
1812	1776
1813		- gpu_opp_table: opp-table1 {
	1777	+ gpu_opp_table: gpu-opp-table {
1814	1778	compatible = "operating-points-v2";
1815	1779
1816	1780	clocks = <&cru PLL_GPLL>;
..	..	@@ -1823,6 +1787,10 @@
1823	1787	3 61
1824	1788	>;
1825	1789
	1790	+ opp-100000000 {
	1791	+ opp-hz = /bits/ 64 <100000000>;
	1792	+ opp-microvolt = <950000>;
	1793	+ };
1826	1794	opp-200000000 {
1827	1795	opp-hz = /bits/ 64 <200000000>;
1828	1796	opp-microvolt = <950000>;
..	..	@@ -1835,54 +1803,84 @@
1835	1803	opp-hz = /bits/ 64 <420000000>;
1836	1804	opp-microvolt = <1100000>;
1837	1805	};
1838		- opp-500000000 {
1839		- opp-hz = /bits/ 64 <500000000>;
1840		- opp-microvolt = <1200000>;
	1806	+ opp-600000000 {
	1807	+ opp-hz = /bits/ 64 <600000000>;
	1808	+ opp-microvolt = <1250000>;
1841	1809	};
1842	1810	};
1843	1811
1844		- noc: syscon@ffac0000 {
1845		- compatible = "rockchip,rk3288-noc", "syscon";
1846		- reg = <0x0 0xffac0000 0x0 0x2000>;
	1812	+ qos_gpu_r: qos@ffaa0000 {
	1813	+ compatible = "syscon";
	1814	+ reg = <0x0 0xffaa0000 0x0 0x20>;
1847	1815	};
1848	1816
1849		- nocp_core: nocp-core@ffac0400 {
1850		- compatible = "rockchip,rk3288-nocp";
1851		- reg = <0x0 0xffac0400 0x0 0x400>;
	1817	+ qos_gpu_w: qos@ffaa0080 {
	1818	+ compatible = "syscon";
	1819	+ reg = <0x0 0xffaa0080 0x0 0x20>;
1852	1820	};
1853	1821
1854		- nocp_gpu: nocp-gpu@ffac0800 {
1855		- compatible = "rockchip,rk3288-nocp";
1856		- reg = <0x0 0xffac0800 0x0 0x400>;
	1822	+ qos_vio1_vop: qos@ffad0000 {
	1823	+ compatible = "syscon";
	1824	+ reg = <0x0 0xffad0000 0x0 0x20>;
1857	1825	};
1858	1826
1859		- nocp_peri: nocp-peri@ffac0c00 {
1860		- compatible = "rockchip,rk3288-nocp";
1861		- reg = <0x0 0xffac0c00 0x0 0x400>;
	1827	+ qos_vio1_isp_w0: qos@ffad0100 {
	1828	+ compatible = "syscon";
	1829	+ reg = <0x0 0xffad0100 0x0 0x20>;
1862	1830	};
1863	1831
1864		- nocp_vpu: nocp-vpu@ffac1000 {
1865		- compatible = "rockchip,rk3288-nocp";
1866		- reg = <0x0 0xffac1000 0x0 0x400>;
	1832	+ qos_vio1_isp_w1: qos@ffad0180 {
	1833	+ compatible = "syscon";
	1834	+ reg = <0x0 0xffad0180 0x0 0x20>;
1867	1835	};
1868	1836
1869		- nocp_vio0: nocp-vio0@ffac1400 {
1870		- compatible = "rockchip,rk3288-nocp";
1871		- reg = <0x0 0xffac1400 0x0 0x400>;
	1837	+ qos_vio0_vop: qos@ffad0400 {
	1838	+ compatible = "syscon";
	1839	+ reg = <0x0 0xffad0400 0x0 0x20>;
1872	1840	};
1873	1841
1874		- nocp_vio1: nocp-vio1@ffac1800 {
1875		- compatible = "rockchip,rk3288-nocp";
1876		- reg = <0x0 0xffac1800 0x0 0x400>;
	1842	+ qos_vio0_vip: qos@ffad0480 {
	1843	+ compatible = "syscon";
	1844	+ reg = <0x0 0xffad0480 0x0 0x20>;
1877	1845	};
1878	1846
1879		- nocp_vio2: nocp-vio2@ffac1c00 {
1880		- compatible = "rockchip,rk3288-nocp";
1881		- reg = <0x0 0xffac1c00 0x0 0x400>;
	1847	+ qos_vio0_iep: qos@ffad0500 {
	1848	+ compatible = "syscon";
	1849	+ reg = <0x0 0xffad0500 0x0 0x20>;
	1850	+ };
	1851	+
	1852	+ qos_vio2_rga_r: qos@ffad0800 {
	1853	+ compatible = "syscon";
	1854	+ reg = <0x0 0xffad0800 0x0 0x20>;
	1855	+ };
	1856	+
	1857	+ qos_vio2_rga_w: qos@ffad0880 {
	1858	+ compatible = "syscon";
	1859	+ reg = <0x0 0xffad0880 0x0 0x20>;
	1860	+ };
	1861	+
	1862	+ qos_vio1_isp_r: qos@ffad0900 {
	1863	+ compatible = "syscon";
	1864	+ reg = <0x0 0xffad0900 0x0 0x20>;
	1865	+ };
	1866	+
	1867	+ qos_video: qos@ffae0000 {
	1868	+ compatible = "syscon";
	1869	+ reg = <0x0 0xffae0000 0x0 0x20>;
	1870	+ };
	1871	+
	1872	+ qos_hevc_r: qos@ffaf0000 {
	1873	+ compatible = "syscon";
	1874	+ reg = <0x0 0xffaf0000 0x0 0x20>;
	1875	+ };
	1876	+
	1877	+ qos_hevc_w: qos@ffaf0080 {
	1878	+ compatible = "syscon";
	1879	+ reg = <0x0 0xffaf0080 0x0 0x20>;
1882	1880	};
1883	1881
1884	1882	efuse: efuse@ffb40000 {
1885		- compatible = "rockchip,rockchip-efuse";
	1883	+ compatible = "rockchip,rk3288-efuse";
1886	1884	reg = <0x0 0xffb40000 0x0 0x20>;
1887	1885	#address-cells = <1>;
1888	1886	#size-cells = <1>;
..	..	@@ -1901,10 +1899,10 @@
1901	1899	reg = <0x6 0x1>;
1902	1900	bits = <0 4>;
1903	1901	};
1904		- efuse_id: id@7 {
1905		- reg = <0x7 0x10>;
	1902	+ cpu_id: cpu-id@7 {
	1903	+ reg = <0x07 0x10>;
1906	1904	};
1907		- cpu_leakage: cpu-leakage@17 {
	1905	+ cpu_leakage: cpu_leakage@17 {
1908	1906	reg = <0x17 0x1>;
1909	1907	};
1910	1908	performance_w: performance@1c {
..	..	@@ -1932,6 +1930,30 @@
1932	1930
1933	1931	rockchip_system_monitor: rockchip-system-monitor {
1934	1932	compatible = "rockchip,system-monitor";
	1933	+ };
	1934	+
	1935	+ rockchip_suspend: rockchip-suspend {
	1936	+ compatible = "rockchip,pm-rk3288";
	1937	+ status = "disabled";
	1938	+ rockchip,sleep-mode-config = <
	1939	+ (0
	1940	+ \|RKPM_CTR_PWR_DMNS
	1941	+ \|RKPM_CTR_GTCLKS
	1942	+ \|RKPM_CTR_PLLS
	1943	+ \|RKPM_CTR_ARMOFF_LPMD
	1944	+ \|RKPM_CTR_SYSCLK_OSC_DIS
	1945	+ )
	1946	+ >;
	1947	+ rockchip,wakeup-config = <
	1948	+ (0
	1949	+ \| RKPM_GPIO_WKUP_EN
	1950	+ )
	1951	+ >;
	1952	+ rockchip,pwm-regulator-config = <
	1953	+ (0
	1954	+ \| PWM2_REGULATOR_EN
	1955	+ )
	1956	+ >;
1935	1957	};
1936	1958
1937	1959	pinctrl: pinctrl {
..	..	@@ -2059,616 +2081,11 @@
2059	2081	#interrupt-cells = <2>;
2060	2082	};
2061	2083
2062		- hdmi {
2063		- hdmi_gpio: hdmi-gpio {
2064		- rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO
2065		- &pcfg_pull_none>,
2066		- <7 RK_PC4 RK_FUNC_GPIO
2067		- &pcfg_pull_none>;
2068		- };
2069		-
2070		- hdmi_cec: hdmi-cec {
2071		- rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
2072		- };
2073		-
2074		- hdmi_ddc: hdmi-ddc {
2075		- rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
2076		- <7 RK_PC4 2 &pcfg_pull_none>;
2077		- };
2078		- };
2079		-
2080		- pcfg_pull_up: pcfg-pull-up {
2081		- bias-pull-up;
2082		- };
2083		-
2084		- pcfg_pull_down: pcfg-pull-down {
2085		- bias-pull-down;
2086		- };
2087		-
2088		- pcfg_pull_none: pcfg-pull-none {
2089		- bias-disable;
2090		- };
2091		-
2092	2084	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2093	2085	bias-disable;
2094	2086	drive-strength = <12>;
2095	2087	};
2096		-
2097		- suspend {
2098		- global_pwroff: global-pwroff {
2099		- rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
2100		- };
2101		-
2102		- ddrio_pwroff: ddrio-pwroff {
2103		- rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2104		- };
2105		-
2106		- ddr0_retention: ddr0-retention {
2107		- rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
2108		- };
2109		-
2110		- ddr1_retention: ddr1-retention {
2111		- rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
2112		- };
2113		- };
2114		-
2115		- edp {
2116		- edp_hpd: edp-hpd {
2117		- rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
2118		- };
2119		- };
2120		-
2121		- i2c0 {
2122		- i2c0_xfer: i2c0-xfer {
2123		- rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
2124		- <0 RK_PC0 1 &pcfg_pull_none>;
2125		- };
2126		- };
2127		-
2128		- i2c1 {
2129		- i2c1_xfer: i2c1-xfer {
2130		- rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
2131		- <8 RK_PA5 1 &pcfg_pull_none>;
2132		- };
2133		- };
2134		-
2135		- i2c2 {
2136		- i2c2_xfer: i2c2-xfer {
2137		- rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
2138		- <6 RK_PB2 1 &pcfg_pull_none>;
2139		- };
2140		- };
2141		-
2142		- i2c3 {
2143		- i2c3_xfer: i2c3-xfer {
2144		- rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
2145		- <2 RK_PC1 1 &pcfg_pull_none>;
2146		- };
2147		- };
2148		-
2149		- i2c4 {
2150		- i2c4_xfer: i2c4-xfer {
2151		- rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
2152		- <7 RK_PC2 1 &pcfg_pull_none>;
2153		- };
2154		- };
2155		-
2156		- i2c5 {
2157		- i2c5_xfer: i2c5-xfer {
2158		- rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
2159		- <7 RK_PC4 1 &pcfg_pull_none>;
2160		- };
2161		- };
2162		-
2163		- i2s0 {
2164		- i2s0_bus: i2s0-bus {
2165		- rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
2166		- <6 RK_PA1 1 &pcfg_pull_none>,
2167		- <6 RK_PA2 1 &pcfg_pull_none>,
2168		- <6 RK_PA3 1 &pcfg_pull_none>,
2169		- <6 RK_PA4 1 &pcfg_pull_none>;
2170		- };
2171		-
2172		- i2s0_mclk: i2s0-mclk {
2173		- rockchip,pins = <6 RK_PB0 1 &pcfg_pull_none>;
2174		- };
2175		- };
2176		-
2177		- lcdc {
2178		- lcdc_rgb_pins: lcdc-rgb-pins {
2179		- rockchip,pins = <1 RK_PD3 1 &pcfg_pull_none>, /* LCDC_DCLK */
2180		- <1 RK_PD2 1 &pcfg_pull_none>, /* LCDC_DEN */
2181		- <1 RK_PD1 1 &pcfg_pull_none>, /* LCDC_VSYNC */
2182		- <1 RK_PD0 1 &pcfg_pull_none>; /* LCDC_HSYNC */
2183		- };
2184		-
2185		- lcdc_sleep_pins: lcdc-sleep-pins {
2186		- rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */
2187		- <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */
2188		- <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */
2189		- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_HSYNC */
2190		- };
2191		- };
2192		-
2193		- sdmmc {
2194		- sdmmc_clk: sdmmc-clk {
2195		- rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
2196		- };
2197		-
2198		- sdmmc_cmd: sdmmc-cmd {
2199		- rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
2200		- };
2201		-
2202		- sdmmc_cd: sdmmc-cd {
2203		- rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
2204		- };
2205		-
2206		- sdmmc_bus1: sdmmc-bus1 {
2207		- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
2208		- };
2209		-
2210		- sdmmc_bus4: sdmmc-bus4 {
2211		- rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
2212		- <6 RK_PC1 1 &pcfg_pull_up>,
2213		- <6 RK_PC2 1 &pcfg_pull_up>,
2214		- <6 RK_PC3 1 &pcfg_pull_up>;
2215		- };
2216		- };
2217		-
2218		- sdio0 {
2219		- sdio0_bus1: sdio0-bus1 {
2220		- rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
2221		- };
2222		-
2223		- sdio0_bus4: sdio0-bus4 {
2224		- rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
2225		- <4 RK_PC5 1 &pcfg_pull_up>,
2226		- <4 RK_PC6 1 &pcfg_pull_up>,
2227		- <4 RK_PC7 1 &pcfg_pull_up>;
2228		- };
2229		-
2230		- sdio0_cmd: sdio0-cmd {
2231		- rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
2232		- };
2233		-
2234		- sdio0_clk: sdio0-clk {
2235		- rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
2236		- };
2237		-
2238		- sdio0_cd: sdio0-cd {
2239		- rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
2240		- };
2241		-
2242		- sdio0_wp: sdio0-wp {
2243		- rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
2244		- };
2245		-
2246		- sdio0_pwr: sdio0-pwr {
2247		- rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
2248		- };
2249		-
2250		- sdio0_bkpwr: sdio0-bkpwr {
2251		- rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
2252		- };
2253		-
2254		- sdio0_int: sdio0-int {
2255		- rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
2256		- };
2257		- };
2258		-
2259		- sdio1 {
2260		- sdio1_bus1: sdio1-bus1 {
2261		- rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
2262		- };
2263		-
2264		- sdio1_bus4: sdio1-bus4 {
2265		- rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
2266		- <3 RK_PD1 4 &pcfg_pull_up>,
2267		- <3 RK_PD2 4 &pcfg_pull_up>,
2268		- <3 RK_PD3 4 &pcfg_pull_up>;
2269		- };
2270		-
2271		- sdio1_cd: sdio1-cd {
2272		- rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
2273		- };
2274		-
2275		- sdio1_wp: sdio1-wp {
2276		- rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
2277		- };
2278		-
2279		- sdio1_bkpwr: sdio1-bkpwr {
2280		- rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
2281		- };
2282		-
2283		- sdio1_int: sdio1-int {
2284		- rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
2285		- };
2286		-
2287		- sdio1_cmd: sdio1-cmd {
2288		- rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
2289		- };
2290		-
2291		- sdio1_clk: sdio1-clk {
2292		- rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
2293		- };
2294		-
2295		- sdio1_pwr: sdio1-pwr {
2296		- rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
2297		- };
2298		- };
2299		-
2300		- emmc {
2301		- emmc_clk: emmc-clk {
2302		- rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
2303		- };
2304		-
2305		- emmc_cmd: emmc-cmd {
2306		- rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
2307		- };
2308		-
2309		- emmc_pwr: emmc-pwr {
2310		- rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
2311		- };
2312		-
2313		- emmc_bus1: emmc-bus1 {
2314		- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
2315		- };
2316		-
2317		- emmc_bus4: emmc-bus4 {
2318		- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
2319		- <3 RK_PA1 2 &pcfg_pull_up>,
2320		- <3 RK_PA2 2 &pcfg_pull_up>,
2321		- <3 RK_PA3 2 &pcfg_pull_up>;
2322		- };
2323		-
2324		- emmc_bus8: emmc-bus8 {
2325		- rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
2326		- <3 RK_PA1 2 &pcfg_pull_up>,
2327		- <3 RK_PA2 2 &pcfg_pull_up>,
2328		- <3 RK_PA3 2 &pcfg_pull_up>,
2329		- <3 RK_PA4 2 &pcfg_pull_up>,
2330		- <3 RK_PA5 2 &pcfg_pull_up>,
2331		- <3 RK_PA6 2 &pcfg_pull_up>,
2332		- <3 RK_PA7 2 &pcfg_pull_up>;
2333		- };
2334		- };
2335		-
2336		- spi0 {
2337		- spi0_clk: spi0-clk {
2338		- rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
2339		- };
2340		- spi0_cs0: spi0-cs0 {
2341		- rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
2342		- };
2343		- spi0_tx: spi0-tx {
2344		- rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
2345		- };
2346		- spi0_rx: spi0-rx {
2347		- rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
2348		- };
2349		- spi0_cs1: spi0-cs1 {
2350		- rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
2351		- };
2352		- };
2353		- spi1 {
2354		- spi1_clk: spi1-clk {
2355		- rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
2356		- };
2357		- spi1_cs0: spi1-cs0 {
2358		- rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
2359		- };
2360		- spi1_rx: spi1-rx {
2361		- rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
2362		- };
2363		- spi1_tx: spi1-tx {
2364		- rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
2365		- };
2366		- };
2367		-
2368		- spi2 {
2369		- spi2_cs1: spi2-cs1 {
2370		- rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
2371		- };
2372		- spi2_clk: spi2-clk {
2373		- rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
2374		- };
2375		- spi2_cs0: spi2-cs0 {
2376		- rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
2377		- };
2378		- spi2_rx: spi2-rx {
2379		- rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
2380		- };
2381		- spi2_tx: spi2-tx {
2382		- rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
2383		- };
2384		- };
2385		-
2386		- uart0 {
2387		- uart0_xfer: uart0-xfer {
2388		- rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
2389		- <4 RK_PC1 1 &pcfg_pull_up>;
2390		- };
2391		-
2392		- uart0_cts: uart0-cts {
2393		- rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
2394		- };
2395		-
2396		- uart0_rts: uart0-rts {
2397		- rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
2398		- };
2399		- };
2400		-
2401		- uart1 {
2402		- uart1_xfer: uart1-xfer {
2403		- rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
2404		- <5 RK_PB1 1 &pcfg_pull_up>;
2405		- };
2406		-
2407		- uart1_cts: uart1-cts {
2408		- rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
2409		- };
2410		-
2411		- uart1_rts: uart1-rts {
2412		- rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
2413		- };
2414		- };
2415		-
2416		- uart2 {
2417		- uart2_xfer: uart2-xfer {
2418		- rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
2419		- <7 RK_PC7 1 &pcfg_pull_up>;
2420		- };
2421		- /* no rts / cts for uart2 */
2422		- };
2423		-
2424		- uart3 {
2425		- uart3_xfer: uart3-xfer {
2426		- rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
2427		- <7 RK_PB0 1 &pcfg_pull_up>;
2428		- };
2429		-
2430		- uart3_cts: uart3-cts {
2431		- rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
2432		- };
2433		-
2434		- uart3_rts: uart3-rts {
2435		- rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
2436		- };
2437		- };
2438		-
2439		- uart4 {
2440		- uart4_xfer: uart4-xfer {
2441		- rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
2442		- <5 RK_PB6 3 &pcfg_pull_up>;
2443		- };
2444		-
2445		- uart4_cts: uart4-cts {
2446		- rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
2447		- };
2448		-
2449		- uart4_rts: uart4-rts {
2450		- rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
2451		- };
2452		- };
2453		-
2454		- tsadc {
2455		- otp_gpio: otp-gpio {
2456		- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
2457		- };
2458		-
2459		- otp_out: otp-out {
2460		- rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
2461		- };
2462		- };
2463		-
2464		- pwm0 {
2465		- pwm0_pin: pwm0-pin {
2466		- rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
2467		- };
2468		-
2469		- pwm0_pin_pull_down: pwm0-pin-pull-down {
2470		- rockchip,pins = <7 RK_PA0 1 &pcfg_pull_down>;
2471		- };
2472		-
2473		- };
2474		-
2475		- pwm1 {
2476		- pwm1_pin: pwm1-pin {
2477		- rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
2478		- };
2479		-
2480		- pwm1_pin_pull_down: pwm1-pin-pull-down {
2481		- rockchip,pins = <7 RK_PA1 1 &pcfg_pull_down>;
2482		- };
2483		- };
2484		-
2485		- pwm2 {
2486		- pwm2_pin: pwm2-pin {
2487		- rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
2488		- };
2489		-
2490		- pwm2_pin_pull_down: pwm2-pin-pull-down {
2491		- rockchip,pins = <7 RK_PC6 3 &pcfg_pull_down>;
2492		- };
2493		- };
2494		-
2495		- pwm3 {
2496		- pwm3_pin: pwm3-pin {
2497		- rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
2498		- };
2499		-
2500		- pwm3_pin_pull_down: pwm3-pin-pull-down {
2501		- rockchip,pins = <7 RK_PC7 3 &pcfg_pull_down>;
2502		- };
2503		- };
2504		-
2505		- gmac {
2506		- rgmii_pins: rgmii-pins {
2507		- rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
2508		- <3 RK_PD7 3 &pcfg_pull_none>,
2509		- <3 RK_PD2 3 &pcfg_pull_none>,
2510		- <3 RK_PD3 3 &pcfg_pull_none>,
2511		- <3 RK_PD4 3 &pcfg_pull_none_12ma>,
2512		- <3 RK_PD5 3 &pcfg_pull_none_12ma>,
2513		- <3 RK_PD0 3 &pcfg_pull_none_12ma>,
2514		- <3 RK_PD1 3 &pcfg_pull_none_12ma>,
2515		- <4 RK_PA0 3 &pcfg_pull_none>,
2516		- <4 RK_PA5 3 &pcfg_pull_none>,
2517		- <4 RK_PA6 3 &pcfg_pull_none>,
2518		- <4 RK_PB1 3 &pcfg_pull_none_12ma>,
2519		- <4 RK_PA4 3 &pcfg_pull_none_12ma>,
2520		- <4 RK_PA1 3 &pcfg_pull_none>,
2521		- <4 RK_PA3 3 &pcfg_pull_none>;
2522		- };
2523		-
2524		- rmii_pins: rmii-pins {
2525		- rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
2526		- <3 RK_PD7 3 &pcfg_pull_none>,
2527		- <3 RK_PD4 3 &pcfg_pull_none>,
2528		- <3 RK_PD5 3 &pcfg_pull_none>,
2529		- <4 RK_PA0 3 &pcfg_pull_none>,
2530		- <4 RK_PA5 3 &pcfg_pull_none>,
2531		- <4 RK_PA4 3 &pcfg_pull_none>,
2532		- <4 RK_PA1 3 &pcfg_pull_none>,
2533		- <4 RK_PA2 3 &pcfg_pull_none>,
2534		- <4 RK_PA3 3 &pcfg_pull_none>;
2535		- };
2536		- };
2537		-
2538		- spdif {
2539		- spdif_tx: spdif-tx {
2540		- rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
2541		- };
2542		- };
2543		-
2544		- isp_pin {
2545		- isp_mipi: isp-mipi {
2546		- rockchip,pins =
2547		- /* cif_clkout */
2548		- <2 RK_PB3 1 &pcfg_pull_none>;
2549		- };
2550		-
2551		- isp_dvp_d2d9: isp-d2d9 {
2552		- rockchip,pins =
2553		- /* cif_data2 ... cif_data9 */
2554		- <2 RK_PA0 1 &pcfg_pull_none>,
2555		- <2 RK_PA1 1 &pcfg_pull_none>,
2556		- <2 RK_PA2 1 &pcfg_pull_none>,
2557		- <2 RK_PA3 1 &pcfg_pull_none>,
2558		- <2 RK_PA4 1 &pcfg_pull_none>,
2559		- <2 RK_PA5 1 &pcfg_pull_none>,
2560		- <2 RK_PA6 1 &pcfg_pull_none>,
2561		- <2 RK_PA7 1 &pcfg_pull_none>,
2562		- /* cif_sync, cif_href */
2563		- <2 RK_PB0 1 &pcfg_pull_none>,
2564		- <2 RK_PB1 1 &pcfg_pull_none>,
2565		- /* cif_clkin */
2566		- <2 RK_PB2 1 &pcfg_pull_none>;
2567		- };
2568		-
2569		- isp_dvp_d0d1: isp-d0d1 {
2570		- rockchip,pins =
2571		- /* cif_data0, cif_data1 */
2572		- <2 RK_PB4 1 &pcfg_pull_none>,
2573		- <2 RK_PB5 1 &pcfg_pull_none>;
2574		- };
2575		-
2576		- isp_dvp_d10d11: isp-d10d11 {
2577		- rockchip,pins =
2578		- /* cif_data10, cif_data11 */
2579		- <2 RK_PB6 1 &pcfg_pull_none>,
2580		- <2 RK_PB7 1 &pcfg_pull_none>;
2581		- };
2582		-
2583		- isp_dvp_d0d7: isp-d0d7 {
2584		- rockchip,pins =
2585		- /* cif_data0 ... cif_data7 */
2586		- <2 RK_PB4 1 &pcfg_pull_none>,
2587		- <2 RK_PB5 1 &pcfg_pull_none>,
2588		- <2 RK_PA0 1 &pcfg_pull_none>,
2589		- <2 RK_PA1 1 &pcfg_pull_none>,
2590		- <2 RK_PA2 1 &pcfg_pull_none>,
2591		- <2 RK_PA3 1 &pcfg_pull_none>,
2592		- <2 RK_PA4 1 &pcfg_pull_none>,
2593		- <2 RK_PA5 1 &pcfg_pull_none>;
2594		- };
2595		-
2596		- isp_shutter: isp-shutter {
2597		- rockchip,pins =
2598		- /* SHUTTEREN, SHUTTERTRIG */
2599		- <7 RK_PB4 2 &pcfg_pull_none>,
2600		- <7 RK_PB7 2 &pcfg_pull_none>;
2601		- };
2602		-
2603		- isp_flash_trigger: isp-flash-trigger {
2604		- rockchip,pins =
2605		- /* ISP_FLASHTRIGOU */
2606		- <7 RK_PB5 2 &pcfg_pull_none>;
2607		- };
2608		-
2609		- isp_prelight: isp-prelight {
2610		- rockchip,pins =
2611		- /* ISP_PRELIGHTTRIG */
2612		- <7 RK_PB6 2 &pcfg_pull_none>;
2613		- };
2614		-
2615		- isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
2616		- rockchip,pins =
2617		- /* ISP_FLASHTRIGOU */
2618		- <7 RK_PB5 2 &pcfg_pull_none>;
2619		- };
2620		- };
2621		-
2622		- cif_pin {
2623		- cif_dvp_d0d1: cif-dvp-d0d1 {
2624		- rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2625		- <2 RK_PB5 1 &pcfg_pull_none>; /* cif_data1 */
2626		- };
2627		-
2628		- cif_dvp_d2d9: cif-dvp-d2d9 {
2629		- rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2630		- <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2631		- <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2632		- <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2633		- <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2634		- <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2635		- <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2636		- <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2637		- <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2638		- <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2639		- <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2640		- <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2641		- };
2642		-
2643		- cif_dvp_d10d11: cif-dvp-d10d11 {
2644		- rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, /* cif_data10 */
2645		- <2 RK_PB7 1 &pcfg_pull_none>; /* cif_data11 */
2646		- };
2647		- };
2648		-
2649		- };
2650		-
2651		- rockchip_suspend: rockchip-suspend {
2652		- compatible = "rockchip,pm-rk3288";
2653		- status = "disabled";
2654		- rockchip,sleep-mode-config = <
2655		- (0
2656		- \|RKPM_CTR_PWR_DMNS
2657		- \|RKPM_CTR_GTCLKS
2658		- \|RKPM_CTR_PLLS
2659		- \|RKPM_CTR_ARMOFF_LPMD
2660		- \|RKPM_CTR_SYSCLK_OSC_DIS
2661		- )
2662		- >;
2663		- rockchip,wakeup-config = <
2664		- (0
2665		- \| RKPM_GPIO_WKUP_EN
2666		- )
2667		- >;
2668		- rockchip,pwm-regulator-config = <
2669		- (0
2670		- \| PWM2_REGULATOR_EN
2671		- )
2672		- >;
2673	2088	};
2674	2089	};
	2090	+
	2091	+#include "rk3288-pinctrl.dtsi"