forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 
 kernel/arch/arm/boot/dts/rk3066a.dtsi
....@@ -7,10 +7,20 @@
77 #include <dt-bindings/gpio/gpio.h>
88 #include <dt-bindings/pinctrl/rockchip.h>
99 #include <dt-bindings/clock/rk3066a-cru.h>
10
+#include <dt-bindings/power/rk3066-power.h>
1011 #include "rk3xxx.dtsi"
1112 
1213 / {
1314 	compatible = "rockchip,rk3066a";
15
+
16
+	aliases {
17
+		gpio0 = &gpio0;
18
+		gpio1 = &gpio1;
19
+		gpio2 = &gpio2;
20
+		gpio3 = &gpio3;
21
+		gpio4 = &gpio4;
22
+		gpio6 = &gpio6;
23
+	};
1424 
1525 	cpus {
1626 		#address-cells = <1>;
....@@ -25,7 +35,7 @@
2535 			operating-points-v2 = <&cpu0_opp_table>;
2636 			clocks = <&cru ARMCLK>;
2737 		};
28
-		cpu@1 {
38
+		cpu1: cpu@1 {
2939 			device_type = "cpu";
3040 			compatible = "arm,cortex-a9";
3141 			next-level-cache = <&L2>;
....@@ -62,6 +72,11 @@
6272 			clock-latency-ns = <40000>;
6373 			status = "disabled";
6474 		};
75
+	};
76
+
77
+	display-subsystem {
78
+		compatible = "rockchip,display-subsystem";
79
+		ports = <&vop0_out>, <&vop1_out>;
6580 	};
6681 
6782 	sram: sram@10080000 {
....@@ -162,6 +177,7 @@
162177 			 <&cru DCLK_LCDC0>,
163178 			 <&cru HCLK_LCDC0>;
164179 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
180
+		power-domains = <&power RK3066_PD_VIO>;
165181 		resets = <&cru SRST_LCDC0_AXI>,
166182 			 <&cru SRST_LCDC0_AHB>,
167183 			 <&cru SRST_LCDC0_DCLK>;
....@@ -171,6 +187,7 @@
171187 		vop0_out: port {
172188 			#address-cells = <1>;
173189 			#size-cells = <0>;
190
+
174191 			vop0_out_hdmi: endpoint@0 {
175192 				reg = <0>;
176193 				remote-endpoint = <&hdmi_in_vop0>;
....@@ -186,6 +203,7 @@
186203 			 <&cru DCLK_LCDC1>,
187204 			 <&cru HCLK_LCDC1>;
188205 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
206
+		power-domains = <&power RK3066_PD_VIO>;
189207 		resets = <&cru SRST_LCDC1_AXI>,
190208 			 <&cru SRST_LCDC1_AHB>,
191209 			 <&cru SRST_LCDC1_DCLK>;
....@@ -195,12 +213,12 @@
195213 		vop1_out: port {
196214 			#address-cells = <1>;
197215 			#size-cells = <0>;
198
-		};
199
-	};
200216 
201
-	display-subsystem {
202
-		compatible = "rockchip,display-subsystem";
203
-		ports = <&vop0_out>, <&vop1_out>;
217
+			vop1_out_hdmi: endpoint@0 {
218
+				reg = <0>;
219
+				remote-endpoint = <&hdmi_in_vop1>;
220
+			};
221
+		};
204222 	};
205223 
206224 	hdmi: hdmi@10116000 {
....@@ -209,17 +227,34 @@
209227 		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
210228 		clocks = <&cru HCLK_HDMI>;
211229 		clock-names = "hclk";
212
-		rockchip,grf = <&grf>;
213230 		pinctrl-names = "default";
214231 		pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
232
+		power-domains = <&power RK3066_PD_VIO>;
233
+		rockchip,grf = <&grf>;
215234 		status = "disabled";
216235 
217
-		hdmi_in: port {
236
+		ports {
218237 			#address-cells = <1>;
219238 			#size-cells = <0>;
220
-			hdmi_in_vop0: endpoint@0 {
239
+
240
+			hdmi_in: port@0 {
221241 				reg = <0>;
222
-				remote-endpoint = <&vop0_out_hdmi>;
242
+				#address-cells = <1>;
243
+				#size-cells = <0>;
244
+
245
+				hdmi_in_vop0: endpoint@0 {
246
+					reg = <0>;
247
+					remote-endpoint = <&vop0_out_hdmi>;
248
+				};
249
+
250
+				hdmi_in_vop1: endpoint@1 {
251
+					reg = <1>;
252
+					remote-endpoint = <&vop1_out_hdmi>;
253
+				};
254
+			};
255
+
256
+			hdmi_out: port@1 {
257
+				reg = <1>;
223258 			};
224259 		};
225260 	};
....@@ -228,8 +263,6 @@
228263 		compatible = "rockchip,rk3066-i2s";
229264 		reg = <0x10118000 0x2000>;
230265 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
231
-		#address-cells = <1>;
232
-		#size-cells = <0>;
233266 		pinctrl-names = "default";
234267 		pinctrl-0 = <&i2s0_bus>;
235268 		dmas = <&dmac1_s 4>, <&dmac1_s 5>;
....@@ -240,6 +273,7 @@
240273 		reset-names = "reset-m";
241274 		rockchip,playback-channels = <8>;
242275 		rockchip,capture-channels = <2>;
276
+		#sound-dai-cells = <0>;
243277 		status = "disabled";
244278 	};
245279 
....@@ -247,8 +281,6 @@
247281 		compatible = "rockchip,rk3066-i2s";
248282 		reg = <0x1011a000 0x2000>;
249283 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
250
-		#address-cells = <1>;
251
-		#size-cells = <0>;
252284 		pinctrl-names = "default";
253285 		pinctrl-0 = <&i2s1_bus>;
254286 		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
....@@ -259,6 +291,7 @@
259291 		reset-names = "reset-m";
260292 		rockchip,playback-channels = <2>;
261293 		rockchip,capture-channels = <2>;
294
+		#sound-dai-cells = <0>;
262295 		status = "disabled";
263296 	};
264297 
....@@ -266,8 +299,6 @@
266299 		compatible = "rockchip,rk3066-i2s";
267300 		reg = <0x1011c000 0x2000>;
268301 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
269
-		#address-cells = <1>;
270
-		#size-cells = <0>;
271302 		pinctrl-names = "default";
272303 		pinctrl-0 = <&i2s2_bus>;
273304 		dmas = <&dmac1_s 9>, <&dmac1_s 10>;
....@@ -278,6 +309,7 @@
278309 		reset-names = "reset-m";
279310 		rockchip,playback-channels = <2>;
280311 		rockchip,capture-channels = <2>;
312
+		#sound-dai-cells = <0>;
281313 		status = "disabled";
282314 	};
283315 
....@@ -387,6 +419,7 @@
387419 			compatible = "rockchip,gpio-bank";
388420 			reg = <0x20034000 0x100>;
389421 			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
422
+			clock-names = "bus";
390423 			clocks = <&cru PCLK_GPIO0>;
391424 
392425 			gpio-controller;
....@@ -400,6 +433,7 @@
400433 			compatible = "rockchip,gpio-bank";
401434 			reg = <0x2003c000 0x100>;
402435 			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
436
+			clock-names = "bus";
403437 			clocks = <&cru PCLK_GPIO1>;
404438 
405439 			gpio-controller;
....@@ -413,6 +447,7 @@
413447 			compatible = "rockchip,gpio-bank";
414448 			reg = <0x2003e000 0x100>;
415449 			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
450
+			clock-names = "bus";
416451 			clocks = <&cru PCLK_GPIO2>;
417452 
418453 			gpio-controller;
....@@ -426,6 +461,7 @@
426461 			compatible = "rockchip,gpio-bank";
427462 			reg = <0x20080000 0x100>;
428463 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
464
+			clock-names = "bus";
429465 			clocks = <&cru PCLK_GPIO3>;
430466 
431467 			gpio-controller;
....@@ -439,6 +475,7 @@
439475 			compatible = "rockchip,gpio-bank";
440476 			reg = <0x20084000 0x100>;
441477 			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
478
+			clock-names = "bus";
442479 			clocks = <&cru PCLK_GPIO4>;
443480 
444481 			gpio-controller;
....@@ -452,6 +489,7 @@
452489 			compatible = "rockchip,gpio-bank";
453490 			reg = <0x2000a000 0x100>;
454491 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
492
+			clock-names = "bus";
455493 			clocks = <&cru PCLK_GPIO6>;
456494 
457495 			gpio-controller;
....@@ -463,10 +501,6 @@
463501 
464502 		pcfg_pull_default: pcfg_pull_default {
465503 			bias-pull-pin-default;
466
-		};
467
-
468
-		pcfg_pull_up: pcfg-pull-up {
469
-			bias-pull-up;
470504 		};
471505 
472506 		pcfg_pull_none: pcfg_pull_none {
....@@ -510,6 +544,17 @@
510544 			 * been already set correctly by firmware, as
511545 			 * flash/emmc is the boot-device.
512546 			 */
547
+		};
548
+
549
+		hdmi {
550
+			hdmi_hpd: hdmi-hpd {
551
+				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
552
+			};
553
+
554
+			hdmii2c_xfer: hdmii2c-xfer {
555
+				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
556
+						<0 RK_PA2 1 &pcfg_pull_none>;
557
+			};
513558 		};
514559 
515560 		i2c0 {
....@@ -609,8 +654,8 @@
609654 
610655 		uart0 {
611656 			uart0_xfer: uart0-xfer {
612
-				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
613
-						<1 RK_PA1 1 &pcfg_pull_up>;
657
+				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
658
+						<1 RK_PA1 1 &pcfg_pull_default>;
614659 			};
615660 
616661 			uart0_cts: uart0-cts {
....@@ -624,8 +669,8 @@
624669 
625670 		uart1 {
626671 			uart1_xfer: uart1-xfer {
627
-				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
628
-						<1 RK_PA5 1 &pcfg_pull_up>;
672
+				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
673
+						<1 RK_PA5 1 &pcfg_pull_default>;
629674 			};
630675 
631676 			uart1_cts: uart1-cts {
....@@ -639,16 +684,16 @@
639684 
640685 		uart2 {
641686 			uart2_xfer: uart2-xfer {
642
-				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
643
-						<1 RK_PB1 1 &pcfg_pull_up>;
687
+				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
688
+						<1 RK_PB1 1 &pcfg_pull_default>;
644689 			};
645690 			/* no rts / cts for uart2 */
646691 		};
647692 
648693 		uart3 {
649694 			uart3_xfer: uart3-xfer {
650
-				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_up>,
651
-						<3 RK_PD4 1 &pcfg_pull_up>;
695
+				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
696
+						<3 RK_PD4 1 &pcfg_pull_default>;
652697 			};
653698 
654699 			uart3_cts: uart3-cts {
....@@ -753,16 +798,6 @@
753798 						<0 RK_PD5 1 &pcfg_pull_default>;
754799 			};
755800 		};
756
-
757
-		hdmi {
758
-			hdmi_hpd: hdmi-hpd {
759
-				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
760
-			};
761
-			hdmii2c_xfer: hdmii2c-xfer {
762
-				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
763
-						<0 RK_PA2 1 &pcfg_pull_none>;
764
-			};
765
-		};
766801 	};
767802 };
768803 
....@@ -788,6 +823,7 @@
788823 			  "ppmmu2",
789824 			  "pp3",
790825 			  "ppmmu3";
826
+	power-domains = <&power RK3066_PD_GPU>;
791827 };
792828 
793829 &i2c0 {
....@@ -836,6 +872,57 @@
836872 	dma-names = "rx-tx";
837873 };
838874 
875
+&pmu {
876
+	power: power-controller {
877
+		compatible = "rockchip,rk3066-power-controller";
878
+		#power-domain-cells = <1>;
879
+		#address-cells = <1>;
880
+		#size-cells = <0>;
881
+
882
+		power-domain@RK3066_PD_VIO {
883
+			reg = <RK3066_PD_VIO>;
884
+			clocks = <&cru ACLK_LCDC0>,
885
+				 <&cru ACLK_LCDC1>,
886
+				 <&cru DCLK_LCDC0>,
887
+				 <&cru DCLK_LCDC1>,
888
+				 <&cru HCLK_LCDC0>,
889
+				 <&cru HCLK_LCDC1>,
890
+				 <&cru SCLK_CIF1>,
891
+				 <&cru ACLK_CIF1>,
892
+				 <&cru HCLK_CIF1>,
893
+				 <&cru SCLK_CIF0>,
894
+				 <&cru ACLK_CIF0>,
895
+				 <&cru HCLK_CIF0>,
896
+				 <&cru HCLK_HDMI>,
897
+				 <&cru ACLK_IPP>,
898
+				 <&cru HCLK_IPP>,
899
+				 <&cru ACLK_RGA>,
900
+				 <&cru HCLK_RGA>;
901
+			pm_qos = <&qos_lcdc0>,
902
+				 <&qos_lcdc1>,
903
+				 <&qos_cif0>,
904
+				 <&qos_cif1>,
905
+				 <&qos_ipp>,
906
+				 <&qos_rga>;
907
+		};
908
+
909
+		power-domain@RK3066_PD_VIDEO {
910
+			reg = <RK3066_PD_VIDEO>;
911
+			clocks = <&cru ACLK_VDPU>,
912
+				 <&cru ACLK_VEPU>,
913
+				 <&cru HCLK_VDPU>,
914
+				 <&cru HCLK_VEPU>;
915
+			pm_qos = <&qos_vpu>;
916
+		};
917
+
918
+		power-domain@RK3066_PD_GPU {
919
+			reg = <RK3066_PD_GPU>;
920
+			clocks = <&cru ACLK_GPU>;
921
+			pm_qos = <&qos_gpu>;
922
+		};
923
+	};
924
+};
925
+
839926 &pwm0 {
840927 	pinctrl-names = "active";
841928 	pinctrl-0 = <&pwm0_out>;