add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/boot/dts/rk3066a.dtsi
..
..
@@ -7,10 +7,20 @@
7
7
 #include <dt-bindings/gpio/gpio.h>
8
8
 #include <dt-bindings/pinctrl/rockchip.h>
9
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 #include <dt-bindings/clock/rk3066a-cru.h>
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+#include <dt-bindings/power/rk3066-power.h>
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 #include "rk3xxx.dtsi"
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12
 
12
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 / {
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 	compatible = "rockchip,rk3066a";
15
+
16
+	aliases {
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+		gpio0 = &gpio0;
18
+		gpio1 = &gpio1;
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+		gpio2 = &gpio2;
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+		gpio3 = &gpio3;
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+		gpio4 = &gpio4;
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+		gpio6 = &gpio6;
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+	};
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24
 
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 	cpus {
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 		#address-cells = <1>;
..
..
@@ -25,7 +35,7 @@
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 			operating-points-v2 = <&cpu0_opp_table>;
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 			clocks = <&cru ARMCLK>;
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 		};
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-		cpu@1 {
38
+		cpu1: cpu@1 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			next-level-cache = <&L2>;
..
..
@@ -62,6 +72,11 @@
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 			clock-latency-ns = <40000>;
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 			status = "disabled";
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 		};
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+	};
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+
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+	display-subsystem {
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+		compatible = "rockchip,display-subsystem";
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+		ports = <&vop0_out>, <&vop1_out>;
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 	};
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81
 
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 	sram: sram@10080000 {
..
..
@@ -162,6 +177,7 @@
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 			 <&cru DCLK_LCDC0>,
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 			 <&cru HCLK_LCDC0>;
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 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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+		power-domains = <&power RK3066_PD_VIO>;
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 		resets = <&cru SRST_LCDC0_AXI>,
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 			 <&cru SRST_LCDC0_AHB>,
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 			 <&cru SRST_LCDC0_DCLK>;
..
..
@@ -171,6 +187,7 @@
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 		vop0_out: port {
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 			#address-cells = <1>;
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 			#size-cells = <0>;
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+
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 			vop0_out_hdmi: endpoint@0 {
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 				reg = <0>;
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 				remote-endpoint = <&hdmi_in_vop0>;
..
..
@@ -186,6 +203,7 @@
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 			 <&cru DCLK_LCDC1>,
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 			 <&cru HCLK_LCDC1>;
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 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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+		power-domains = <&power RK3066_PD_VIO>;
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 		resets = <&cru SRST_LCDC1_AXI>,
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 			 <&cru SRST_LCDC1_AHB>,
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 			 <&cru SRST_LCDC1_DCLK>;
..
..
@@ -195,12 +213,12 @@
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 		vop1_out: port {
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 			#address-cells = <1>;
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 			#size-cells = <0>;
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-		};
199
-	};
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216
 
201
-	display-subsystem {
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-		compatible = "rockchip,display-subsystem";
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-		ports = <&vop0_out>, <&vop1_out>;
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+			vop1_out_hdmi: endpoint@0 {
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+				reg = <0>;
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+				remote-endpoint = <&hdmi_in_vop1>;
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+			};
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+		};
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222
 	};
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223
 
206
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 	hdmi: hdmi@10116000 {
..
..
@@ -209,17 +227,34 @@
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 		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&cru HCLK_HDMI>;
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 		clock-names = "hclk";
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-		rockchip,grf = <&grf>;
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 		pinctrl-names = "default";
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 		pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
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+		power-domains = <&power RK3066_PD_VIO>;
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+		rockchip,grf = <&grf>;
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234
 		status = "disabled";
216
235
 
217
-		hdmi_in: port {
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+		ports {
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 			#address-cells = <1>;
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 			#size-cells = <0>;
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-			hdmi_in_vop0: endpoint@0 {
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+
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+			hdmi_in: port@0 {
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 				reg = <0>;
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-				remote-endpoint = <&vop0_out_hdmi>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
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+				hdmi_in_vop0: endpoint@0 {
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+					reg = <0>;
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+					remote-endpoint = <&vop0_out_hdmi>;
248
+				};
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+
250
+				hdmi_in_vop1: endpoint@1 {
251
+					reg = <1>;
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+					remote-endpoint = <&vop1_out_hdmi>;
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+				};
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+			};
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+
256
+			hdmi_out: port@1 {
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+				reg = <1>;
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 			};
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 		};
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 	};
..
..
@@ -228,8 +263,6 @@
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 		compatible = "rockchip,rk3066-i2s";
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 		reg = <0x10118000 0x2000>;
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 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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 		pinctrl-names = "default";
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 		pinctrl-0 = <&i2s0_bus>;
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 		dmas = <&dmac1_s 4>, <&dmac1_s 5>;
..
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@@ -240,6 +273,7 @@
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 		reset-names = "reset-m";
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 		rockchip,playback-channels = <8>;
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 		rockchip,capture-channels = <2>;
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+		#sound-dai-cells = <0>;
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 		status = "disabled";
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 	};
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..
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@@ -247,8 +281,6 @@
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 		compatible = "rockchip,rk3066-i2s";
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 		reg = <0x1011a000 0x2000>;
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 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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 		pinctrl-names = "default";
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 		pinctrl-0 = <&i2s1_bus>;
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 		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
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@@ -259,6 +291,7 @@
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 		reset-names = "reset-m";
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 		rockchip,playback-channels = <2>;
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 		rockchip,capture-channels = <2>;
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+		#sound-dai-cells = <0>;
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 		status = "disabled";
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 	};
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..
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@@ -266,8 +299,6 @@
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 		compatible = "rockchip,rk3066-i2s";
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 		reg = <0x1011c000 0x2000>;
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 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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 		pinctrl-names = "default";
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 		pinctrl-0 = <&i2s2_bus>;
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 		dmas = <&dmac1_s 9>, <&dmac1_s 10>;
..
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@@ -278,6 +309,7 @@
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 		reset-names = "reset-m";
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 		rockchip,playback-channels = <2>;
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 		rockchip,capture-channels = <2>;
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+		#sound-dai-cells = <0>;
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 		status = "disabled";
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 	};
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315
 
..
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@@ -387,6 +419,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x20034000 0x100>;
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 			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
422
+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO0>;
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424
 
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 			gpio-controller;
..
..
@@ -400,6 +433,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x2003c000 0x100>;
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 			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO1>;
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 			gpio-controller;
..
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@@ -413,6 +447,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x2003e000 0x100>;
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 			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO2>;
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452
 
418
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 			gpio-controller;
..
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@@ -426,6 +461,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x20080000 0x100>;
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 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO3>;
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431
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 			gpio-controller;
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@@ -439,6 +475,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x20084000 0x100>;
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 			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
478
+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO4>;
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480
 
444
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 			gpio-controller;
..
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@@ -452,6 +489,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x2000a000 0x100>;
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 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO6>;
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494
 
457
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 			gpio-controller;
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@@ -506,6 +544,17 @@
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 			 * been already set correctly by firmware, as
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 			 * flash/emmc is the boot-device.
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 			 */
547
+		};
548
+
549
+		hdmi {
550
+			hdmi_hpd: hdmi-hpd {
551
+				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
552
+			};
553
+
554
+			hdmii2c_xfer: hdmii2c-xfer {
555
+				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
556
+						<0 RK_PA2 1 &pcfg_pull_none>;
557
+			};
509
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 		};
510
559
 
511
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 		i2c0 {
..
..
@@ -749,16 +798,6 @@
749
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 						<0 RK_PD5 1 &pcfg_pull_default>;
750
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 			};
751
800
 		};
752
-
753
-		hdmi {
754
-			hdmi_hpd: hdmi-hpd {
755
-				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
756
-			};
757
-			hdmii2c_xfer: hdmii2c-xfer {
758
-				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
759
-						<0 RK_PA2 1 &pcfg_pull_none>;
760
-			};
761
-		};
762
801
 	};
763
802
 };
764
803
 
..
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@@ -784,6 +823,7 @@
784
823
 			  "ppmmu2",
785
824
 			  "pp3",
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 			  "ppmmu3";
826
+	power-domains = <&power RK3066_PD_GPU>;
787
827
 };
788
828
 
789
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 &i2c0 {
..
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@@ -832,6 +872,57 @@
832
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 	dma-names = "rx-tx";
833
873
 };
834
874
 
875
+&pmu {
876
+	power: power-controller {
877
+		compatible = "rockchip,rk3066-power-controller";
878
+		#power-domain-cells = <1>;
879
+		#address-cells = <1>;
880
+		#size-cells = <0>;
881
+
882
+		power-domain@RK3066_PD_VIO {
883
+			reg = <RK3066_PD_VIO>;
884
+			clocks = <&cru ACLK_LCDC0>,
885
+				 <&cru ACLK_LCDC1>,
886
+				 <&cru DCLK_LCDC0>,
887
+				 <&cru DCLK_LCDC1>,
888
+				 <&cru HCLK_LCDC0>,
889
+				 <&cru HCLK_LCDC1>,
890
+				 <&cru SCLK_CIF1>,
891
+				 <&cru ACLK_CIF1>,
892
+				 <&cru HCLK_CIF1>,
893
+				 <&cru SCLK_CIF0>,
894
+				 <&cru ACLK_CIF0>,
895
+				 <&cru HCLK_CIF0>,
896
+				 <&cru HCLK_HDMI>,
897
+				 <&cru ACLK_IPP>,
898
+				 <&cru HCLK_IPP>,
899
+				 <&cru ACLK_RGA>,
900
+				 <&cru HCLK_RGA>;
901
+			pm_qos = <&qos_lcdc0>,
902
+				 <&qos_lcdc1>,
903
+				 <&qos_cif0>,
904
+				 <&qos_cif1>,
905
+				 <&qos_ipp>,
906
+				 <&qos_rga>;
907
+		};
908
+
909
+		power-domain@RK3066_PD_VIDEO {
910
+			reg = <RK3066_PD_VIDEO>;
911
+			clocks = <&cru ACLK_VDPU>,
912
+				 <&cru ACLK_VEPU>,
913
+				 <&cru HCLK_VDPU>,
914
+				 <&cru HCLK_VEPU>;
915
+			pm_qos = <&qos_vpu>;
916
+		};
917
+
918
+		power-domain@RK3066_PD_GPU {
919
+			reg = <RK3066_PD_GPU>;
920
+			clocks = <&cru ACLK_GPU>;
921
+			pm_qos = <&qos_gpu>;
922
+		};
923
+	};
924
+};
925
+
835
926
 &pwm0 {
836
927
 	pinctrl-names = "active";
837
928
 	pinctrl-0 = <&pwm0_out>;