.. | .. |
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7 | 7 | */ |
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8 | 8 | |
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9 | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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| 10 | +#include <dt-bindings/clock/r9a06g032-sysctrl.h> |
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10 | 11 | |
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11 | 12 | / { |
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12 | 13 | compatible = "renesas,r9a06g032"; |
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.. | .. |
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21 | 22 | device_type = "cpu"; |
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22 | 23 | compatible = "arm,cortex-a7"; |
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23 | 24 | reg = <0>; |
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24 | | - clocks = <&sysctrl 84>; |
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| 25 | + clocks = <&sysctrl R9A06G032_CLK_A7MP>; |
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25 | 26 | }; |
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26 | 27 | |
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27 | 28 | cpu@1 { |
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28 | 29 | device_type = "cpu"; |
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29 | 30 | compatible = "arm,cortex-a7"; |
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30 | 31 | reg = <1>; |
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31 | | - clocks = <&sysctrl 84>; |
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| 32 | + clocks = <&sysctrl R9A06G032_CLK_A7MP>; |
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32 | 33 | enable-method = "renesas,r9a06g032-smp"; |
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33 | 34 | cpu-release-addr = <0 0x4000c204>; |
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34 | 35 | }; |
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.. | .. |
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77 | 78 | }; |
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78 | 79 | |
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79 | 80 | uart0: serial@40060000 { |
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80 | | - compatible = "snps,dw-apb-uart"; |
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| 81 | + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; |
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81 | 82 | reg = <0x40060000 0x400>; |
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82 | 83 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
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83 | 84 | reg-shift = <2>; |
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84 | 85 | reg-io-width = <4>; |
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85 | | - clocks = <&sysctrl 146>; |
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86 | | - clock-names = "baudclk"; |
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| 86 | + clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; |
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| 87 | + clock-names = "baudclk", "apb_pclk"; |
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87 | 88 | status = "disabled"; |
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88 | 89 | }; |
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89 | 90 | |
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90 | | - gic: gic@44101000 { |
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91 | | - compatible = "arm,cortex-a7-gic", "arm,gic-400"; |
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| 91 | + uart1: serial@40061000 { |
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| 92 | + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; |
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| 93 | + reg = <0x40061000 0x400>; |
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| 94 | + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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| 95 | + reg-shift = <2>; |
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| 96 | + reg-io-width = <4>; |
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| 97 | + clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; |
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| 98 | + clock-names = "baudclk", "apb_pclk"; |
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| 99 | + status = "disabled"; |
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| 100 | + }; |
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| 101 | + |
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| 102 | + uart2: serial@40062000 { |
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| 103 | + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; |
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| 104 | + reg = <0x40062000 0x400>; |
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| 105 | + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
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| 106 | + reg-shift = <2>; |
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| 107 | + reg-io-width = <4>; |
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| 108 | + clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; |
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| 109 | + clock-names = "baudclk", "apb_pclk"; |
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| 110 | + status = "disabled"; |
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| 111 | + }; |
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| 112 | + |
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| 113 | + uart3: serial@50000000 { |
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| 114 | + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; |
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| 115 | + reg = <0x50000000 0x400>; |
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| 116 | + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
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| 117 | + reg-shift = <2>; |
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| 118 | + reg-io-width = <4>; |
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| 119 | + clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; |
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| 120 | + clock-names = "baudclk", "apb_pclk"; |
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| 121 | + status = "disabled"; |
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| 122 | + }; |
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| 123 | + |
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| 124 | + uart4: serial@50001000 { |
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| 125 | + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; |
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| 126 | + reg = <0x50001000 0x400>; |
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| 127 | + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
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| 128 | + reg-shift = <2>; |
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| 129 | + reg-io-width = <4>; |
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| 130 | + clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; |
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| 131 | + clock-names = "baudclk", "apb_pclk"; |
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| 132 | + status = "disabled"; |
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| 133 | + }; |
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| 134 | + |
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| 135 | + uart5: serial@50002000 { |
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| 136 | + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; |
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| 137 | + reg = <0x50002000 0x400>; |
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| 138 | + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
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| 139 | + reg-shift = <2>; |
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| 140 | + reg-io-width = <4>; |
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| 141 | + clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; |
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| 142 | + clock-names = "baudclk", "apb_pclk"; |
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| 143 | + status = "disabled"; |
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| 144 | + }; |
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| 145 | + |
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| 146 | + uart6: serial@50003000 { |
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| 147 | + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; |
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| 148 | + reg = <0x50003000 0x400>; |
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| 149 | + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
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| 150 | + reg-shift = <2>; |
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| 151 | + reg-io-width = <4>; |
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| 152 | + clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; |
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| 153 | + clock-names = "baudclk", "apb_pclk"; |
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| 154 | + status = "disabled"; |
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| 155 | + }; |
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| 156 | + |
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| 157 | + uart7: serial@50004000 { |
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| 158 | + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; |
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| 159 | + reg = <0x50004000 0x400>; |
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| 160 | + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
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| 161 | + reg-shift = <2>; |
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| 162 | + reg-io-width = <4>; |
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| 163 | + clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; |
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| 164 | + clock-names = "baudclk", "apb_pclk"; |
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| 165 | + status = "disabled"; |
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| 166 | + }; |
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| 167 | + |
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| 168 | + pinctrl: pinctrl@40067000 { |
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| 169 | + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; |
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| 170 | + reg = <0x40067000 0x1000>, <0x51000000 0x480>; |
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| 171 | + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; |
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| 172 | + clock-names = "bus"; |
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| 173 | + status = "okay"; |
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| 174 | + }; |
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| 175 | + |
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| 176 | + gic: interrupt-controller@44101000 { |
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| 177 | + compatible = "arm,gic-400", "arm,cortex-a7-gic"; |
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92 | 178 | interrupt-controller; |
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93 | 179 | #interrupt-cells = <3>; |
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94 | 180 | reg = <0x44101000 0x1000>, /* Distributer */ |
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