forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2
kernel/arch/arm/boot/dts/r9a06g032.dtsi
....@@ -7,6 +7,7 @@
77 */
88
99 #include <dt-bindings/interrupt-controller/arm-gic.h>
10
+#include <dt-bindings/clock/r9a06g032-sysctrl.h>
1011
1112 / {
1213 compatible = "renesas,r9a06g032";
....@@ -21,14 +22,14 @@
2122 device_type = "cpu";
2223 compatible = "arm,cortex-a7";
2324 reg = <0>;
24
- clocks = <&sysctrl 84>;
25
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
2526 };
2627
2728 cpu@1 {
2829 device_type = "cpu";
2930 compatible = "arm,cortex-a7";
3031 reg = <1>;
31
- clocks = <&sysctrl 84>;
32
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
3233 enable-method = "renesas,r9a06g032-smp";
3334 cpu-release-addr = <0 0x4000c204>;
3435 };
....@@ -77,18 +78,103 @@
7778 };
7879
7980 uart0: serial@40060000 {
80
- compatible = "snps,dw-apb-uart";
81
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
8182 reg = <0x40060000 0x400>;
8283 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
8384 reg-shift = <2>;
8485 reg-io-width = <4>;
85
- clocks = <&sysctrl 146>;
86
- clock-names = "baudclk";
86
+ clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
87
+ clock-names = "baudclk", "apb_pclk";
8788 status = "disabled";
8889 };
8990
90
- gic: gic@44101000 {
91
- compatible = "arm,cortex-a7-gic", "arm,gic-400";
91
+ uart1: serial@40061000 {
92
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
93
+ reg = <0x40061000 0x400>;
94
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
95
+ reg-shift = <2>;
96
+ reg-io-width = <4>;
97
+ clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
98
+ clock-names = "baudclk", "apb_pclk";
99
+ status = "disabled";
100
+ };
101
+
102
+ uart2: serial@40062000 {
103
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
104
+ reg = <0x40062000 0x400>;
105
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
106
+ reg-shift = <2>;
107
+ reg-io-width = <4>;
108
+ clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
109
+ clock-names = "baudclk", "apb_pclk";
110
+ status = "disabled";
111
+ };
112
+
113
+ uart3: serial@50000000 {
114
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
115
+ reg = <0x50000000 0x400>;
116
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
117
+ reg-shift = <2>;
118
+ reg-io-width = <4>;
119
+ clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
120
+ clock-names = "baudclk", "apb_pclk";
121
+ status = "disabled";
122
+ };
123
+
124
+ uart4: serial@50001000 {
125
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
126
+ reg = <0x50001000 0x400>;
127
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
128
+ reg-shift = <2>;
129
+ reg-io-width = <4>;
130
+ clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
131
+ clock-names = "baudclk", "apb_pclk";
132
+ status = "disabled";
133
+ };
134
+
135
+ uart5: serial@50002000 {
136
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
137
+ reg = <0x50002000 0x400>;
138
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
139
+ reg-shift = <2>;
140
+ reg-io-width = <4>;
141
+ clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
142
+ clock-names = "baudclk", "apb_pclk";
143
+ status = "disabled";
144
+ };
145
+
146
+ uart6: serial@50003000 {
147
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
148
+ reg = <0x50003000 0x400>;
149
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
150
+ reg-shift = <2>;
151
+ reg-io-width = <4>;
152
+ clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
153
+ clock-names = "baudclk", "apb_pclk";
154
+ status = "disabled";
155
+ };
156
+
157
+ uart7: serial@50004000 {
158
+ compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
159
+ reg = <0x50004000 0x400>;
160
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
161
+ reg-shift = <2>;
162
+ reg-io-width = <4>;
163
+ clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
164
+ clock-names = "baudclk", "apb_pclk";
165
+ status = "disabled";
166
+ };
167
+
168
+ pinctrl: pinctrl@40067000 {
169
+ compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
170
+ reg = <0x40067000 0x1000>, <0x51000000 0x480>;
171
+ clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
172
+ clock-names = "bus";
173
+ status = "okay";
174
+ };
175
+
176
+ gic: interrupt-controller@44101000 {
177
+ compatible = "arm,gic-400", "arm,cortex-a7-gic";
92178 interrupt-controller;
93179 #interrupt-cells = <3>;
94180 reg = <0x44101000 0x1000>, /* Distributer */