add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
..
..
@@ -46,6 +46,8 @@
46
46
  */
47
47
 
48
48
 #include <dt-bindings/gpio/gpio.h>
49
+#include <dt-bindings/input/linux-event-codes.h>
50
+#include <dt-bindings/interrupt-controller/irq.h>
49
51
 
50
52
 / {
51
53
 	/* these are used by bootloader for disabling nodes */
..
..
@@ -59,6 +61,51 @@
59
61
 
60
62
 	chosen {
61
63
 		stdout-path = &uart2;
64
+	};
65
+
66
+	gpio-keys {
67
+		compatible = "gpio-keys";
68
+
69
+		user-pb {
70
+			label = "user_pb";
71
+			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
72
+			linux,code = <BTN_0>;
73
+		};
74
+
75
+		user-pb1x {
76
+			label = "user_pb1x";
77
+			linux,code = <BTN_1>;
78
+			interrupt-parent = <&gsc>;
79
+			interrupts = <0>;
80
+		};
81
+
82
+		key-erased {
83
+			label = "key-erased";
84
+			linux,code = <BTN_2>;
85
+			interrupt-parent = <&gsc>;
86
+			interrupts = <1>;
87
+		};
88
+
89
+		eeprom-wp {
90
+			label = "eeprom_wp";
91
+			linux,code = <BTN_3>;
92
+			interrupt-parent = <&gsc>;
93
+			interrupts = <2>;
94
+		};
95
+
96
+		tamper {
97
+			label = "tamper";
98
+			linux,code = <BTN_4>;
99
+			interrupt-parent = <&gsc>;
100
+			interrupts = <5>;
101
+		};
102
+
103
+		switch-hold {
104
+			label = "switch_hold";
105
+			linux,code = <BTN_5>;
106
+			interrupt-parent = <&gsc>;
107
+			interrupts = <7>;
108
+		};
62
109
 	};
63
110
 
64
111
 	leds {
..
..
@@ -81,6 +128,7 @@
81
128
 	};
82
129
 
83
130
 	memory@10000000 {
131
+		device_type = "memory";
84
132
 		reg = <0x10000000 0x20000000>;
85
133
 	};
86
134
 
..
..
@@ -129,11 +177,101 @@
129
177
 	pinctrl-0 = <&pinctrl_i2c1>;
130
178
 	status = "okay";
131
179
 
132
-	gpio: pca9555@23 {
180
+	gsc: gsc@20 {
181
+		compatible = "gw,gsc";
182
+		reg = <0x20>;
183
+		interrupt-parent = <&gpio1>;
184
+		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
185
+		interrupt-controller;
186
+		#interrupt-cells = <1>;
187
+		#size-cells = <0>;
188
+
189
+		adc {
190
+			compatible = "gw,gsc-adc";
191
+			#address-cells = <1>;
192
+			#size-cells = <0>;
193
+
194
+			channel@0 {
195
+				gw,mode = <0>;
196
+				reg = <0x00>;
197
+				label = "temp";
198
+			};
199
+
200
+			channel@2 {
201
+				gw,mode = <1>;
202
+				reg = <0x02>;
203
+				label = "vdd_vin";
204
+			};
205
+
206
+			channel@5 {
207
+				gw,mode = <1>;
208
+				reg = <0x05>;
209
+				label = "vdd_3p3";
210
+			};
211
+
212
+			channel@8 {
213
+				gw,mode = <1>;
214
+				reg = <0x08>;
215
+				label = "vdd_bat";
216
+			};
217
+
218
+			channel@b {
219
+				gw,mode = <1>;
220
+				reg = <0x0b>;
221
+				label = "vdd_5p0";
222
+			};
223
+
224
+			channel@e {
225
+				gw,mode = <1>;
226
+				reg = <0xe>;
227
+				label = "vdd_arm";
228
+			};
229
+
230
+			channel@11 {
231
+				gw,mode = <1>;
232
+				reg = <0x11>;
233
+				label = "vdd_soc";
234
+			};
235
+
236
+			channel@14 {
237
+				gw,mode = <1>;
238
+				reg = <0x14>;
239
+				label = "vdd_3p0";
240
+			};
241
+
242
+			channel@17 {
243
+				gw,mode = <1>;
244
+				reg = <0x17>;
245
+				label = "vdd_1p5";
246
+			};
247
+
248
+			channel@1d {
249
+				gw,mode = <1>;
250
+				reg = <0x1d>;
251
+				label = "vdd_1p8a";
252
+			};
253
+
254
+			channel@20 {
255
+				gw,mode = <1>;
256
+				reg = <0x20>;
257
+				label = "vdd_1p0b";
258
+			};
259
+
260
+			channel@26 {
261
+				gw,mode = <1>;
262
+				reg = <0x26>;
263
+				label = "vdd_an1";
264
+			};
265
+		};
266
+	};
267
+
268
+	gsc_gpio: gpio@23 {
133
269
 		compatible = "nxp,pca9555";
134
270
 		reg = <0x23>;
135
271
 		gpio-controller;
136
272
 		#gpio-cells = <2>;
273
+		interrupt-parent = <&gsc>;
274
+		interrupts = <4>;
137
275
 	};
138
276
 
139
277
 	eeprom1: eeprom@50 {
..
..
@@ -171,6 +309,25 @@
171
309
 	pinctrl-names = "default";
172
310
 	pinctrl-0 = <&pinctrl_i2c2>;
173
311
 	status = "okay";
312
+
313
+	magn@1c {
314
+		compatible = "st,lsm9ds1-magn";
315
+		reg = <0x1c>;
316
+		pinctrl-names = "default";
317
+		pinctrl-0 = <&pinctrl_mag>;
318
+		interrupt-parent = <&gpio1>;
319
+		interrupts = <2 IRQ_TYPE_EDGE_RISING>;
320
+	};
321
+
322
+	imu@6a {
323
+		compatible = "st,lsm9ds1-imu";
324
+		reg = <0x6a>;
325
+		st,drdy-int-pin = <1>;
326
+		pinctrl-names = "default";
327
+		pinctrl-0 = <&pinctrl_imu>;
328
+		interrupt-parent = <&gpio7>;
329
+		interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
330
+	};
174
331
 
175
332
 	ltc3676: pmic@3c {
176
333
 		compatible = "lltc,ltc3676";
..
..
@@ -408,6 +565,7 @@
408
565
 		fsl,pins = <
409
566
 			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
410
567
 			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
568
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0xb0b1
411
569
 		>;
412
570
 	};
413
571
 
..
..
@@ -422,6 +580,12 @@
422
580
 		fsl,pins = <
423
581
 			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
424
582
 			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
583
+		>;
584
+	};
585
+
586
+	pinctrl_imu: imugrp {
587
+		fsl,pins = <
588
+			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b0
425
589
 		>;
426
590
 	};
427
591
 
..
..
@@ -448,6 +612,12 @@
448
612
 		>;
449
613
 	};
450
614
 
615
+	pinctrl_mag: maggrp {
616
+		fsl,pins = <
617
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
618
+		>;
619
+	};
620
+
451
621
 	pinctrl_pcie: pciegrp {
452
622
 		fsl,pins = <
453
623
 			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x1b0b0