add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/boot/dts/imx51.dtsi
..
..
@@ -104,6 +104,11 @@
104
104
 		#phy-cells = <0>;
105
105
 	};
106
106
 
107
+	capture-subsystem {
108
+		compatible = "fsl,imx-capture-subsystem";
109
+		ports = <&ipu_csi0>, <&ipu_csi1>;
110
+	};
111
+
107
112
 	display-subsystem {
108
113
 		compatible = "fsl,imx-display-subsystem";
109
114
 		ports = <&ipu_di0>, <&ipu_di1>;
..
..
@@ -116,9 +121,19 @@
116
121
 		interrupt-parent = <&tzic>;
117
122
 		ranges;
118
123
 
119
-		iram: iram@1ffe0000 {
124
+		iram: sram@1ffe0000 {
120
125
 			compatible = "mmio-sram";
121
126
 			reg = <0x1ffe0000 0x20000>;
127
+		};
128
+
129
+		gpu: gpu@30000000 {
130
+			compatible = "amd,imageon-200.1", "amd,imageon";
131
+			reg = <0x30000000 0x20000>;
132
+			reg-names = "kgsl_3d0_reg_memory";
133
+			interrupts = <12>;
134
+			interrupt-names = "kgsl_3d0_irq";
135
+			clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
136
+			clock-names = "core_clk", "mem_iface_clk";
122
137
 		};
123
138
 
124
139
 		ipu: ipu@40000000 {
..
..
@@ -132,6 +147,14 @@
132
147
 				 <&clks IMX5_CLK_IPU_DI1_GATE>;
133
148
 			clock-names = "bus", "di0", "di1";
134
149
 			resets = <&src 2>;
150
+
151
+			ipu_csi0: port@0 {
152
+				reg = <0>;
153
+			};
154
+
155
+			ipu_csi1: port@1 {
156
+				reg = <1>;
157
+			};
135
158
 
136
159
 			ipu_di0: port@2 {
137
160
 				reg = <2>;
..
..
@@ -148,7 +171,7 @@
148
171
 			};
149
172
 		};
150
173
 
151
-		aips@70000000 { /* AIPS1 */
174
+		bus@70000000 { /* AIPS1 */
152
175
 			compatible = "fsl,aips-bus", "simple-bus";
153
176
 			#address-cells = <1>;
154
177
 			#size-cells = <1>;
..
..
@@ -162,7 +185,7 @@
162
185
 				reg = <0x70000000 0x40000>;
163
186
 				ranges;
164
187
 
165
-				esdhc1: esdhc@70004000 {
188
+				esdhc1: mmc@70004000 {
166
189
 					compatible = "fsl,imx51-esdhc";
167
190
 					reg = <0x70004000 0x4000>;
168
191
 					interrupts = <1>;
..
..
@@ -173,7 +196,7 @@
173
196
 					status = "disabled";
174
197
 				};
175
198
 
176
-				esdhc2: esdhc@70008000 {
199
+				esdhc2: mmc@70008000 {
177
200
 					compatible = "fsl,imx51-esdhc";
178
201
 					reg = <0x70008000 0x4000>;
179
202
 					interrupts = <2>;
..
..
@@ -195,7 +218,7 @@
195
218
 					status = "disabled";
196
219
 				};
197
220
 
198
-				ecspi1: ecspi@70010000 {
221
+				ecspi1: spi@70010000 {
199
222
 					#address-cells = <1>;
200
223
 					#size-cells = <0>;
201
224
 					compatible = "fsl,imx51-ecspi";
..
..
@@ -222,7 +245,7 @@
222
245
 					status = "disabled";
223
246
 				};
224
247
 
225
-				esdhc3: esdhc@70020000 {
248
+				esdhc3: mmc@70020000 {
226
249
 					compatible = "fsl,imx51-esdhc";
227
250
 					reg = <0x70020000 0x4000>;
228
251
 					interrupts = <3>;
..
..
@@ -234,7 +257,7 @@
234
257
 					status = "disabled";
235
258
 				};
236
259
 
237
-				esdhc4: esdhc@70024000 {
260
+				esdhc4: mmc@70024000 {
238
261
 					compatible = "fsl,imx51-esdhc";
239
262
 					reg = <0x70024000 0x4000>;
240
263
 					interrupts = <4>;
..
..
@@ -377,7 +400,7 @@
377
400
 			};
378
401
 
379
402
 			pwm1: pwm@73fb4000 {
380
-				#pwm-cells = <2>;
403
+				#pwm-cells = <3>;
381
404
 				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
382
405
 				reg = <0x73fb4000 0x4000>;
383
406
 				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
..
..
@@ -387,7 +410,7 @@
387
410
 			};
388
411
 
389
412
 			pwm2: pwm@73fb8000 {
390
-				#pwm-cells = <2>;
413
+				#pwm-cells = <3>;
391
414
 				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
392
415
 				reg = <0x73fb8000 0x4000>;
393
416
 				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
..
..
@@ -416,9 +439,10 @@
416
439
 				status = "disabled";
417
440
 			};
418
441
 
419
-			src: src@73fd0000 {
442
+			src: reset-controller@73fd0000 {
420
443
 				compatible = "fsl,imx51-src";
421
444
 				reg = <0x73fd0000 0x4000>;
445
+				interrupts = <75>;
422
446
 				#reset-cells = <1>;
423
447
 			};
424
448
 
..
..
@@ -430,7 +454,7 @@
430
454
 			};
431
455
 		};
432
456
 
433
-		aips@80000000 {	/* AIPS2 */
457
+		bus@80000000 {	/* AIPS2 */
434
458
 			compatible = "fsl,aips-bus", "simple-bus";
435
459
 			#address-cells = <1>;
436
460
 			#size-cells = <1>;
..
..
@@ -442,7 +466,7 @@
442
466
 				reg = <0x83f00000 0x60>;
443
467
 			};
444
468
 
445
-			iim: iim@83f98000 {
469
+			iim: efuse@83f98000 {
446
470
 				compatible = "fsl,imx51-iim", "fsl,imx27-iim";
447
471
 				reg = <0x83f98000 0x4000>;
448
472
 				interrupts = <69>;
..
..
@@ -462,7 +486,7 @@
462
486
 				status = "disabled";
463
487
 			};
464
488
 
465
-			ecspi2: ecspi@83fac000 {
489
+			ecspi2: spi@83fac000 {
466
490
 				#address-cells = <1>;
467
491
 				#size-cells = <0>;
468
492
 				compatible = "fsl,imx51-ecspi";
..
..
@@ -474,7 +498,7 @@
474
498
 				status = "disabled";
475
499
 			};
476
500
 
477
-			sdma: sdma@83fb0000 {
501
+			sdma: dma-controller@83fb0000 {
478
502
 				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
479
503
 				reg = <0x83fb0000 0x4000>;
480
504
 				interrupts = <6>;
..
..
@@ -485,7 +509,7 @@
485
509
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
486
510
 			};
487
511
 
488
-			cspi: cspi@83fc0000 {
512
+			cspi: spi@83fc0000 {
489
513
 				#address-cells = <1>;
490
514
 				#size-cells = <0>;
491
515
 				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
..
..
@@ -606,7 +630,7 @@
606
630
 				status = "disabled";
607
631
 			};
608
632
 
609
-			vpu@83ff4000 {
633
+			vpu: vpu@83ff4000 {
610
634
 				compatible = "fsl,imx51-vpu", "cnm,codahx4";
611
635
 				reg = <0x83ff4000 0x1000>;
612
636
 				interrupts = <9>;