.. | .. |
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21 | 21 | gpio0 = &gpio1; |
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22 | 22 | gpio1 = &gpio2; |
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23 | 23 | gpio2 = &gpio3; |
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| 24 | + i2c0 = &i2c1; |
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| 25 | + i2c1 = &i2c2; |
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| 26 | + i2c2 = &i2c3; |
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| 27 | + mmc0 = &esdhc1; |
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| 28 | + mmc1 = &esdhc2; |
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| 29 | + mmc2 = &esdhc3; |
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24 | 30 | serial0 = &uart1; |
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25 | 31 | serial1 = &uart2; |
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26 | 32 | serial2 = &uart3; |
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.. | .. |
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53 | 59 | interrupt-parent = <&avic>; |
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54 | 60 | ranges; |
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55 | 61 | |
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56 | | - L2: l2-cache@30000000 { |
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| 62 | + L2: cache-controller@30000000 { |
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57 | 63 | compatible = "arm,l210-cache"; |
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58 | 64 | reg = <0x30000000 0x1000>; |
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59 | 65 | cache-unified; |
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60 | 66 | cache-level = <2>; |
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61 | 67 | }; |
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62 | 68 | |
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63 | | - aips1: aips@43f00000 { |
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| 69 | + aips1: bus@43f00000 { |
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64 | 70 | compatible = "fsl,aips", "simple-bus"; |
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65 | 71 | #address-cells = <1>; |
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66 | 72 | #size-cells = <1>; |
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.. | .. |
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131 | 137 | status = "disabled"; |
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132 | 138 | }; |
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133 | 139 | |
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134 | | - spi1: cspi@43fa4000 { |
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| 140 | + spi1: spi@43fa4000 { |
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135 | 141 | #address-cells = <1>; |
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136 | 142 | #size-cells = <0>; |
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137 | 143 | compatible = "fsl,imx35-cspi"; |
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.. | .. |
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172 | 178 | status = "disabled"; |
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173 | 179 | }; |
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174 | 180 | |
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175 | | - spi2: cspi@50010000 { |
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| 181 | + spi2: spi@50010000 { |
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176 | 182 | #address-cells = <1>; |
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177 | 183 | #size-cells = <0>; |
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178 | 184 | compatible = "fsl,imx35-cspi"; |
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.. | .. |
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193 | 199 | }; |
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194 | 200 | }; |
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195 | 201 | |
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196 | | - aips2: aips@53f00000 { |
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| 202 | + aips2: bus@53f00000 { |
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197 | 203 | compatible = "fsl,aips", "simple-bus"; |
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198 | 204 | #address-cells = <1>; |
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199 | 205 | #size-cells = <1>; |
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.. | .. |
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225 | 231 | #interrupt-cells = <2>; |
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226 | 232 | }; |
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227 | 233 | |
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228 | | - esdhc1: esdhc@53fb4000 { |
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| 234 | + esdhc1: mmc@53fb4000 { |
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229 | 235 | compatible = "fsl,imx35-esdhc"; |
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230 | 236 | reg = <0x53fb4000 0x4000>; |
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231 | 237 | interrupts = <7>; |
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.. | .. |
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234 | 240 | status = "disabled"; |
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235 | 241 | }; |
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236 | 242 | |
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237 | | - esdhc2: esdhc@53fb8000 { |
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| 243 | + esdhc2: mmc@53fb8000 { |
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238 | 244 | compatible = "fsl,imx35-esdhc"; |
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239 | 245 | reg = <0x53fb8000 0x4000>; |
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240 | 246 | interrupts = <8>; |
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.. | .. |
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243 | 249 | status = "disabled"; |
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244 | 250 | }; |
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245 | 251 | |
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246 | | - esdhc3: esdhc@53fbc000 { |
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| 252 | + esdhc3: mmc@53fbc000 { |
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247 | 253 | compatible = "fsl,imx35-esdhc"; |
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248 | 254 | reg = <0x53fbc000 0x4000>; |
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249 | 255 | interrupts = <9>; |
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.. | .. |
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278 | 284 | #interrupt-cells = <2>; |
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279 | 285 | }; |
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280 | 286 | |
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281 | | - sdma: sdma@53fd4000 { |
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| 287 | + sdma: dma-controller@53fd4000 { |
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282 | 288 | compatible = "fsl,imx35-sdma"; |
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283 | 289 | reg = <0x53fd4000 0x4000>; |
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284 | 290 | clocks = <&clks 9>, <&clks 65>; |
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.. | .. |
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314 | 320 | status = "disabled"; |
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315 | 321 | }; |
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316 | 322 | |
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317 | | - iim@53ff0000 { |
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| 323 | + efuse@53ff0000 { |
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318 | 324 | compatible = "fsl,imx35-iim"; |
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319 | 325 | reg = <0x53ff0000 0x4000>; |
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320 | 326 | interrupts = <19>; |
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