.. | .. |
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40 | 40 | spi2 = &cspi3; |
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41 | 41 | }; |
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42 | 42 | |
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43 | | - aitc: aitc-interrupt-controller@e0000000 { |
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| 43 | + aitc: aitc-interrupt-controller@10040000 { |
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44 | 44 | compatible = "fsl,imx27-aitc", "fsl,avic"; |
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45 | 45 | interrupt-controller; |
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46 | 46 | #interrupt-cells = <1>; |
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.. | .. |
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134 | 134 | }; |
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135 | 135 | |
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136 | 136 | pwm: pwm@10006000 { |
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137 | | - #pwm-cells = <2>; |
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| 137 | + #pwm-cells = <3>; |
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138 | 138 | compatible = "fsl,imx27-pwm"; |
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139 | 139 | reg = <0x10006000 0x1000>; |
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140 | 140 | interrupts = <23>; |
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.. | .. |
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207 | 207 | status = "disabled"; |
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208 | 208 | }; |
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209 | 209 | |
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210 | | - cspi1: cspi@1000e000 { |
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| 210 | + cspi1: spi@1000e000 { |
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211 | 211 | #address-cells = <1>; |
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212 | 212 | #size-cells = <0>; |
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213 | 213 | compatible = "fsl,imx27-cspi"; |
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.. | .. |
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219 | 219 | status = "disabled"; |
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220 | 220 | }; |
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221 | 221 | |
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222 | | - cspi2: cspi@1000f000 { |
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| 222 | + cspi2: spi@1000f000 { |
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223 | 223 | #address-cells = <1>; |
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224 | 224 | #size-cells = <0>; |
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225 | 225 | compatible = "fsl,imx27-cspi"; |
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.. | .. |
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265 | 265 | status = "disabled"; |
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266 | 266 | }; |
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267 | 267 | |
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268 | | - sdhci1: sdhci@10013000 { |
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| 268 | + sdhci1: mmc@10013000 { |
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269 | 269 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
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270 | 270 | reg = <0x10013000 0x1000>; |
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271 | 271 | interrupts = <11>; |
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.. | .. |
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277 | 277 | status = "disabled"; |
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278 | 278 | }; |
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279 | 279 | |
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280 | | - sdhci2: sdhci@10014000 { |
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| 280 | + sdhci2: mmc@10014000 { |
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281 | 281 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
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282 | 282 | reg = <0x10014000 0x1000>; |
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283 | 283 | interrupts = <10>; |
---|
.. | .. |
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371 | 371 | status = "disabled"; |
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372 | 372 | }; |
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373 | 373 | |
---|
374 | | - cspi3: cspi@10017000 { |
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| 374 | + cspi3: spi@10017000 { |
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375 | 375 | #address-cells = <1>; |
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376 | 376 | #size-cells = <0>; |
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377 | 377 | compatible = "fsl,imx27-cspi"; |
---|
.. | .. |
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431 | 431 | status = "disabled"; |
---|
432 | 432 | }; |
---|
433 | 433 | |
---|
434 | | - sdhci3: sdhci@1001e000 { |
---|
| 434 | + sdhci3: mmc@1001e000 { |
---|
435 | 435 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
---|
436 | 436 | reg = <0x1001e000 0x1000>; |
---|
437 | 437 | interrupts = <9>; |
---|
.. | .. |
---|
525 | 525 | reg = <0x10024600 0x200>; |
---|
526 | 526 | }; |
---|
527 | 527 | |
---|
528 | | - sahara2: sahara@10025000 { |
---|
| 528 | + sahara2: crypto@10025000 { |
---|
529 | 529 | compatible = "fsl,imx27-sahara"; |
---|
530 | 530 | reg = <0x10025000 0x1000>; |
---|
531 | 531 | interrupts = <59>; |
---|
.. | .. |
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540 | 540 | #clock-cells = <1>; |
---|
541 | 541 | }; |
---|
542 | 542 | |
---|
543 | | - iim: iim@10028000 { |
---|
| 543 | + iim: efuse@10028000 { |
---|
544 | 544 | compatible = "fsl,imx27-iim"; |
---|
545 | 545 | reg = <0x10028000 0x1000>; |
---|
546 | 546 | interrupts = <62>; |
---|
.. | .. |
---|
558 | 558 | }; |
---|
559 | 559 | }; |
---|
560 | 560 | |
---|
561 | | - nfc: nand@d8000000 { |
---|
| 561 | + nfc: nand-controller@d8000000 { |
---|
562 | 562 | #address-cells = <1>; |
---|
563 | 563 | #size-cells = <1>; |
---|
564 | 564 | compatible = "fsl,imx27-nand"; |
---|
.. | .. |
---|
585 | 585 | status = "disabled"; |
---|
586 | 586 | }; |
---|
587 | 587 | |
---|
588 | | - iram: iram@ffff4c00 { |
---|
| 588 | + iram: sram@ffff4c00 { |
---|
589 | 589 | compatible = "mmio-sram"; |
---|
590 | 590 | reg = <0xffff4c00 0xb400>; |
---|
591 | 591 | }; |
---|