add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/boot/dts/dra76-evm.dts
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..
@@ -1,9 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
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  */
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 /dts-v1/;
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6
 
..
..
@@ -16,9 +13,50 @@
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 	model = "TI DRA762 EVM";
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 	compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
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15
 
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+	aliases {
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+		display0 = &hdmi0;
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+
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+		sound0 = &sound0;
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+		sound1 = &hdmi;
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+	};
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+
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 	memory@0 {
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 		device_type = "memory";
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 		reg = <0x0 0x80000000 0x0 0x80000000>;
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+	};
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+
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+	reserved-memory {
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+		#address-cells = <2>;
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+		#size-cells = <2>;
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+		ranges;
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+
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+		ipu2_cma_pool: ipu2_cma@95800000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x95800000 0x0 0x3800000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		dsp1_cma_pool: dsp1_cma@99000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x99000000 0x0 0x4000000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		ipu1_cma_pool: ipu1_cma@9d000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x9d000000 0x0 0x2000000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		dsp2_cma_pool: dsp2_cma@9f000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x9f000000 0x0 0x800000>;
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+			reusable;
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+			status = "okay";
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+		};
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 	};
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61
 
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 	vsys_12v0: fixedregulator-vsys12v0 {
..
..
@@ -118,6 +156,54 @@
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 		vin-supply = <&vio_3v3>;
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 		regulator-min-microvolt = <1800000>;
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 		regulator-max-microvolt = <1800000>;
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+	};
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+
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+	clk_ov5640_fixed: clock {
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+		compatible = "fixed-clock";
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+		#clock-cells = <0>;
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+		clock-frequency = <24000000>;
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+	};
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+
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+	hdmi0: connector {
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+		compatible = "hdmi-connector";
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+		label = "hdmi";
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+
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+		type = "a";
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+
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+		port {
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+			hdmi_connector_in: endpoint {
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+				remote-endpoint = <&tpd12s015_out>;
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+			};
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+		};
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+	};
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+
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+	tpd12s015: encoder {
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+		compatible = "ti,tpd12s015";
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+
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+		gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>,   /* gpio7_30, CT CP HPD */
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+			<&gpio7 31 GPIO_ACTIVE_HIGH>,   /* gpio7_31, LS OE */
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+			<&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
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+
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+		ports {
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+
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+			port@0 {
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+				reg = <0>;
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+
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+				tpd12s015_in: endpoint {
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+					remote-endpoint = <&hdmi_out>;
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+				};
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+			};
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+
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+			port@1 {
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+				reg = <1>;
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+
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+				tpd12s015_out: endpoint {
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+					remote-endpoint = <&hdmi_connector_in>;
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+				};
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+			};
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+		};
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 	};
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 };
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..
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@@ -320,6 +406,27 @@
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 	};
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 };
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+&i2c5 {
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+	status = "okay";
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+	clock-frequency = <400000>;
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+
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+	ov5640@3c {
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+		compatible = "ovti,ov5640";
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+		reg = <0x3c>;
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+
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+		clocks = <&clk_ov5640_fixed>;
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+		clock-names = "xclk";
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+
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+		port {
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+			csi2_cam0: endpoint {
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+				remote-endpoint = <&csi2_phy0>;
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+				clock-lanes = <0>;
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+				data-lanes = <1 2>;
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+			};
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+		};
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+	};
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+};
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+
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 &cpu0 {
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 	vdd-supply = <&buck10_reg>;
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 };
..
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@@ -368,25 +475,23 @@
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 	status = "disabled";
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 };
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477
 
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-&mac {
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+&mac_sw {
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 	status = "okay";
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-
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-	dual_emac;
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 };
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-&cpsw_emac0 {
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-	phy_id = <&davinci_mdio>, <2>;
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+&cpsw_port1 {
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+	phy-handle = <&dp83867_0>;
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 	phy-mode = "rgmii-id";
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-	dual_emac_res_vlan = <1>;
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+	ti,dual-emac-pvid = <1>;
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 };
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-&cpsw_emac1 {
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-	phy_id = <&davinci_mdio>, <3>;
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+&cpsw_port2 {
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+	phy-handle = <&dp83867_1>;
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 	phy-mode = "rgmii-id";
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-	dual_emac_res_vlan = <2>;
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+	ti,dual-emac-pvid = <2>;
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 };
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-&davinci_mdio {
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+&davinci_mdio_sw {
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 	dp83867_0: ethernet-phy@2 {
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 		reg = <2>;
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 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
..
..
@@ -412,6 +517,23 @@
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 &usb2_phy2 {
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 	phy-supply = <&ldo3_reg>;
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+};
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+
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+&dss {
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+	status = "okay";
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+	vdda_video-supply = <&ldo5_reg>;
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+};
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+
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+&hdmi {
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+	status = "okay";
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+
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+	vdda-supply = <&ldo1_reg>;
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+
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+	port {
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+		hdmi_out: endpoint {
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+			remote-endpoint = <&tpd12s015_in>;
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+		};
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+	};
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 };
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 &qspi {
..
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@@ -450,3 +572,31 @@
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 		max-bitrate = <5000000>;
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 	};
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 };
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+
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+&csi2_0 {
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+	csi2_phy0: endpoint {
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+		remote-endpoint = <&csi2_cam0>;
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+		clock-lanes = <0>;
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+		data-lanes = <1 2>;
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+	};
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+};
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+
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+&ipu2 {
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+	status = "okay";
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+	memory-region = <&ipu2_cma_pool>;
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+};
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+
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+&ipu1 {
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+	status = "okay";
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+	memory-region = <&ipu1_cma_pool>;
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+};
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+
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+&dsp1 {
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+	status = "okay";
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+	memory-region = <&dsp1_cma_pool>;
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+};
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+
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+&dsp2 {
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+	status = "okay";
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+	memory-region = <&dsp2_cma_pool>;
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+};