add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/boot/dts/dra7-evm.dts
..
..
@@ -1,9 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
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  */
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 /dts-v1/;
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..
..
@@ -38,6 +35,40 @@
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 		regulator-max-microvolt = <1800000>;
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 	};
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+	reserved-memory {
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+		#address-cells = <2>;
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+		#size-cells = <2>;
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+		ranges;
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+
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+		ipu2_memory_region: ipu2-memory@95800000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x95800000 0x0 0x3800000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		dsp1_memory_region: dsp1-memory@99000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x99000000 0x0 0x4000000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		ipu1_memory_region: ipu1-memory@9d000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x9d000000 0x0 0x2000000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		dsp2_memory_region: dsp2-memory@9f000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x9f000000 0x0 0x800000>;
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+			reusable;
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+			status = "okay";
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+		};
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+	};
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+
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 	evm_3v3_sd: fixedregulator-sd {
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 		compatible = "regulator-fixed";
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 		regulator-name = "evm_3v3_sd";
..
..
@@ -64,10 +95,10 @@
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 		regulator-max-microvolt = <1800000>;
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 	};
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-	evm_3v3: fixedregulator-evm3v3 {
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+	vsys_3v3: fixedregulator-vsys3v3 {
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 		/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
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 		compatible = "regulator-fixed";
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-		regulator-name = "evm_3v3";
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+		regulator-name = "vsys_3v3";
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 		regulator-min-microvolt = <3300000>;
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 		regulator-max-microvolt = <3300000>;
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 		vin-supply = <&evm_12v0>;
..
..
@@ -501,32 +532,61 @@
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 	phy-supply = <&ldousb_reg>;
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 };
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534
 
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-&gpio7 {
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+&gpio7_target {
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 	ti,no-reset-on-init;
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 	ti,no-idle-on-init;
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 };
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-&mac {
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+&mac_sw {
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 	status = "okay";
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-	dual_emac;
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 };
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-&cpsw_emac0 {
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-	phy_id = <&davinci_mdio>, <2>;
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+&cpsw_port1 {
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+	phy-handle = <&ethphy0>;
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 	phy-mode = "rgmii";
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-	dual_emac_res_vlan = <1>;
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+	ti,dual-emac-pvid = <1>;
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 };
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-&cpsw_emac1 {
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-	phy_id = <&davinci_mdio>, <3>;
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+&cpsw_port2 {
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+	phy-handle = <&ethphy1>;
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 	phy-mode = "rgmii";
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-	dual_emac_res_vlan = <2>;
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+	ti,dual-emac-pvid = <2>;
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+};
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+
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+&davinci_mdio_sw {
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+	ethphy0: ethernet-phy@2 {
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+		reg = <2>;
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+	};
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+
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+	ethphy1: ethernet-phy@3 {
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+		reg = <3>;
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+	};
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 };
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 &dcan1 {
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-	status = "ok";
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+	status = "okay";
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 	pinctrl-names = "default", "sleep", "active";
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 	pinctrl-0 = <&dcan1_pins_sleep>;
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 	pinctrl-1 = <&dcan1_pins_sleep>;
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 	pinctrl-2 = <&dcan1_pins_default>;
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 };
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+
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+&ipu2 {
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+	status = "okay";
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+	memory-region = <&ipu2_memory_region>;
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+};
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+
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+&ipu1 {
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+	status = "okay";
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+	memory-region = <&ipu1_memory_region>;
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+};
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+
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+&dsp1 {
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+	status = "okay";
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+	memory-region = <&dsp1_memory_region>;
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+};
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+
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+&dsp2 {
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+	status = "okay";
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+	memory-region = <&dsp2_memory_region>;
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+};