kernel/arch/arm/boot/dts/bcm-hr2.dtsi
.. .. @@ -104,7 +104,7 @@ 104 104 <0x20100 0x100>; 105 105 }; 106 106 107 - L2: l2-cache@22000 {107 + L2: cache-controller@22000 {108 108 compatible = "arm,pl310-cache"; 109 109 reg = <0x22000 0x1000>; 110 110 cache-unified; .. .. @@ -268,7 +268,7 @@ 268 268 clock-frequency = <100000>; 269 269 }; 270 270 271 - watchdog@39000 {271 + watchdog: watchdog@39000 {272 272 compatible = "arm,sp805", "arm,primecell"; 273 273 reg = <0x39000 0x1000>; 274 274 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;