.. | .. |
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25 | 25 | */ |
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26 | 26 | |
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27 | 27 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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28 | | -#include "skeleton64.dtsi" |
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29 | 28 | |
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30 | 29 | / { |
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| 30 | + #address-cells = <2>; |
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| 31 | + #size-cells = <2>; |
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31 | 32 | /* SOC compatibility */ |
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32 | 33 | compatible = "al,alpine"; |
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| 34 | + |
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| 35 | + memory { |
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| 36 | + device_type = "memory"; |
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| 37 | + reg = <0 0 0 0>; |
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| 38 | + }; |
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33 | 39 | |
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34 | 40 | /* CPU Configuration */ |
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35 | 41 | cpus { |
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.. | .. |
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85 | 91 | }; |
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86 | 92 | |
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87 | 93 | /* Interrupt Controller */ |
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88 | | - gic: gic@fb001000 { |
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| 94 | + gic: interrupt-controller@fb001000 { |
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89 | 95 | compatible = "arm,cortex-a15-gic"; |
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90 | 96 | #interrupt-cells = <3>; |
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91 | 97 | #size-cells = <0>; |
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