forked from ~ljy/RK356X_SDK_RELEASE

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2023-11-22 f743a7adbd6e230d66a6206fa115b59fec2d88eb 
 kernel/drivers/pinctrl/pinctrl-rockchip.c
....@@ -725,15 +725,17 @@
725725 };
726726 
727727 static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
728
-	RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
729
-	RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
728
+	RK_MUXROUTE_GRF(3, RK_PD1, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_RX_M0 */
729
+	RK_MUXROUTE_GRF(3, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_TX_M0 */
730
+	RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_RX_M1 */
731
+	RK_MUXROUTE_GRF(3, RK_PA4, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_TX_M1 */
730732 
731
-	RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
732
-	RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
733
-	RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
733
+	RK_MUXROUTE_GRF(1, RK_PA1, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_SCLK_M0 */
734
+	RK_MUXROUTE_GRF(1, RK_PD6, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_SCLK_M1 */
735
+	RK_MUXROUTE_GRF(2, RK_PD1, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_SCLK_M2 */
734736 
735
-	RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
736
-	RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
737
+	RK_MUXROUTE_GRF(1, RK_PC6, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_SCLK_M0 */
738
+	RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_SCLK_M1 */
737739 
738740 	RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
739741 	RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
....@@ -2010,6 +2012,146 @@
20102012 		*bit = (pin_num % 8) * 2;
20112013 }
20122014 
2015
+#define RK3528_DRV_BITS_PER_PIN		8
2016
+#define RK3528_DRV_PINS_PER_REG		2
2017
+#define RK3528_DRV_GPIO0_OFFSET		0x100
2018
+#define RK3528_DRV_GPIO1_OFFSET		0x20120
2019
+#define RK3528_DRV_GPIO2_OFFSET		0x30160
2020
+#define RK3528_DRV_GPIO3_OFFSET		0x20190
2021
+#define RK3528_DRV_GPIO4_OFFSET		0x101C0
2022
+
2023
+static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2024
+					int pin_num, struct regmap **regmap,
2025
+					int *reg, u8 *bit)
2026
+{
2027
+	struct rockchip_pinctrl *info = bank->drvdata;
2028
+
2029
+	*regmap = info->regmap_base;
2030
+	switch (bank->bank_num) {
2031
+	case 0:
2032
+		*reg = RK3528_DRV_GPIO0_OFFSET;
2033
+		break;
2034
+
2035
+	case 1:
2036
+		*reg = RK3528_DRV_GPIO1_OFFSET;
2037
+		break;
2038
+
2039
+	case 2:
2040
+		*reg = RK3528_DRV_GPIO2_OFFSET;
2041
+		break;
2042
+
2043
+	case 3:
2044
+		*reg = RK3528_DRV_GPIO3_OFFSET;
2045
+		break;
2046
+
2047
+	case 4:
2048
+		*reg = RK3528_DRV_GPIO4_OFFSET;
2049
+		break;
2050
+
2051
+	default:
2052
+		dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2053
+		break;
2054
+	}
2055
+
2056
+	*reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
2057
+	*bit = pin_num % RK3528_DRV_PINS_PER_REG;
2058
+	*bit *= RK3528_DRV_BITS_PER_PIN;
2059
+}
2060
+
2061
+#define RK3528_PULL_BITS_PER_PIN		2
2062
+#define RK3528_PULL_PINS_PER_REG		8
2063
+#define RK3528_PULL_GPIO0_OFFSET		0x200
2064
+#define RK3528_PULL_GPIO1_OFFSET		0x20210
2065
+#define RK3528_PULL_GPIO2_OFFSET		0x30220
2066
+#define RK3528_PULL_GPIO3_OFFSET		0x20230
2067
+#define RK3528_PULL_GPIO4_OFFSET		0x10240
2068
+
2069
+static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2070
+					 int pin_num, struct regmap **regmap,
2071
+					 int *reg, u8 *bit)
2072
+{
2073
+	struct rockchip_pinctrl *info = bank->drvdata;
2074
+
2075
+	*regmap = info->regmap_base;
2076
+	switch (bank->bank_num) {
2077
+	case 0:
2078
+		*reg = RK3528_PULL_GPIO0_OFFSET;
2079
+		break;
2080
+
2081
+	case 1:
2082
+		*reg = RK3528_PULL_GPIO1_OFFSET;
2083
+		break;
2084
+
2085
+	case 2:
2086
+		*reg = RK3528_PULL_GPIO2_OFFSET;
2087
+		break;
2088
+
2089
+	case 3:
2090
+		*reg = RK3528_PULL_GPIO3_OFFSET;
2091
+		break;
2092
+
2093
+	case 4:
2094
+		*reg = RK3528_PULL_GPIO4_OFFSET;
2095
+		break;
2096
+
2097
+	default:
2098
+		dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2099
+		break;
2100
+	}
2101
+
2102
+	*reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
2103
+	*bit = pin_num % RK3528_PULL_PINS_PER_REG;
2104
+	*bit *= RK3528_PULL_BITS_PER_PIN;
2105
+}
2106
+
2107
+#define RK3528_SMT_BITS_PER_PIN		1
2108
+#define RK3528_SMT_PINS_PER_REG		8
2109
+#define RK3528_SMT_GPIO0_OFFSET		0x400
2110
+#define RK3528_SMT_GPIO1_OFFSET		0x20410
2111
+#define RK3528_SMT_GPIO2_OFFSET		0x30420
2112
+#define RK3528_SMT_GPIO3_OFFSET		0x20430
2113
+#define RK3528_SMT_GPIO4_OFFSET		0x10440
2114
+
2115
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2116
+					   int pin_num,
2117
+					   struct regmap **regmap,
2118
+					   int *reg, u8 *bit)
2119
+{
2120
+	struct rockchip_pinctrl *info = bank->drvdata;
2121
+
2122
+	*regmap = info->regmap_base;
2123
+	switch (bank->bank_num) {
2124
+	case 0:
2125
+		*reg = RK3528_SMT_GPIO0_OFFSET;
2126
+		break;
2127
+
2128
+	case 1:
2129
+		*reg = RK3528_SMT_GPIO1_OFFSET;
2130
+		break;
2131
+
2132
+	case 2:
2133
+		*reg = RK3528_SMT_GPIO2_OFFSET;
2134
+		break;
2135
+
2136
+	case 3:
2137
+		*reg = RK3528_SMT_GPIO3_OFFSET;
2138
+		break;
2139
+
2140
+	case 4:
2141
+		*reg = RK3528_SMT_GPIO4_OFFSET;
2142
+		break;
2143
+
2144
+	default:
2145
+		dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2146
+		break;
2147
+	}
2148
+
2149
+	*reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
2150
+	*bit = pin_num % RK3528_SMT_PINS_PER_REG;
2151
+	*bit *= RK3528_SMT_BITS_PER_PIN;
2152
+	return 0;
2153
+}
2154
+
20132155 #define RK3568_SR_PMU_OFFSET		0x60
20142156 #define RK3568_SR_GRF_OFFSET		0x0180
20152157 #define RK3568_SR_BANK_STRIDE		0x10
....@@ -2226,7 +2368,7 @@
22262368 		rmask_bits = RV1126_DRV_BITS_PER_PIN;
22272369 		ret = strength;
22282370 		goto config;
2229
-	} else if (ctrl->type == RK3568) {
2371
+	} else if (ctrl->type == RK3568 || ctrl->type == RK3528) {
22302372 		rmask_bits = RK3568_DRV_BITS_PER_PIN;
22312373 		ret = (1 << (strength + 1)) - 1;
22322374 		goto config;
....@@ -2396,6 +2538,7 @@
23962538 	case RK3308:
23972539 	case RK3368:
23982540 	case RK3399:
2541
+	case RK3528:
23992542 	case RK3568:
24002543 		pull_type = bank->pull_type[pin_num / 8];
24012544 		data >>= bit;
....@@ -2444,6 +2587,7 @@
24442587 	case RK3308:
24452588 	case RK3368:
24462589 	case RK3399:
2590
+	case RK3528:
24472591 	case RK3568:
24482592 		pull_type = bank->pull_type[pin_num / 8];
24492593 		ret = -EINVAL;
....@@ -2796,6 +2940,7 @@
27962940 	case RK3308:
27972941 	case RK3368:
27982942 	case RK3399:
2943
+	case RK3528:
27992944 	case RK3568:
28002945 		return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
28012946 	}
....@@ -4025,6 +4170,49 @@
40254170 		.drv_calc_reg		= rk3399_calc_drv_reg_and_bit,
40264171 };
40274172 
4173
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
4174
+	PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
4175
+				    IOMUX_WIDTH_4BIT,
4176
+				    IOMUX_WIDTH_4BIT,
4177
+				    IOMUX_WIDTH_4BIT,
4178
+				    IOMUX_WIDTH_4BIT,
4179
+				    0, 0, 0, 0),
4180
+	PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4181
+				    IOMUX_WIDTH_4BIT,
4182
+				    IOMUX_WIDTH_4BIT,
4183
+				    IOMUX_WIDTH_4BIT,
4184
+				    IOMUX_WIDTH_4BIT,
4185
+				    0x20020, 0x20028, 0x20030, 0x20038),
4186
+	PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4187
+				    IOMUX_WIDTH_4BIT,
4188
+				    IOMUX_WIDTH_4BIT,
4189
+				    IOMUX_WIDTH_4BIT,
4190
+				    IOMUX_WIDTH_4BIT,
4191
+				    0x30040, 0, 0, 0),
4192
+	PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
4193
+				    IOMUX_WIDTH_4BIT,
4194
+				    IOMUX_WIDTH_4BIT,
4195
+				    IOMUX_WIDTH_4BIT,
4196
+				    IOMUX_WIDTH_4BIT,
4197
+				    0x20060, 0x20068, 0x20070, 0),
4198
+	PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
4199
+				    IOMUX_WIDTH_4BIT,
4200
+				    IOMUX_WIDTH_4BIT,
4201
+				    IOMUX_WIDTH_4BIT,
4202
+				    IOMUX_WIDTH_4BIT,
4203
+				    0x10080, 0x10088, 0x10090, 0x10098),
4204
+};
4205
+
4206
+static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = {
4207
+	.pin_banks		= rk3528_pin_banks,
4208
+	.nr_banks		= ARRAY_SIZE(rk3528_pin_banks),
4209
+	.label			= "RK3528-GPIO",
4210
+	.type			= RK3528,
4211
+	.pull_calc_reg		= rk3528_calc_pull_reg_and_bit,
4212
+	.drv_calc_reg		= rk3528_calc_drv_reg_and_bit,
4213
+	.schmitt_calc_reg	= rk3528_calc_schmitt_reg_and_bit,
4214
+};
4215
+
40284216 static struct rockchip_pin_bank rk3568_pin_banks[] = {
40294217 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
40304218 					     IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
....@@ -4128,6 +4316,10 @@
41284316 	{ .compatible = "rockchip,rk3399-pinctrl",
41294317 		.data = &rk3399_pin_ctrl },
41304318 #endif
4319
+#ifdef CONFIG_CPU_RK3528
4320
+	{ .compatible = "rockchip,rk3528-pinctrl",
4321
+		.data = &rk3528_pin_ctrl },
4322
+#endif
41314323 #ifdef CONFIG_CPU_RK3568
41324324 	{ .compatible = "rockchip,rk3568-pinctrl",
41334325 		.data = &rk3568_pin_ctrl },