add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/sound/soc/stm/stm32_sai.h
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@@ -1,19 +1,9 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
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  *
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  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
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- *
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- * License terms: GPL V2.0.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published by
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- * the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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- * details.
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  */
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 #include <linux/bitfield.h>
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@@ -36,6 +26,12 @@
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 /* Sub-block A registers, relative to sub-block A address */
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 #define STM_SAI_PDMCR_REGX	0x40
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 #define STM_SAI_PDMLY_REGX	0x44
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+
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+/* Hardware configuration registers */
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+#define STM_SAI_HWCFGR		0x3F0
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+#define STM_SAI_VERR		0x3F4
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+#define STM_SAI_IDR		0x3F8
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+#define STM_SAI_SIDR		0x3FC
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 /******************** Bit definition for SAI_GCR register *******************/
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 #define SAI_GCR_SYNCIN_SHIFT	0
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@@ -82,7 +78,7 @@
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 #define SAI_XCR1_NODIV		BIT(SAI_XCR1_NODIV_SHIFT)
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 #define SAI_XCR1_MCKDIV_SHIFT	20
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-#define SAI_XCR1_MCKDIV_WIDTH(x)	(((x) == SAI_STM32F4) ? 4 : 6)
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+#define SAI_XCR1_MCKDIV_WIDTH(x)	(((x) == STM_SAI_STM32F4) ? 4 : 6)
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 #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
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 				SAI_XCR1_MCKDIV_SHIFT)
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 #define SAI_XCR1_MCKDIV_SET(x)	((x) << SAI_XCR1_MCKDIV_SHIFT)
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@@ -90,6 +86,9 @@
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 #define SAI_XCR1_OSR_SHIFT	26
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 #define SAI_XCR1_OSR		BIT(SAI_XCR1_OSR_SHIFT)
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+
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+#define SAI_XCR1_MCKEN_SHIFT	27
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+#define SAI_XCR1_MCKEN		BIT(SAI_XCR1_MCKEN_SHIFT)
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 /******************* Bit definition for SAI_XCR2 register *******************/
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 #define SAI_XCR2_FTH_SHIFT	0
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@@ -231,8 +230,33 @@
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 #define SAI_PDMDLY_4R_MASK	GENMASK(30, SAI_PDMDLY_4R_SHIFT)
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 #define SAI_PDMDLY_4R_WIDTH	3
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-#define STM_SAI_IS_F4(ip)	((ip)->conf->version == SAI_STM32F4)
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-#define STM_SAI_IS_H7(ip)	((ip)->conf->version == SAI_STM32H7)
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+/* Registers below apply to SAI version 2.1 and more */
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+
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+/* Bit definition for SAI_HWCFGR register */
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+#define SAI_HWCFGR_FIFO_SIZE	GENMASK(7, 0)
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+#define SAI_HWCFGR_SPDIF_PDM	GENMASK(11, 8)
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+#define SAI_HWCFGR_REGOUT	GENMASK(19, 12)
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+
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+/* Bit definition for SAI_VERR register */
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+#define SAI_VERR_MIN_MASK	GENMASK(3, 0)
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+#define SAI_VERR_MAJ_MASK	GENMASK(7, 4)
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+
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+/* Bit definition for SAI_IDR register */
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+#define SAI_IDR_ID_MASK		GENMASK(31, 0)
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+
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+/* Bit definition for SAI_SIDR register */
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+#define SAI_SIDR_ID_MASK	GENMASK(31, 0)
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+
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+#define SAI_IPIDR_NUMBER	0x00130031
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+
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+/* SAI version numbers are 1.x for F4. Major version number set to 1 for F4 */
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+#define STM_SAI_STM32F4		BIT(4)
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+/* Dummy version number for H7 socs and next */
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+#define STM_SAI_STM32H7		0x0
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+
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+#define STM_SAI_IS_F4(ip)	((ip)->conf.version == STM_SAI_STM32F4)
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+#define STM_SAI_HAS_SPDIF_PDM(ip)\
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+				((ip)->pdata->conf.has_spdif_pdm)
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 enum stm32_sai_syncout {
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 	STM_SAI_SYNC_OUT_NONE,
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@@ -240,19 +264,16 @@
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 	STM_SAI_SYNC_OUT_B,
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 };
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-enum stm32_sai_version {
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-	SAI_STM32F4,
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-	SAI_STM32H7
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-};
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-
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 /**
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  * struct stm32_sai_conf - SAI configuration
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  * @version: SAI version
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- * @has_spdif: SAI S/PDIF support flag
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+ * @fifo_size: SAI fifo size as words number
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+ * @has_spdif_pdm: SAI S/PDIF and PDM features support flag
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  */
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 struct stm32_sai_conf {
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-	int version;
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-	bool has_spdif;
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+	u32 version;
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+	u32 fifo_size;
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+	bool has_spdif_pdm;
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 };
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 /**
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@@ -262,9 +283,10 @@
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  * @pclk: SAI bus clock
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  * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz
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  * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz
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- * @version: SOC version
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+ * @conf: SAI hardware capabitilites
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  * @irq: SAI interrupt line
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  * @set_sync: pointer to synchro mode configuration callback
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+ * @gcr: SAI Global Configuration Register
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  */
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 struct stm32_sai_data {
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 	struct platform_device *pdev;
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@@ -272,8 +294,9 @@
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 	struct clk *pclk;
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 	struct clk *clk_x8k;
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 	struct clk *clk_x11k;
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-	struct stm32_sai_conf *conf;
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+	struct stm32_sai_conf conf;
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 	int irq;
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 	int (*set_sync)(struct stm32_sai_data *sai,
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 			struct device_node *np_provider, int synco, int synci);
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+	u32 gcr;
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 };