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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | 3 | * skl_topology.h - Intel HDA Platform topology header file |
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3 | 4 | * |
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.. | .. |
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5 | 6 | * Author: Jeeja KP <jeeja.kp@intel.com> |
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6 | 7 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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7 | 8 | * |
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8 | | - * This program is free software; you can redistribute it and/or modify |
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9 | | - * it under the terms of the GNU General Public License as published by |
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10 | | - * the Free Software Foundation; version 2 of the License. |
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11 | | - * |
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12 | | - * This program is distributed in the hope that it will be useful, but |
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13 | | - * WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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15 | | - * General Public License for more details. |
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16 | | - * |
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17 | 9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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18 | | - * |
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19 | 10 | */ |
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20 | 11 | |
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21 | 12 | #ifndef __SKL_TOPOLOGY_H__ |
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.. | .. |
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106 | 97 | u8 number_of_channels; |
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107 | 98 | u8 valid_bit_depth; |
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108 | 99 | u8 sample_type; |
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109 | | - u8 reserved[1]; |
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| 100 | + u8 reserved; |
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110 | 101 | } __packed; |
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111 | 102 | |
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112 | 103 | struct skl_base_cfg { |
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113 | | - u32 cps; |
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| 104 | + u32 cpc; |
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114 | 105 | u32 ibs; |
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115 | 106 | u32 obs; |
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116 | 107 | u32 is_pages; |
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.. | .. |
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128 | 119 | struct skl_dma_control { |
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129 | 120 | u32 node_id; |
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130 | 121 | u32 config_length; |
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131 | | - u32 config_data[0]; |
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| 122 | + u32 config_data[]; |
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132 | 123 | } __packed; |
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133 | 124 | |
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134 | 125 | struct skl_cpr_cfg { |
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.. | .. |
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149 | 140 | enum skl_s_freq src_cfg; |
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150 | 141 | } __packed; |
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151 | 142 | |
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152 | | -struct notification_mask { |
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153 | | - u32 notify; |
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154 | | - u32 enable; |
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155 | | -} __packed; |
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156 | | - |
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157 | 143 | struct skl_up_down_mixer_cfg { |
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158 | 144 | struct skl_base_cfg base_cfg; |
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159 | 145 | enum skl_ch_cfg out_ch_cfg; |
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.. | .. |
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166 | 152 | |
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167 | 153 | struct skl_algo_cfg { |
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168 | 154 | struct skl_base_cfg base_cfg; |
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169 | | - char params[0]; |
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| 155 | + char params[]; |
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170 | 156 | } __packed; |
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171 | 157 | |
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172 | 158 | struct skl_base_outfmt_cfg { |
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.. | .. |
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224 | 210 | struct skl_uuid_inst_map { |
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225 | 211 | u16 inst_id; |
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226 | 212 | u16 reserved; |
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227 | | - uuid_le mod_uuid; |
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| 213 | + guid_t mod_uuid; |
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228 | 214 | } __packed; |
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229 | 215 | |
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230 | 216 | struct skl_kpb_params { |
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.. | .. |
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236 | 222 | }; |
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237 | 223 | |
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238 | 224 | struct skl_module_inst_id { |
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239 | | - uuid_le mod_uuid; |
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| 225 | + guid_t mod_uuid; |
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240 | 226 | int module_id; |
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241 | 227 | u32 instance_id; |
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242 | 228 | int pvt_id; |
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.. | .. |
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320 | 306 | struct skl_path_config configs[SKL_MAX_PATH_CONFIGS]; |
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321 | 307 | struct list_head w_list; |
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322 | 308 | bool passthru; |
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| 309 | + u32 pipe_config_idx; |
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323 | 310 | }; |
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324 | 311 | |
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325 | 312 | enum skl_module_state { |
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.. | .. |
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357 | 344 | struct skl_module_res { |
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358 | 345 | u8 id; |
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359 | 346 | u32 is_pages; |
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360 | | - u32 cps; |
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361 | 347 | u32 ibs; |
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362 | 348 | u32 obs; |
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363 | 349 | u32 dma_buffer_size; |
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.. | .. |
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369 | 355 | }; |
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370 | 356 | |
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371 | 357 | struct skl_module { |
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372 | | - uuid_le uuid; |
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| 358 | + guid_t uuid; |
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373 | 359 | u8 loadable; |
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374 | 360 | u8 input_pin_type; |
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375 | 361 | u8 output_pin_type; |
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.. | .. |
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398 | 384 | u8 out_queue_mask; |
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399 | 385 | u8 in_queue; |
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400 | 386 | u8 out_queue; |
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401 | | - u32 mcps; |
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402 | | - u32 ibs; |
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403 | | - u32 obs; |
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404 | 387 | u8 is_loadable; |
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405 | 388 | u8 core_id; |
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406 | 389 | u8 dev_type; |
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.. | .. |
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456 | 439 | SKL_CH_QUATRO = 4, |
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457 | 440 | }; |
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458 | 441 | |
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459 | | -static inline struct skl *get_skl_ctx(struct device *dev) |
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| 442 | +static inline struct skl_dev *get_skl_ctx(struct device *dev) |
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460 | 443 | { |
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461 | 444 | struct hdac_bus *bus = dev_get_drvdata(dev); |
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462 | 445 | |
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.. | .. |
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465 | 448 | |
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466 | 449 | int skl_tplg_be_update_params(struct snd_soc_dai *dai, |
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467 | 450 | struct skl_pipe_params *params); |
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468 | | -int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps, |
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| 451 | +int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps, |
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469 | 452 | u32 caps_size, u32 node_id); |
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470 | 453 | void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, |
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471 | 454 | struct skl_pipe_params *params, int stream); |
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472 | 455 | int skl_tplg_init(struct snd_soc_component *component, |
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473 | | - struct hdac_bus *ebus); |
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| 456 | + struct hdac_bus *bus); |
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| 457 | +void skl_tplg_exit(struct snd_soc_component *component, |
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| 458 | + struct hdac_bus *bus); |
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474 | 459 | struct skl_module_cfg *skl_tplg_fe_get_cpr_module( |
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475 | 460 | struct snd_soc_dai *dai, int stream); |
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476 | 461 | int skl_tplg_update_pipe_params(struct device *dev, |
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477 | 462 | struct skl_module_cfg *mconfig, struct skl_pipe_params *params); |
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478 | 463 | |
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479 | | -void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps); |
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480 | | -void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps); |
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| 464 | +void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps); |
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| 465 | +void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps); |
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481 | 466 | |
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482 | | -int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); |
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| 467 | +int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe); |
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483 | 468 | |
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484 | | -int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); |
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| 469 | +int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe); |
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485 | 470 | |
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486 | | -int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); |
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| 471 | +int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe); |
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487 | 472 | |
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488 | | -int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); |
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| 473 | +int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe); |
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489 | 474 | |
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490 | | -int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); |
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| 475 | +int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe); |
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491 | 476 | |
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492 | | -int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); |
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| 477 | +int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe); |
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493 | 478 | |
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494 | | -int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config); |
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| 479 | +int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *mconfig); |
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495 | 480 | |
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496 | | -int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg |
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497 | | - *src_module, struct skl_module_cfg *dst_module); |
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| 481 | +int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg |
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| 482 | + *src_mcfg, struct skl_module_cfg *dst_mcfg); |
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498 | 483 | |
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499 | | -int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg |
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500 | | - *src_module, struct skl_module_cfg *dst_module); |
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| 484 | +int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg |
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| 485 | + *src_mcfg, struct skl_module_cfg *dst_mcfg); |
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501 | 486 | |
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502 | | -int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, |
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| 487 | +int skl_set_module_params(struct skl_dev *skl, u32 *params, int size, |
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503 | 488 | u32 param_id, struct skl_module_cfg *mcfg); |
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504 | | -int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, |
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| 489 | +int skl_get_module_params(struct skl_dev *skl, u32 *params, int size, |
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505 | 490 | u32 param_id, struct skl_module_cfg *mcfg); |
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506 | 491 | |
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507 | 492 | struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, |
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.. | .. |
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515 | 500 | int skl_dai_load(struct snd_soc_component *cmp, int index, |
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516 | 501 | struct snd_soc_dai_driver *dai_drv, |
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517 | 502 | struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai); |
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518 | | -void skl_tplg_add_moduleid_in_bind_params(struct skl *skl, |
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| 503 | +void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl, |
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519 | 504 | struct snd_soc_dapm_widget *w); |
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520 | 505 | #endif |
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