add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/sound/soc/codecs/wm9713.c
..
..
@@ -1,13 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
1
2
 /*
2
3
  * wm9713.c  --  ALSA Soc WM9713 codec support
3
4
  *
4
5
  * Copyright 2006-10 Wolfson Microelectronics PLC.
5
6
  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
6
- *
7
- *  This program is free software; you can redistribute  it and/or modify it
8
- *  under  the terms of  the GNU General  Public License as published by the
9
- *  Free Software Foundation;  either version 2 of the  License, or (at your
10
- *  option) any later version.
11
7
  *
12
8
  *  Features:-
13
9
  *
..
..
@@ -759,7 +755,7 @@
759
755
 	u64 Kpart;
760
756
 	unsigned int K, Ndiv, Nmod, target;
761
757
 
762
-	/* The the PLL output is always 98.304MHz. */
758
+	/* The PLL output is always 98.304MHz. */
763
759
 	target = 98304000;
764
760
 
765
761
 	/* If the input frequency is over 14.4MHz then scale it down. */
..
..
@@ -811,7 +807,7 @@
811
807
 	pll_div->k = K;
812
808
 }
813
809
 
814
-/**
810
+/*
815
811
  * Please note that changing the PLL input frequency may require
816
812
  * resynchronisation with the AC97 controller.
817
813
  */
..
..
@@ -943,7 +939,7 @@
943
939
 		unsigned int fmt)
944
940
 {
945
941
 	struct snd_soc_component *component = codec_dai->component;
946
-	u16 gpio = snd_soc_component_read32(component, AC97_GPIO_CFG) & 0xffc5;
942
+	u16 gpio = snd_soc_component_read(component, AC97_GPIO_CFG) & 0xffc5;
947
943
 	u16 reg = 0x8000;
948
944
 
949
945
 	/* clock masters */