add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/sound/soc/codecs/wm8961.c
..
..
@@ -1,13 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * wm8961.c  --  WM8961 ALSA SoC Audio driver
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  *
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  * Copyright 2009-10 Wolfson Microelectronics, plc
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  *
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  * Author: Mark Brown
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Currently unimplemented features:
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  *  - ALC
..
..
@@ -195,10 +192,10 @@
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 			   struct snd_kcontrol *kcontrol, int event)
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 {
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 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
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-	u16 hp_reg = snd_soc_component_read32(component, WM8961_ANALOGUE_HP_0);
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-	u16 cp_reg = snd_soc_component_read32(component, WM8961_CHARGE_PUMP_1);
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-	u16 pwr_reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_2);
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-	u16 dcs_reg = snd_soc_component_read32(component, WM8961_DC_SERVO_1);
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+	u16 hp_reg = snd_soc_component_read(component, WM8961_ANALOGUE_HP_0);
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+	u16 cp_reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_1);
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+	u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);
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+	u16 dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);
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 	int timeout = 500;
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200
 
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 	if (event & SND_SOC_DAPM_POST_PMU) {
..
..
@@ -232,7 +229,7 @@
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 		snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);
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 		do {
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 			msleep(1);
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-			dcs_reg = snd_soc_component_read32(component, WM8961_DC_SERVO_1);
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+			dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);
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 		} while (--timeout &&
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 			 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
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 				WM8961_DCS_TRIG_STARTUP_HPL));
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..
@@ -287,8 +284,8 @@
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 			    struct snd_kcontrol *kcontrol, int event)
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 {
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 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
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-	u16 pwr_reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_2);
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-	u16 spk_reg = snd_soc_component_read32(component, WM8961_CLASS_D_CONTROL_1);
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+	u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);
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+	u16 spk_reg = snd_soc_component_read(component, WM8961_CLASS_D_CONTROL_1);
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 	if (event & SND_SOC_DAPM_POST_PMU) {
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 		/* Enable the PGA */
..
..
@@ -524,7 +521,7 @@
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 		    abs(wm8961_srate[best].rate - fs))
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 			best = i;
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 	}
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-	reg = snd_soc_component_read32(component, WM8961_ADDITIONAL_CONTROL_3);
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+	reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_3);
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 	reg &= ~WM8961_SAMPLE_RATE_MASK;
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 	reg |= wm8961_srate[best].val;
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 	snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_3, reg);
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@@ -557,12 +554,12 @@
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 		wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
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 		wm8961->sysclk / fs);
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-	reg = snd_soc_component_read32(component, WM8961_CLOCKING_4);
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+	reg = snd_soc_component_read(component, WM8961_CLOCKING_4);
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 	reg &= ~WM8961_CLK_SYS_RATE_MASK;
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 	reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
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 	snd_soc_component_write(component, WM8961_CLOCKING_4, reg);
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-	reg = snd_soc_component_read32(component, WM8961_AUDIO_INTERFACE_0);
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+	reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);
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 	reg &= ~WM8961_WL_MASK;
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 	switch (params_width(params)) {
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 	case 16:
..
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@@ -582,7 +579,7 @@
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 	snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, reg);
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 	/* Sloping stop-band filter is recommended for <= 24kHz */
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-	reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_2);
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+	reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);
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 	if (fs <= 24000)
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 		reg |= WM8961_DACSLOPE;
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 	else
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@@ -598,7 +595,7 @@
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 {
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 	struct snd_soc_component *component = dai->component;
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 	struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);
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-	u16 reg = snd_soc_component_read32(component, WM8961_CLOCKING1);
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+	u16 reg = snd_soc_component_read(component, WM8961_CLOCKING1);
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 	if (freq > 33000000) {
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 		dev_err(component->dev, "MCLK must be <33MHz\n");
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@@ -624,7 +621,7 @@
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 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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 {
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 	struct snd_soc_component *component = dai->component;
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-	u16 aif = snd_soc_component_read32(component, WM8961_AUDIO_INTERFACE_0);
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+	u16 aif = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);
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 	aif &= ~(WM8961_BCLKINV | WM8961_LRP |
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 		 WM8961_MS | WM8961_FORMAT_MASK);
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@@ -653,7 +650,7 @@
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 	case SND_SOC_DAIFMT_DSP_B:
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 		aif |= WM8961_LRP;
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-		/* fall through */
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+		fallthrough;
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 	case SND_SOC_DAIFMT_DSP_A:
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 		aif |= 3;
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 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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@@ -691,7 +688,7 @@
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 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
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 {
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 	struct snd_soc_component *component = dai->component;
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-	u16 reg = snd_soc_component_read32(component, WM8961_ADDITIONAL_CONTROL_2);
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+	u16 reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_2);
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 	if (tristate)
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 		reg |= WM8961_TRIS;
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@@ -701,10 +698,10 @@
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 	return snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_2, reg);
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 }
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-static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
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+static int wm8961_mute(struct snd_soc_dai *dai, int mute, int direction)
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 {
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 	struct snd_soc_component *component = dai->component;
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-	u16 reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_1);
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+	u16 reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_1);
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 	if (mute)
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 		reg |= WM8961_DACMU;
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@@ -723,14 +720,14 @@
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 	switch (div_id) {
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 	case WM8961_BCLK:
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-		reg = snd_soc_component_read32(component, WM8961_CLOCKING2);
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+		reg = snd_soc_component_read(component, WM8961_CLOCKING2);
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 		reg &= ~WM8961_BCLKDIV_MASK;
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 		reg |= div;
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 		snd_soc_component_write(component, WM8961_CLOCKING2, reg);
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 		break;
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 	case WM8961_LRCLK:
733
-		reg = snd_soc_component_read32(component, WM8961_AUDIO_INTERFACE_2);
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+		reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_2);
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 		reg &= ~WM8961_LRCLK_RATE_MASK;
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 		reg |= div;
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 		snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_2, reg);
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@@ -760,12 +757,12 @@
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 	case SND_SOC_BIAS_PREPARE:
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 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
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 			/* Enable bias generation */
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-			reg = snd_soc_component_read32(component, WM8961_ANTI_POP);
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+			reg = snd_soc_component_read(component, WM8961_ANTI_POP);
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 			reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
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 			snd_soc_component_write(component, WM8961_ANTI_POP, reg);
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 			/* VMID=2*50k, VREF */
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-			reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1);
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+			reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
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 			reg &= ~WM8961_VMIDSEL_MASK;
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 			reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
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 			snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
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@@ -775,17 +772,17 @@
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 	case SND_SOC_BIAS_STANDBY:
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 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
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 			/* VREF off */
778
-			reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1);
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+			reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
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 			reg &= ~WM8961_VREF;
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 			snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
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 			/* Bias generation off */
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-			reg = snd_soc_component_read32(component, WM8961_ANTI_POP);
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+			reg = snd_soc_component_read(component, WM8961_ANTI_POP);
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 			reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
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 			snd_soc_component_write(component, WM8961_ANTI_POP, reg);
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 			/* VMID off */
788
-			reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1);
785
+			reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
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 			reg &= ~WM8961_VMIDSEL_MASK;
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 			snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
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 		}
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@@ -809,9 +806,10 @@
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 	.hw_params = wm8961_hw_params,
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 	.set_sysclk = wm8961_set_sysclk,
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 	.set_fmt = wm8961_set_fmt,
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-	.digital_mute = wm8961_digital_mute,
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+	.mute_stream = wm8961_mute,
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 	.set_tristate = wm8961_set_tristate,
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811
 	.set_clkdiv = wm8961_set_clkdiv,
812
+	.no_capture_mute = 1,
815
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 };
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 static struct snd_soc_dai_driver wm8961_dai = {
..
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@@ -836,35 +834,35 @@
836
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 	u16 reg;
837
835
 
838
836
 	/* Enable class W */
839
-	reg = snd_soc_component_read32(component, WM8961_CHARGE_PUMP_B);
837
+	reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_B);
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 	reg |= WM8961_CP_DYN_PWR_MASK;
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 	snd_soc_component_write(component, WM8961_CHARGE_PUMP_B, reg);
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 	/* Latch volume update bits (right channel only, we always
844
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 	 * write both out) and default ZC on. */
845
-	reg = snd_soc_component_read32(component, WM8961_ROUT1_VOLUME);
843
+	reg = snd_soc_component_read(component, WM8961_ROUT1_VOLUME);
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 	snd_soc_component_write(component, WM8961_ROUT1_VOLUME,
847
845
 		     reg | WM8961_LO1ZC | WM8961_OUT1VU);
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 	snd_soc_component_write(component, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
849
-	reg = snd_soc_component_read32(component, WM8961_ROUT2_VOLUME);
847
+	reg = snd_soc_component_read(component, WM8961_ROUT2_VOLUME);
850
848
 	snd_soc_component_write(component, WM8961_ROUT2_VOLUME,
851
849
 		     reg | WM8961_SPKRZC | WM8961_SPKVU);
852
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 	snd_soc_component_write(component, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
853
851
 
854
-	reg = snd_soc_component_read32(component, WM8961_RIGHT_ADC_VOLUME);
852
+	reg = snd_soc_component_read(component, WM8961_RIGHT_ADC_VOLUME);
855
853
 	snd_soc_component_write(component, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
856
-	reg = snd_soc_component_read32(component, WM8961_RIGHT_INPUT_VOLUME);
854
+	reg = snd_soc_component_read(component, WM8961_RIGHT_INPUT_VOLUME);
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 	snd_soc_component_write(component, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
858
856
 
859
857
 	/* Use soft mute by default */
860
-	reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_2);
858
+	reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);
861
859
 	reg |= WM8961_DACSMM;
862
860
 	snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);
863
861
 
864
862
 	/* Use automatic clocking mode by default; for now this is all
865
863
 	 * we support.
866
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 	 */
867
-	reg = snd_soc_component_read32(component, WM8961_CLOCKING_3);
865
+	reg = snd_soc_component_read(component, WM8961_CLOCKING_3);
868
866
 	reg &= ~WM8961_MANUAL_MODE;
869
867
 	snd_soc_component_write(component, WM8961_CLOCKING_3, reg);
870
868