add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/tty/serial/8250/8250_uniphier.c
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@@ -12,9 +12,6 @@
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12
 
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 #include "8250.h"
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14
 
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-/* Most (but not all) of UniPhier UART devices have 64-depth FIFO. */
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-#define UNIPHIER_UART_DEFAULT_FIFO_SIZE	64
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-
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 /*
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  * This hardware is similar to 8250, but its register map is a bit different:
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  *   - MMIO32 (regshift = 2)
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@@ -78,7 +75,7 @@
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 		break;
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 	case UART_LCR:
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 		valshift = 8;
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-		/* fall through */
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+		fallthrough;
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 	case UART_MCR:
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 		offset = UNIPHIER_UART_LCR_MCR;
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 		break;
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@@ -104,7 +101,7 @@
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 	case UART_SCR:
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 		/* No SCR for this hardware.  Use CHAR as a scratch register */
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 		valshift = 8;
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-		/* fall through */
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+		fallthrough;
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 	case UART_FCR:
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 		offset = UNIPHIER_UART_CHAR_FCR;
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 		break;
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@@ -112,7 +109,7 @@
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 		valshift = 8;
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 		/* Divisor latch access bit does not exist. */
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 		value &= ~UART_LCR_DLAB;
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-		/* fall through */
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+		fallthrough;
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 	case UART_MCR:
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 		offset = UNIPHIER_UART_LCR_MCR;
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 		break;
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@@ -158,42 +155,6 @@
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 	writel(value, up->port.membase + UNIPHIER_UART_DLR);
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 }
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-static int uniphier_of_serial_setup(struct device *dev, struct uart_port *port,
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-				    struct uniphier8250_priv *priv)
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-{
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-	int ret;
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-	u32 prop;
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-	struct device_node *np = dev->of_node;
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-
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-	ret = of_alias_get_id(np, "serial");
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-	if (ret < 0) {
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-		dev_err(dev, "failed to get alias id\n");
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-		return ret;
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-	}
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-	port->line = ret;
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-
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-	/* Get clk rate through clk driver */
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-	priv->clk = devm_clk_get(dev, NULL);
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-	if (IS_ERR(priv->clk)) {
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-		dev_err(dev, "failed to get clock\n");
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-		return PTR_ERR(priv->clk);
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-	}
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-
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-	ret = clk_prepare_enable(priv->clk);
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-	if (ret < 0)
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-		return ret;
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-
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-	port->uartclk = clk_get_rate(priv->clk);
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-
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-	/* Check for fifo size */
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-	if (of_property_read_u32(np, "fifo-size", &prop) == 0)
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-		port->fifosize = prop;
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-	else
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-		port->fifosize = UNIPHIER_UART_DEFAULT_FIFO_SIZE;
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-
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-	return 0;
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-}
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-
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 static int uniphier_uart_probe(struct platform_device *pdev)
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 {
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 	struct device *dev = &pdev->dev;
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@@ -215,10 +176,8 @@
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 		return -ENOMEM;
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 	irq = platform_get_irq(pdev, 0);
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-	if (irq < 0) {
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-		dev_err(dev, "failed to get IRQ number\n");
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+	if (irq < 0)
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 		return irq;
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-	}
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 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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 	if (!priv)
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@@ -226,9 +185,24 @@
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 	memset(&up, 0, sizeof(up));
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-	ret = uniphier_of_serial_setup(dev, &up.port, priv);
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-	if (ret < 0)
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+	ret = of_alias_get_id(dev->of_node, "serial");
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+	if (ret < 0) {
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+		dev_err(dev, "failed to get alias id\n");
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 		return ret;
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+	}
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+	up.port.line = ret;
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+
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+	priv->clk = devm_clk_get(dev, NULL);
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+	if (IS_ERR(priv->clk)) {
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+		dev_err(dev, "failed to get clock\n");
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+		return PTR_ERR(priv->clk);
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+	}
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+
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+	ret = clk_prepare_enable(priv->clk);
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+	if (ret)
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+		return ret;
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+
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+	up.port.uartclk = clk_get_rate(priv->clk);
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 	spin_lock_init(&priv->atomic_write_lock);
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@@ -241,10 +215,14 @@
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 	up.port.type = PORT_16550A;
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 	up.port.iotype = UPIO_MEM32;
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+	up.port.fifosize = 64;
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 	up.port.regshift = UNIPHIER_UART_REGSHIFT;
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 	up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE;
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 	up.capabilities = UART_CAP_FIFO;
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+	if (of_property_read_bool(dev->of_node, "auto-flow-control"))
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+		up.capabilities |= UART_CAP_AFE;
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+
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 	up.port.serial_in = uniphier_serial_in;
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 	up.port.serial_out = uniphier_serial_out;
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 	up.dl_read = uniphier_serial_dl_read;