~hc/RK356X_SDK_RELEASE.git

..	..	@@ -43,14 +43,31 @@
43	43	void (exit)(struct pci_dev dev);
44	44	};
45	45
46		-#define PCI_NUM_BAR_RESOURCES 6
	46	+struct f815xxa_data {
	47	+ spinlock_t lock;
	48	+ int idx;
	49	+};
47	50
48	51	struct serial_private {
49	52	struct pci_dev *dev;
50	53	unsigned int nr;
51	54	struct pci_serial_quirk *quirk;
52	55	const struct pciserial_board *board;
53		- int line[0];
	56	+ int line[];
	57	+};
	58	+
	59	+#define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
	60	+
	61	+static const struct pci_device_id pci_use_msi[] = {
	62	+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
	63	+ 0xA000, 0x1000) },
	64	+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
	65	+ 0xA000, 0x1000) },
	66	+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
	67	+ 0xA000, 0x1000) },
	68	+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
	69	+ PCI_ANY_ID, PCI_ANY_ID) },
	70	+ { }
54	71	};
55	72
56	73	static int pci_default_setup(struct serial_private*,
..	..	@@ -58,13 +75,12 @@
58	75
59	76	static void moan_device(const char str, struct pci_dev dev)
60	77	{
61		- dev_err(&dev->dev,
62		- "%s: %s\n"
	78	+ pci_err(dev, "%s\n"
63	79	"Please send the output of lspci -vv, this\n"
64	80	"message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65	81	"manufacturer and name of serial board or\n"
66	82	"modem board to <linux-serial@vger.kernel.org>.\n",
67		- pci_name(dev), str, dev->vendor, dev->device,
	83	+ str, dev->vendor, dev->device,
68	84	dev->subsystem_vendor, dev->subsystem_device);
69	85	}
70	86
..	..	@@ -74,7 +90,7 @@
74	90	{
75	91	struct pci_dev *dev = priv->dev;
76	92
77		- if (bar >= PCI_NUM_BAR_RESOURCES)
	93	+ if (bar >= PCI_STD_NUM_BARS)
78	94	return -EINVAL;
79	95
80	96	if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
..	..	@@ -221,7 +237,7 @@
221	237	/* is firmware started? */
222	238	pci_read_config_dword(dev, 0x44, &oldval);
223	239	if (oldval == 0x00001000L) { /* RESET value */
224		- dev_dbg(&dev->dev, "Local i960 firmware missing\n");
	240	+ pci_dbg(dev, "Local i960 firmware missing\n");
225	241	return -ENODEV;
226	242	}
227	243	return 0;
..	..	@@ -262,7 +278,7 @@
262	278	/*
263	279	* enable/disable interrupts
264	280	*/
265		- p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
	281	+ p = ioremap(pci_resource_start(dev, 0), 0x80);
266	282	if (p == NULL)
267	283	return -ENOMEM;
268	284	writel(irq_config, p + 0x4c);
..	..	@@ -286,7 +302,7 @@
286	302	/*
287	303	* disable interrupts
288	304	*/
289		- p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
	305	+ p = ioremap(pci_resource_start(dev, 0), 0x80);
290	306	if (p != NULL) {
291	307	writel(0, p + 0x4c);
292	308
..	..	@@ -462,7 +478,7 @@
462	478	break;
463	479	}
464	480
465		- p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
	481	+ p = ioremap(pci_resource_start(dev, 0), 0x80);
466	482	if (p == NULL)
467	483	return -ENOMEM;
468	484
..	..	@@ -571,9 +587,8 @@
571	587	* (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
572	588	*/
573	589	if ((dev->subsystem_device & 0x00f0) >= 0x70) {
574		- dev_info(&dev->dev,
575		- "ignoring Timedia subdevice %04x for parport_serial\n",
576		- dev->subsystem_device);
	590	+ pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
	591	+ dev->subsystem_device);
577	592	return -ENODEV;
578	593	}
579	594
..	..	@@ -618,7 +633,7 @@
618	633	break;
619	634	case 3:
620	635	offset = board->uart_offset;
621		- /* FALLTHROUGH */
	636	+ fallthrough;
622	637	case 4: /* BAR 2 */
623	638	case 5: /* BAR 3 */
624	639	case 6: /* BAR 4 */
..	..	@@ -810,8 +825,7 @@
810	825	if (sub_serports > 0)
811	826	return sub_serports;
812	827
813		- dev_err(&dev->dev,
814		- "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
	828	+ pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
815	829	return 0;
816	830	}
817	831
..	..	@@ -880,18 +894,16 @@
880	894	/* enable IO_Space bit */
881	895	#define ITE_887x_POSIO_ENABLE (1 << 31)
882	896
	897	+/* inta_addr are the configuration addresses of the ITE */
	898	+static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
883	899	static int pci_ite887x_init(struct pci_dev *dev)
884	900	{
885		- /* inta_addr are the configuration addresses of the ITE */
886		- static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
887		- 0x200, 0x280, 0 };
888	901	int ret, i, type;
889	902	struct resource *iobase = NULL;
890	903	u32 miscr, uartbar, ioport;
891	904
892	905	/* search for the base-ioport */
893		- i = 0;
894		- while (inta_addr[i] && iobase == NULL) {
	906	+ for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
895	907	iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
896	908	"ite887x");
897	909	if (iobase != NULL) {
..	..	@@ -908,13 +920,11 @@
908	920	break;
909	921	}
910	922	release_region(iobase->start, ITE_887x_IOSIZE);
911		- iobase = NULL;
912	923	}
913		- i++;
914	924	}
915	925
916		- if (!inta_addr[i]) {
917		- dev_err(&dev->dev, "ite887x: could not find iobase\n");
	926	+ if (i == ARRAY_SIZE(inta_addr)) {
	927	+ pci_err(dev, "could not find iobase\n");
918	928	return -ENODEV;
919	929	}
920	930
..	..	@@ -984,43 +994,29 @@
984	994	}
985	995
986	996	/*
987		- * EndRun Technologies.
988		- * Determine the number of ports available on the device.
	997	+ * Oxford Semiconductor Inc.
	998	+ * Check if an OxSemi device is part of the Tornado range of devices.
989	999	*/
990	1000	#define PCI_VENDOR_ID_ENDRUN 0x7401
991	1001	#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
992	1002
993		-static int pci_endrun_init(struct pci_dev *dev)
	1003	+static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
994	1004	{
995		- u8 __iomem *p;
996		- unsigned long deviceID;
997		- unsigned int number_uarts = 0;
	1005	+ /* OxSemi Tornado devices are all 0xCxxx */
	1006	+ if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
	1007	+ (dev->device & 0xf000) != 0xc000)
	1008	+ return false;
998	1009
999		- /* EndRun device is all 0xexxx */
	1010	+ /* EndRun devices are all 0xExxx */
1000	1011	if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1001		- (dev->device & 0xf000) != 0xe000)
1002		- return 0;
	1012	+ (dev->device & 0xf000) != 0xe000)
	1013	+ return false;
1003	1014
1004		- p = pci_iomap(dev, 0, 5);
1005		- if (p == NULL)
1006		- return -ENOMEM;
1007		-
1008		- deviceID = ioread32(p);
1009		- /* EndRun device */
1010		- if (deviceID == 0x07000200) {
1011		- number_uarts = ioread8(p + 4);
1012		- dev_dbg(&dev->dev,
1013		- "%d ports detected on EndRun PCI Express device\n",
1014		- number_uarts);
1015		- }
1016		- pci_iounmap(dev, p);
1017		- return number_uarts;
	1015	+ return true;
1018	1016	}
1019	1017
1020	1018	/*
1021		- * Oxford Semiconductor Inc.
1022		- * Check that device is part of the Tornado range of devices, then determine
1023		- * the number of ports available on the device.
	1019	+ * Determine the number of ports available on a Tornado device.
1024	1020	*/
1025	1021	static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1026	1022	{
..	..	@@ -1028,9 +1024,7 @@
1028	1024	unsigned long deviceID;
1029	1025	unsigned int number_uarts = 0;
1030	1026
1031		- /* OxSemi Tornado devices are all 0xCxxx */
1032		- if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1033		- (dev->device & 0xF000) != 0xC000)
	1027	+ if (!pci_oxsemi_tornado_p(dev))
1034	1028	return 0;
1035	1029
1036	1030	p = pci_iomap(dev, 0, 5);
..	..	@@ -1041,9 +1035,10 @@
1041	1035	/* Tornado device */
1042	1036	if (deviceID == 0x07000200) {
1043	1037	number_uarts = ioread8(p + 4);
1044		- dev_dbg(&dev->dev,
1045		- "%d ports detected on Oxford PCI Express device\n",
1046		- number_uarts);
	1038	+ pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
	1039	+ number_uarts,
	1040	+ dev->vendor == PCI_VENDOR_ID_ENDRUN ?
	1041	+ "EndRun" : "Oxford");
1047	1042	}
1048	1043	pci_iounmap(dev, p);
1049	1044	return number_uarts;
..	..	@@ -1103,15 +1098,15 @@
1103	1098	{ 0, }
1104	1099	};
1105	1100
1106		-static int pci_quatech_amcc(u16 devid)
	1101	+static int pci_quatech_amcc(struct pci_dev *dev)
1107	1102	{
1108	1103	struct quatech_feature *qf = &quatech_cards[0];
1109	1104	while (qf->devid) {
1110		- if (qf->devid == devid)
	1105	+ if (qf->devid == dev->device)
1111	1106	return qf->amcc;
1112	1107	qf++;
1113	1108	}
1114		- pr_err("quatech: unknown port type '0x%04X'.\n", devid);
	1109	+ pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1115	1110	return 0;
1116	1111	};
1117	1112
..	..	@@ -1274,7 +1269,7 @@
1274	1269
1275	1270	static int pci_quatech_init(struct pci_dev *dev)
1276	1271	{
1277		- if (pci_quatech_amcc(dev->device)) {
	1272	+ if (pci_quatech_amcc(dev)) {
1278	1273	unsigned long base = pci_resource_start(dev, 0);
1279	1274	if (base) {
1280	1275	u32 tmp;
..	..	@@ -1298,7 +1293,7 @@
1298	1293	port->port.uartclk = pci_quatech_clock(port);
1299	1294	/* For now just warn about RS422 */
1300	1295	if (pci_quatech_rs422(port))
1301		- pr_warn("quatech: software control of RS422 features not currently supported.\n");
	1296	+ pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1302	1297	return pci_default_setup(priv, board, port, idx);
1303	1298	}
1304	1299
..	..	@@ -1326,8 +1321,65 @@
1326	1321
1327	1322	return setup_port(priv, port, bar, offset, board->reg_shift);
1328	1323	}
	1324	+static void
	1325	+pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
	1326	+ unsigned int quot, unsigned int quot_frac)
	1327	+{
	1328	+ int scr;
	1329	+ int lcr;
1329	1330
	1331	+ for (scr = 16; scr > 4; scr--) {
	1332	+ unsigned int maxrate = port->uartclk / scr;
	1333	+ unsigned int divisor = max(maxrate / baud, 1U);
	1334	+ int delta = maxrate / divisor - baud;
	1335	+
	1336	+ if (baud > maxrate + baud / 50)
	1337	+ continue;
	1338	+
	1339	+ if (delta > baud / 50)
	1340	+ divisor++;
	1341	+
	1342	+ if (divisor > 0xffff)
	1343	+ continue;
	1344	+
	1345	+ /* Update delta due to possible divisor change */
	1346	+ delta = maxrate / divisor - baud;
	1347	+ if (abs(delta) < baud / 50) {
	1348	+ lcr = serial_port_in(port, UART_LCR);
	1349	+ serial_port_out(port, UART_LCR, lcr \| 0x80);
	1350	+ serial_port_out(port, UART_DLL, divisor & 0xff);
	1351	+ serial_port_out(port, UART_DLM, divisor >> 8 & 0xff);
	1352	+ serial_port_out(port, 2, 16 - scr);
	1353	+ serial_port_out(port, UART_LCR, lcr);
	1354	+ return;
	1355	+ }
	1356	+ }
	1357	+}
1330	1358	static int pci_pericom_setup(struct serial_private *priv,
	1359	+ const struct pciserial_board *board,
	1360	+ struct uart_8250_port *port, int idx)
	1361	+{
	1362	+ unsigned int bar, offset = board->first_offset, maxnr;
	1363	+
	1364	+ bar = FL_GET_BASE(board->flags);
	1365	+ if (board->flags & FL_BASE_BARS)
	1366	+ bar += idx;
	1367	+ else
	1368	+ offset += idx * board->uart_offset;
	1369	+
	1370	+
	1371	+ maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
	1372	+ (board->reg_shift + 3);
	1373	+
	1374	+ if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
	1375	+ return 1;
	1376	+
	1377	+ port->port.set_divisor = pericom_do_set_divisor;
	1378	+
	1379	+ return setup_port(priv, port, bar, offset, board->reg_shift);
	1380	+}
	1381	+
	1382	+static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1331	1383	const struct pciserial_board *board,
1332	1384	struct uart_8250_port *port, int idx)
1333	1385	{
..	..	@@ -1347,6 +1399,8 @@
1347	1399
1348	1400	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1349	1401	return 1;
	1402	+
	1403	+ port->port.set_divisor = pericom_do_set_divisor;
1350	1404
1351	1405	return setup_port(priv, port, bar, offset, board->reg_shift);
1352	1406	}
..	..	@@ -1453,7 +1507,7 @@
1453	1507	/* Get the io address from configuration space */
1454	1508	pci_read_config_word(pdev, config_base + 4, &iobase);
1455	1509
1456		- dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
	1510	+ pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1457	1511
1458	1512	port->port.iotype = UPIO_PORT;
1459	1513	port->port.iobase = iobase;
..	..	@@ -1477,7 +1531,6 @@
1477	1531	resource_size_t bar_data[3];
1478	1532	u8 config_base;
1479	1533	struct serial_private *priv = pci_get_drvdata(dev);
1480		- struct uart_8250_port *port;
1481	1534
1482	1535	if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) \|\|
1483	1536	!(pci_resource_flags(dev, 4) & IORESOURCE_IO) \|\|
..	..	@@ -1524,13 +1577,7 @@
1524	1577
1525	1578	pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1526	1579
1527		- if (priv) {
1528		- /* re-apply RS232/485 mode when
1529		- * pciserial_resume_ports()
1530		- */
1531		- port = serial8250_get_port(priv->line[i]);
1532		- pci_fintek_rs485_config(&port->port, NULL);
1533		- } else {
	1580	+ if (!priv) {
1534	1581	/* First init without port data
1535	1582	* force init to RS232 Mode
1536	1583	*/
..	..	@@ -1541,12 +1588,83 @@
1541	1588	return max_port;
1542	1589	}
1543	1590
	1591	+static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
	1592	+{
	1593	+ struct f815xxa_data *data = p->private_data;
	1594	+ unsigned long flags;
	1595	+
	1596	+ spin_lock_irqsave(&data->lock, flags);
	1597	+ writeb(value, p->membase + offset);
	1598	+ readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
	1599	+ spin_unlock_irqrestore(&data->lock, flags);
	1600	+}
	1601	+
	1602	+static int pci_fintek_f815xxa_setup(struct serial_private *priv,
	1603	+ const struct pciserial_board *board,
	1604	+ struct uart_8250_port *port, int idx)
	1605	+{
	1606	+ struct pci_dev *pdev = priv->dev;
	1607	+ struct f815xxa_data *data;
	1608	+
	1609	+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	1610	+ if (!data)
	1611	+ return -ENOMEM;
	1612	+
	1613	+ data->idx = idx;
	1614	+ spin_lock_init(&data->lock);
	1615	+
	1616	+ port->port.private_data = data;
	1617	+ port->port.iotype = UPIO_MEM;
	1618	+ port->port.flags \|= UPF_IOREMAP;
	1619	+ port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
	1620	+ port->port.serial_out = f815xxa_mem_serial_out;
	1621	+
	1622	+ return 0;
	1623	+}
	1624	+
	1625	+static int pci_fintek_f815xxa_init(struct pci_dev *dev)
	1626	+{
	1627	+ u32 max_port, i;
	1628	+ int config_base;
	1629	+
	1630	+ if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
	1631	+ return -ENODEV;
	1632	+
	1633	+ switch (dev->device) {
	1634	+ case 0x1204: /* 4 ports */
	1635	+ case 0x1208: /* 8 ports */
	1636	+ max_port = dev->device & 0xff;
	1637	+ break;
	1638	+ case 0x1212: /* 12 ports */
	1639	+ max_port = 12;
	1640	+ break;
	1641	+ default:
	1642	+ return -EINVAL;
	1643	+ }
	1644	+
	1645	+ /* Set to mmio decode */
	1646	+ pci_write_config_byte(dev, 0x209, 0x40);
	1647	+
	1648	+ for (i = 0; i < max_port; ++i) {
	1649	+ /* UART0 configuration offset start from 0x2A0 */
	1650	+ config_base = 0x2A0 + 0x08 * i;
	1651	+
	1652	+ /* Select 128-byte FIFO and 8x FIFO threshold */
	1653	+ pci_write_config_byte(dev, config_base + 0x01, 0x33);
	1654	+
	1655	+ /* Enable UART I/O port */
	1656	+ pci_write_config_byte(dev, config_base + 0, 0x01);
	1657	+ }
	1658	+
	1659	+ return max_port;
	1660	+}
	1661	+
1544	1662	static int skip_tx_en_setup(struct serial_private *priv,
1545	1663	const struct pciserial_board *board,
1546	1664	struct uart_8250_port *port, int idx)
1547	1665	{
1548	1666	port->port.quirks \|= UPQ_NO_TXEN_TEST;
1549		- dev_dbg(&priv->dev->dev,
	1667	+ pci_dbg(priv->dev,
1550	1668	"serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1551	1669	priv->dev->vendor, priv->dev->device,
1552	1670	priv->dev->subsystem_vendor, priv->dev->subsystem_device);
..	..	@@ -1637,6 +1755,79 @@
1637	1755	return pci_default_setup(priv, board, port, idx);
1638	1756	}
1639	1757
	1758	+
	1759	+#define CH384_XINT_ENABLE_REG 0xEB
	1760	+#define CH384_XINT_ENABLE_BIT 0x02
	1761	+
	1762	+static int pci_wch_ch38x_init(struct pci_dev *dev)
	1763	+{
	1764	+ int max_port;
	1765	+ unsigned long iobase;
	1766	+
	1767	+
	1768	+ switch (dev->device) {
	1769	+ case 0x3853: /* 8 ports */
	1770	+ max_port = 8;
	1771	+ break;
	1772	+ default:
	1773	+ return -EINVAL;
	1774	+ }
	1775	+
	1776	+ iobase = pci_resource_start(dev, 0);
	1777	+ outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
	1778	+
	1779	+ return max_port;
	1780	+}
	1781	+
	1782	+static void pci_wch_ch38x_exit(struct pci_dev *dev)
	1783	+{
	1784	+ unsigned long iobase;
	1785	+
	1786	+ iobase = pci_resource_start(dev, 0);
	1787	+ outb(0x0, iobase + CH384_XINT_ENABLE_REG);
	1788	+}
	1789	+
	1790	+
	1791	+static int
	1792	+pci_sunix_setup(struct serial_private *priv,
	1793	+ const struct pciserial_board *board,
	1794	+ struct uart_8250_port *port, int idx)
	1795	+{
	1796	+ int bar;
	1797	+ int offset;
	1798	+
	1799	+ port->port.flags \|= UPF_FIXED_TYPE;
	1800	+ port->port.type = PORT_SUNIX;
	1801	+
	1802	+ if (idx < 4) {
	1803	+ bar = 0;
	1804	+ offset = idx * board->uart_offset;
	1805	+ } else {
	1806	+ bar = 1;
	1807	+ idx -= 4;
	1808	+ idx = div_s64_rem(idx, 4, &offset);
	1809	+ offset = idx * 64 + offset * board->uart_offset;
	1810	+ }
	1811	+
	1812	+ return setup_port(priv, port, bar, offset, 0);
	1813	+}
	1814	+
	1815	+static int
	1816	+pci_moxa_setup(struct serial_private *priv,
	1817	+ const struct pciserial_board *board,
	1818	+ struct uart_8250_port *port, int idx)
	1819	+{
	1820	+ unsigned int bar = FL_GET_BASE(board->flags);
	1821	+ int offset;
	1822	+
	1823	+ if (board->num_ports == 4 && idx == 3)
	1824	+ offset = 7 * board->uart_offset;
	1825	+ else
	1826	+ offset = idx * board->uart_offset;
	1827	+
	1828	+ return setup_port(priv, port, bar, offset, 0);
	1829	+}
	1830	+
1640	1831	#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1641	1832	#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1642	1833	#define PCI_DEVICE_ID_OCTPRO 0x0001
..	..	@@ -1648,6 +1839,8 @@
1648	1839	#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1649	1840	#define PCI_VENDOR_ID_ADVANTECH 0x13fe
1650	1841	#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
	1842	+#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
	1843	+#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
1651	1844	#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1652	1845	#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1653	1846	#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
..	..	@@ -1688,6 +1881,7 @@
1688	1881	#define PCIE_VENDOR_ID_WCH 0x1c00
1689	1882	#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1690	1883	#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
	1884	+#define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
1691	1885	#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1692	1886
1693	1887	#define PCI_VENDOR_ID_ACCESIO 0x494f
..	..	@@ -1726,6 +1920,18 @@
1726	1920	#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1727	1921
1728	1922
	1923	+#define PCI_DEVICE_ID_MOXA_CP102E 0x1024
	1924	+#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
	1925	+#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
	1926	+#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
	1927	+#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
	1928	+#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
	1929	+#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
	1930	+#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
	1931	+#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
	1932	+#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
	1933	+#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
	1934	+#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1729	1935
1730	1936	/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1731	1937	#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
..	..	@@ -1770,6 +1976,16 @@
1770	1976	.subvendor = PCI_ANY_ID,
1771	1977	.subdevice = PCI_ANY_ID,
1772	1978	.init = pci_hp_diva_init,
	1979	+ .setup = pci_hp_diva_setup,
	1980	+ },
	1981	+ /*
	1982	+ * HPE PCI serial device
	1983	+ */
	1984	+ {
	1985	+ .vendor = PCI_VENDOR_ID_HP_3PAR,
	1986	+ .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
	1987	+ .subvendor = PCI_ANY_ID,
	1988	+ .subdevice = PCI_ANY_ID,
1773	1989	.setup = pci_hp_diva_setup,
1774	1990	},
1775	1991	/*
..	..	@@ -1989,7 +2205,7 @@
1989	2205	.device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
1990	2206	.subvendor = PCI_ANY_ID,
1991	2207	.subdevice = PCI_ANY_ID,
1992		- .setup = pci_pericom_setup,
	2208	+ .setup = pci_pericom_setup_four_at_eight,
1993	2209	},
1994	2210	/*
1995	2211	* PLX
..	..	@@ -2026,107 +2242,120 @@
2026	2242	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2027	2243	.subvendor = PCI_ANY_ID,
2028	2244	.subdevice = PCI_ANY_ID,
2029		- .setup = pci_pericom_setup,
	2245	+ .setup = pci_pericom_setup_four_at_eight,
2030	2246	},
2031	2247	{
2032	2248	.vendor = PCI_VENDOR_ID_ACCESIO,
2033	2249	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2034	2250	.subvendor = PCI_ANY_ID,
2035	2251	.subdevice = PCI_ANY_ID,
2036		- .setup = pci_pericom_setup,
	2252	+ .setup = pci_pericom_setup_four_at_eight,
2037	2253	},
2038	2254	{
2039	2255	.vendor = PCI_VENDOR_ID_ACCESIO,
2040	2256	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2041	2257	.subvendor = PCI_ANY_ID,
2042	2258	.subdevice = PCI_ANY_ID,
2043		- .setup = pci_pericom_setup,
	2259	+ .setup = pci_pericom_setup_four_at_eight,
2044	2260	},
2045	2261	{
2046	2262	.vendor = PCI_VENDOR_ID_ACCESIO,
2047	2263	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2048	2264	.subvendor = PCI_ANY_ID,
2049	2265	.subdevice = PCI_ANY_ID,
2050		- .setup = pci_pericom_setup,
	2266	+ .setup = pci_pericom_setup_four_at_eight,
2051	2267	},
2052	2268	{
2053	2269	.vendor = PCI_VENDOR_ID_ACCESIO,
2054	2270	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2055	2271	.subvendor = PCI_ANY_ID,
2056	2272	.subdevice = PCI_ANY_ID,
2057		- .setup = pci_pericom_setup,
	2273	+ .setup = pci_pericom_setup_four_at_eight,
2058	2274	},
2059	2275	{
2060	2276	.vendor = PCI_VENDOR_ID_ACCESIO,
2061	2277	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2062	2278	.subvendor = PCI_ANY_ID,
2063	2279	.subdevice = PCI_ANY_ID,
2064		- .setup = pci_pericom_setup,
	2280	+ .setup = pci_pericom_setup_four_at_eight,
2065	2281	},
2066	2282	{
2067	2283	.vendor = PCI_VENDOR_ID_ACCESIO,
2068	2284	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2069	2285	.subvendor = PCI_ANY_ID,
2070	2286	.subdevice = PCI_ANY_ID,
2071		- .setup = pci_pericom_setup,
	2287	+ .setup = pci_pericom_setup_four_at_eight,
2072	2288	},
2073	2289	{
2074	2290	.vendor = PCI_VENDOR_ID_ACCESIO,
2075	2291	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2076	2292	.subvendor = PCI_ANY_ID,
2077	2293	.subdevice = PCI_ANY_ID,
2078		- .setup = pci_pericom_setup,
	2294	+ .setup = pci_pericom_setup_four_at_eight,
2079	2295	},
2080	2296	{
2081		- .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
	2297	+ .vendor = PCI_VENDOR_ID_ACCESIO,
2082	2298	.device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2083	2299	.subvendor = PCI_ANY_ID,
2084	2300	.subdevice = PCI_ANY_ID,
2085		- .setup = pci_pericom_setup,
	2301	+ .setup = pci_pericom_setup_four_at_eight,
	2302	+ },
	2303	+ {
	2304	+ .vendor = PCI_VENDOR_ID_ACCESIO,
	2305	+ .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
	2306	+ .subvendor = PCI_ANY_ID,
	2307	+ .subdevice = PCI_ANY_ID,
	2308	+ .setup = pci_pericom_setup_four_at_eight,
2086	2309	},
2087	2310	{
2088	2311	.vendor = PCI_VENDOR_ID_ACCESIO,
2089	2312	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2090	2313	.subvendor = PCI_ANY_ID,
2091	2314	.subdevice = PCI_ANY_ID,
2092		- .setup = pci_pericom_setup,
	2315	+ .setup = pci_pericom_setup_four_at_eight,
2093	2316	},
2094	2317	{
2095	2318	.vendor = PCI_VENDOR_ID_ACCESIO,
2096	2319	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2097	2320	.subvendor = PCI_ANY_ID,
2098	2321	.subdevice = PCI_ANY_ID,
2099		- .setup = pci_pericom_setup,
	2322	+ .setup = pci_pericom_setup_four_at_eight,
2100	2323	},
2101	2324	{
2102	2325	.vendor = PCI_VENDOR_ID_ACCESIO,
2103	2326	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2104	2327	.subvendor = PCI_ANY_ID,
2105	2328	.subdevice = PCI_ANY_ID,
2106		- .setup = pci_pericom_setup,
	2329	+ .setup = pci_pericom_setup_four_at_eight,
2107	2330	},
2108	2331	{
2109	2332	.vendor = PCI_VENDOR_ID_ACCESIO,
2110	2333	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2111	2334	.subvendor = PCI_ANY_ID,
2112	2335	.subdevice = PCI_ANY_ID,
2113		- .setup = pci_pericom_setup,
	2336	+ .setup = pci_pericom_setup_four_at_eight,
2114	2337	},
2115	2338	{
2116	2339	.vendor = PCI_VENDOR_ID_ACCESIO,
2117	2340	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2118	2341	.subvendor = PCI_ANY_ID,
2119	2342	.subdevice = PCI_ANY_ID,
2120		- .setup = pci_pericom_setup,
	2343	+ .setup = pci_pericom_setup_four_at_eight,
2121	2344	},
2122	2345	{
2123	2346	.vendor = PCI_VENDOR_ID_ACCESIO,
2124	2347	.device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2125	2348	.subvendor = PCI_ANY_ID,
2126	2349	.subdevice = PCI_ANY_ID,
2127		- .setup = pci_pericom_setup,
	2350	+ .setup = pci_pericom_setup_four_at_eight,
2128	2351	},
2129		- /*
	2352	+ {
	2353	+ .vendor = PCI_VENDOR_ID_ACCESIO,
	2354	+ .device = PCI_ANY_ID,
	2355	+ .subvendor = PCI_ANY_ID,
	2356	+ .subdevice = PCI_ANY_ID,
	2357	+ .setup = pci_pericom_setup,
	2358	+ }, /*
2130	2359	* SBS Technologies, Inc., PMC-OCTALPRO 232
2131	2360	*/
2132	2361	{
..	..	@@ -2222,21 +2451,14 @@
2222	2451	.setup = pci_timedia_setup,
2223	2452	},
2224	2453	/*
2225		- * SUNIX (Timedia) cards
2226		- * Do not "probe" for these cards as there is at least one combination
2227		- * card that should be handled by parport_pc that doesn't match the
2228		- * rule in pci_timedia_probe.
2229		- * It is part number is MIO5079A but its subdevice ID is 0x0102.
2230		- * There are some boards with part number SER5037AL that report
2231		- * subdevice ID 0x0002.
	2454	+ * Sunix PCI serial boards
2232	2455	*/
2233	2456	{
2234	2457	.vendor = PCI_VENDOR_ID_SUNIX,
2235	2458	.device = PCI_DEVICE_ID_SUNIX_1999,
2236	2459	.subvendor = PCI_VENDOR_ID_SUNIX,
2237	2460	.subdevice = PCI_ANY_ID,
2238		- .init = pci_timedia_init,
2239		- .setup = pci_timedia_setup,
	2461	+ .setup = pci_sunix_setup,
2240	2462	},
2241	2463	/*
2242	2464	* Xircom cards
..	..	@@ -2268,7 +2490,7 @@
2268	2490	.device = PCI_ANY_ID,
2269	2491	.subvendor = PCI_ANY_ID,
2270	2492	.subdevice = PCI_ANY_ID,
2271		- .init = pci_endrun_init,
	2493	+ .init = pci_oxsemi_tornado_init,
2272	2494	.setup = pci_default_setup,
2273	2495	},
2274	2496	/*
..	..	@@ -2452,6 +2674,16 @@
2452	2674	.subdevice = PCI_ANY_ID,
2453	2675	.setup = pci_wch_ch38x_setup,
2454	2676	},
	2677	+ /* WCH CH384 8S card (16850 clone) */
	2678	+ {
	2679	+ .vendor = PCIE_VENDOR_ID_WCH,
	2680	+ .device = PCIE_DEVICE_ID_WCH_CH384_8S,
	2681	+ .subvendor = PCI_ANY_ID,
	2682	+ .subdevice = PCI_ANY_ID,
	2683	+ .init = pci_wch_ch38x_init,
	2684	+ .exit = pci_wch_ch38x_exit,
	2685	+ .setup = pci_wch_ch38x_setup,
	2686	+ },
2455	2687	/*
2456	2688	* ASIX devices with FIFO bug
2457	2689	*/
..	..	@@ -2496,6 +2728,40 @@
2496	2728	.setup = pci_fintek_setup,
2497	2729	.init = pci_fintek_init,
2498	2730	},
	2731	+ /*
	2732	+ * MOXA
	2733	+ */
	2734	+ {
	2735	+ .vendor = PCI_VENDOR_ID_MOXA,
	2736	+ .device = PCI_ANY_ID,
	2737	+ .subvendor = PCI_ANY_ID,
	2738	+ .subdevice = PCI_ANY_ID,
	2739	+ .setup = pci_moxa_setup,
	2740	+ },
	2741	+ {
	2742	+ .vendor = 0x1c29,
	2743	+ .device = 0x1204,
	2744	+ .subvendor = PCI_ANY_ID,
	2745	+ .subdevice = PCI_ANY_ID,
	2746	+ .setup = pci_fintek_f815xxa_setup,
	2747	+ .init = pci_fintek_f815xxa_init,
	2748	+ },
	2749	+ {
	2750	+ .vendor = 0x1c29,
	2751	+ .device = 0x1208,
	2752	+ .subvendor = PCI_ANY_ID,
	2753	+ .subdevice = PCI_ANY_ID,
	2754	+ .setup = pci_fintek_f815xxa_setup,
	2755	+ .init = pci_fintek_f815xxa_init,
	2756	+ },
	2757	+ {
	2758	+ .vendor = 0x1c29,
	2759	+ .device = 0x1212,
	2760	+ .subvendor = PCI_ANY_ID,
	2761	+ .subdevice = PCI_ANY_ID,
	2762	+ .setup = pci_fintek_f815xxa_setup,
	2763	+ .init = pci_fintek_f815xxa_init,
	2764	+ },
2499	2765
2500	2766	/*
2501	2767	* Default "match everything" terminator entry
..	..	@@ -2525,15 +2791,6 @@
2525	2791	quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2526	2792	break;
2527	2793	return quirk;
2528		-}
2529		-
2530		-static inline int get_pci_irq(struct pci_dev *dev,
2531		- const struct pciserial_board *board)
2532		-{
2533		- if (board->flags & FL_NOIRQ)
2534		- return 0;
2535		- else
2536		- return dev->irq;
2537	2794	}
2538	2795
2539	2796	/*
..	..	@@ -2578,7 +2835,7 @@
2578	2835	pbn_b0_2_1843200,
2579	2836	pbn_b0_4_1843200,
2580	2837
2581		- pbn_b0_1_4000000,
	2838	+ pbn_b0_1_3906250,
2582	2839
2583	2840	pbn_b0_bt_1_115200,
2584	2841	pbn_b0_bt_2_115200,
..	..	@@ -2656,12 +2913,11 @@
2656	2913	pbn_panacom2,
2657	2914	pbn_panacom4,
2658	2915	pbn_plx_romulus,
2659		- pbn_endrun_2_4000000,
2660	2916	pbn_oxsemi,
2661		- pbn_oxsemi_1_4000000,
2662		- pbn_oxsemi_2_4000000,
2663		- pbn_oxsemi_4_4000000,
2664		- pbn_oxsemi_8_4000000,
	2917	+ pbn_oxsemi_1_3906250,
	2918	+ pbn_oxsemi_2_3906250,
	2919	+ pbn_oxsemi_4_3906250,
	2920	+ pbn_oxsemi_8_3906250,
2665	2921	pbn_intel_i960,
2666	2922	pbn_sgi_ioc3,
2667	2923	pbn_computone_4,
..	..	@@ -2684,12 +2940,28 @@
2684	2940	pbn_fintek_4,
2685	2941	pbn_fintek_8,
2686	2942	pbn_fintek_12,
	2943	+ pbn_fintek_F81504A,
	2944	+ pbn_fintek_F81508A,
	2945	+ pbn_fintek_F81512A,
2687	2946	pbn_wch382_2,
2688	2947	pbn_wch384_4,
	2948	+ pbn_wch384_8,
2689	2949	pbn_pericom_PI7C9X7951,
2690	2950	pbn_pericom_PI7C9X7952,
2691	2951	pbn_pericom_PI7C9X7954,
2692	2952	pbn_pericom_PI7C9X7958,
	2953	+ pbn_sunix_pci_1s,
	2954	+ pbn_sunix_pci_2s,
	2955	+ pbn_sunix_pci_4s,
	2956	+ pbn_sunix_pci_8s,
	2957	+ pbn_sunix_pci_16s,
	2958	+ pbn_titan_1_4000000,
	2959	+ pbn_titan_2_4000000,
	2960	+ pbn_titan_4_4000000,
	2961	+ pbn_titan_8_4000000,
	2962	+ pbn_moxa8250_2p,
	2963	+ pbn_moxa8250_4p,
	2964	+ pbn_moxa8250_8p,
2693	2965	};
2694	2966
2695	2967	/*
..	..	@@ -2792,10 +3064,10 @@
2792	3064	.uart_offset = 8,
2793	3065	},
2794	3066
2795		- [pbn_b0_1_4000000] = {
	3067	+ [pbn_b0_1_3906250] = {
2796	3068	.flags = FL_BASE0,
2797	3069	.num_ports = 1,
2798		- .base_baud = 4000000,
	3070	+ .base_baud = 3906250,
2799	3071	.uart_offset = 8,
2800	3072	},
2801	3073
..	..	@@ -3167,20 +3439,6 @@
3167	3439	},
3168	3440
3169	3441	/*
3170		- * EndRun Technologies
3171		- * Uses the size of PCI Base region 0 to
3172		- * signal now many ports are available
3173		- * 2 port 952 Uart support
3174		- */
3175		- [pbn_endrun_2_4000000] = {
3176		- .flags = FL_BASE0,
3177		- .num_ports = 2,
3178		- .base_baud = 4000000,
3179		- .uart_offset = 0x200,
3180		- .first_offset = 0x1000,
3181		- },
3182		-
3183		- /*
3184	3442	* This board uses the size of PCI Base region 0 to
3185	3443	* signal now many ports are available
3186	3444	*/
..	..	@@ -3190,31 +3448,31 @@
3190	3448	.base_baud = 115200,
3191	3449	.uart_offset = 8,
3192	3450	},
3193		- [pbn_oxsemi_1_4000000] = {
	3451	+ [pbn_oxsemi_1_3906250] = {
3194	3452	.flags = FL_BASE0,
3195	3453	.num_ports = 1,
3196		- .base_baud = 4000000,
	3454	+ .base_baud = 3906250,
3197	3455	.uart_offset = 0x200,
3198	3456	.first_offset = 0x1000,
3199	3457	},
3200		- [pbn_oxsemi_2_4000000] = {
	3458	+ [pbn_oxsemi_2_3906250] = {
3201	3459	.flags = FL_BASE0,
3202	3460	.num_ports = 2,
3203		- .base_baud = 4000000,
	3461	+ .base_baud = 3906250,
3204	3462	.uart_offset = 0x200,
3205	3463	.first_offset = 0x1000,
3206	3464	},
3207		- [pbn_oxsemi_4_4000000] = {
	3465	+ [pbn_oxsemi_4_3906250] = {
3208	3466	.flags = FL_BASE0,
3209	3467	.num_ports = 4,
3210		- .base_baud = 4000000,
	3468	+ .base_baud = 3906250,
3211	3469	.uart_offset = 0x200,
3212	3470	.first_offset = 0x1000,
3213	3471	},
3214		- [pbn_oxsemi_8_4000000] = {
	3472	+ [pbn_oxsemi_8_3906250] = {
3215	3473	.flags = FL_BASE0,
3216	3474	.num_ports = 8,
3217		- .base_baud = 4000000,
	3475	+ .base_baud = 3906250,
3218	3476	.uart_offset = 0x200,
3219	3477	.first_offset = 0x1000,
3220	3478	},
..	..	@@ -3386,6 +3644,21 @@
3386	3644	.base_baud = 115200,
3387	3645	.first_offset = 0x40,
3388	3646	},
	3647	+ [pbn_fintek_F81504A] = {
	3648	+ .num_ports = 4,
	3649	+ .uart_offset = 8,
	3650	+ .base_baud = 115200,
	3651	+ },
	3652	+ [pbn_fintek_F81508A] = {
	3653	+ .num_ports = 8,
	3654	+ .uart_offset = 8,
	3655	+ .base_baud = 115200,
	3656	+ },
	3657	+ [pbn_fintek_F81512A] = {
	3658	+ .num_ports = 12,
	3659	+ .uart_offset = 8,
	3660	+ .base_baud = 115200,
	3661	+ },
3389	3662	[pbn_wch382_2] = {
3390	3663	.flags = FL_BASE0,
3391	3664	.num_ports = 2,
..	..	@@ -3399,6 +3672,13 @@
3399	3672	.base_baud = 115200,
3400	3673	.uart_offset = 8,
3401	3674	.first_offset = 0xC0,
	3675	+ },
	3676	+ [pbn_wch384_8] = {
	3677	+ .flags = FL_BASE0,
	3678	+ .num_ports = 8,
	3679	+ .base_baud = 115200,
	3680	+ .uart_offset = 8,
	3681	+ .first_offset = 0x00,
3402	3682	},
3403	3683	/*
3404	3684	* Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
..	..	@@ -3427,6 +3707,77 @@
3427	3707	.base_baud = 921600,
3428	3708	.uart_offset = 0x8,
3429	3709	},
	3710	+ [pbn_sunix_pci_1s] = {
	3711	+ .num_ports = 1,
	3712	+ .base_baud = 921600,
	3713	+ .uart_offset = 0x8,
	3714	+ },
	3715	+ [pbn_sunix_pci_2s] = {
	3716	+ .num_ports = 2,
	3717	+ .base_baud = 921600,
	3718	+ .uart_offset = 0x8,
	3719	+ },
	3720	+ [pbn_sunix_pci_4s] = {
	3721	+ .num_ports = 4,
	3722	+ .base_baud = 921600,
	3723	+ .uart_offset = 0x8,
	3724	+ },
	3725	+ [pbn_sunix_pci_8s] = {
	3726	+ .num_ports = 8,
	3727	+ .base_baud = 921600,
	3728	+ .uart_offset = 0x8,
	3729	+ },
	3730	+ [pbn_sunix_pci_16s] = {
	3731	+ .num_ports = 16,
	3732	+ .base_baud = 921600,
	3733	+ .uart_offset = 0x8,
	3734	+ },
	3735	+ [pbn_titan_1_4000000] = {
	3736	+ .flags = FL_BASE0,
	3737	+ .num_ports = 1,
	3738	+ .base_baud = 4000000,
	3739	+ .uart_offset = 0x200,
	3740	+ .first_offset = 0x1000,
	3741	+ },
	3742	+ [pbn_titan_2_4000000] = {
	3743	+ .flags = FL_BASE0,
	3744	+ .num_ports = 2,
	3745	+ .base_baud = 4000000,
	3746	+ .uart_offset = 0x200,
	3747	+ .first_offset = 0x1000,
	3748	+ },
	3749	+ [pbn_titan_4_4000000] = {
	3750	+ .flags = FL_BASE0,
	3751	+ .num_ports = 4,
	3752	+ .base_baud = 4000000,
	3753	+ .uart_offset = 0x200,
	3754	+ .first_offset = 0x1000,
	3755	+ },
	3756	+ [pbn_titan_8_4000000] = {
	3757	+ .flags = FL_BASE0,
	3758	+ .num_ports = 8,
	3759	+ .base_baud = 4000000,
	3760	+ .uart_offset = 0x200,
	3761	+ .first_offset = 0x1000,
	3762	+ },
	3763	+ [pbn_moxa8250_2p] = {
	3764	+ .flags = FL_BASE1,
	3765	+ .num_ports = 2,
	3766	+ .base_baud = 921600,
	3767	+ .uart_offset = 0x200,
	3768	+ },
	3769	+ [pbn_moxa8250_4p] = {
	3770	+ .flags = FL_BASE1,
	3771	+ .num_ports = 4,
	3772	+ .base_baud = 921600,
	3773	+ .uart_offset = 0x200,
	3774	+ },
	3775	+ [pbn_moxa8250_8p] = {
	3776	+ .flags = FL_BASE1,
	3777	+ .num_ports = 8,
	3778	+ .base_baud = 921600,
	3779	+ .uart_offset = 0x200,
	3780	+ },
3430	3781	};
3431	3782
3432	3783	static const struct pci_device_id blacklist[] = {
..	..	@@ -3439,20 +3790,6 @@
3439	3790	{ PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3440	3791	{ PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3441	3792	{ PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3442		-
3443		- /* Moxa Smartio MUE boards handled by 8250_moxa */
3444		- { PCI_VDEVICE(MOXA, 0x1024), },
3445		- { PCI_VDEVICE(MOXA, 0x1025), },
3446		- { PCI_VDEVICE(MOXA, 0x1045), },
3447		- { PCI_VDEVICE(MOXA, 0x1144), },
3448		- { PCI_VDEVICE(MOXA, 0x1160), },
3449		- { PCI_VDEVICE(MOXA, 0x1161), },
3450		- { PCI_VDEVICE(MOXA, 0x1182), },
3451		- { PCI_VDEVICE(MOXA, 0x1183), },
3452		- { PCI_VDEVICE(MOXA, 0x1322), },
3453		- { PCI_VDEVICE(MOXA, 0x1342), },
3454		- { PCI_VDEVICE(MOXA, 0x1381), },
3455		- { PCI_VDEVICE(MOXA, 0x1683), },
3456	3793
3457	3794	/* Intel platforms with MID UART */
3458	3795	{ PCI_VDEVICE(INTEL, 0x081b), },
..	..	@@ -3468,12 +3805,21 @@
3468	3805	{ PCI_VDEVICE(INTEL, 0x0f0c), },
3469	3806	{ PCI_VDEVICE(INTEL, 0x228a), },
3470	3807	{ PCI_VDEVICE(INTEL, 0x228c), },
	3808	+ { PCI_VDEVICE(INTEL, 0x4b96), },
	3809	+ { PCI_VDEVICE(INTEL, 0x4b97), },
	3810	+ { PCI_VDEVICE(INTEL, 0x4b98), },
	3811	+ { PCI_VDEVICE(INTEL, 0x4b99), },
	3812	+ { PCI_VDEVICE(INTEL, 0x4b9a), },
	3813	+ { PCI_VDEVICE(INTEL, 0x4b9b), },
3471	3814	{ PCI_VDEVICE(INTEL, 0x9ce3), },
3472	3815	{ PCI_VDEVICE(INTEL, 0x9ce4), },
3473	3816
3474	3817	/* Exar devices */
3475	3818	{ PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3476	3819	{ PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
	3820	+
	3821	+ /* End of the black list */
	3822	+ { }
3477	3823	};
3478	3824
3479	3825	static int serial_pci_is_class_communication(struct pci_dev *dev)
..	..	@@ -3487,25 +3833,6 @@
3487	3833	((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) \|\|
3488	3834	(dev->class & 0xff) > 6)
3489	3835	return -ENODEV;
3490		-
3491		- return 0;
3492		-}
3493		-
3494		-static int serial_pci_is_blacklisted(struct pci_dev *dev)
3495		-{
3496		- const struct pci_device_id *bldev;
3497		-
3498		- /*
3499		- * Do not access blacklisted devices that are known not to
3500		- * feature serial ports or are handled by other modules.
3501		- */
3502		- for (bldev = blacklist;
3503		- bldev < blacklist + ARRAY_SIZE(blacklist);
3504		- bldev++) {
3505		- if (dev->vendor == bldev->vendor &&
3506		- dev->device == bldev->device)
3507		- return -ENODEV;
3508		- }
3509	3836
3510	3837	return 0;
3511	3838	}
..	..	@@ -3532,7 +3859,7 @@
3532	3859	return -ENODEV;
3533	3860
3534	3861	num_iomem = num_port = 0;
3535		- for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
	3862	+ for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3536	3863	if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3537	3864	num_port++;
3538	3865	if (first_port == -1)
..	..	@@ -3560,7 +3887,7 @@
3560	3887	*/
3561	3888	first_port = -1;
3562	3889	num_port = 0;
3563		- for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
	3890	+ for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3564	3891	if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3565	3892	pci_resource_len(dev, i) == 8 &&
3566	3893	(first_port == -1 \|\| (first_port + num_port) == i)) {
..	..	@@ -3637,19 +3964,40 @@
3637	3964	memset(&uart, 0, sizeof(uart));
3638	3965	uart.port.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF \| UPF_SHARE_IRQ;
3639	3966	uart.port.uartclk = board->base_baud * 16;
3640		- uart.port.irq = get_pci_irq(dev, board);
	3967	+
	3968	+ if (board->flags & FL_NOIRQ) {
	3969	+ uart.port.irq = 0;
	3970	+ } else {
	3971	+ if (pci_match_id(pci_use_msi, dev)) {
	3972	+ pci_dbg(dev, "Using MSI(-X) interrupts\n");
	3973	+ pci_set_master(dev);
	3974	+ uart.port.flags &= ~UPF_SHARE_IRQ;
	3975	+ rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
	3976	+ } else {
	3977	+ pci_dbg(dev, "Using legacy interrupts\n");
	3978	+ rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
	3979	+ }
	3980	+ if (rc < 0) {
	3981	+ kfree(priv);
	3982	+ priv = ERR_PTR(rc);
	3983	+ goto err_deinit;
	3984	+ }
	3985	+
	3986	+ uart.port.irq = pci_irq_vector(dev, 0);
	3987	+ }
	3988	+
3641	3989	uart.port.dev = &dev->dev;
3642	3990
3643	3991	for (i = 0; i < nr_ports; i++) {
3644	3992	if (quirk->setup(priv, board, &uart, i))
3645	3993	break;
3646	3994
3647		- dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
	3995	+ pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3648	3996	uart.port.iobase, uart.port.irq, uart.port.iotype);
3649	3997
3650	3998	priv->line[i] = serial8250_register_8250_port(&uart);
3651	3999	if (priv->line[i] < 0) {
3652		- dev_err(&dev->dev,
	4000	+ pci_err(dev,
3653	4001	"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3654	4002	uart.port.iobase, uart.port.irq,
3655	4003	uart.port.iotype, priv->line[i]);
..	..	@@ -3733,6 +4081,7 @@
3733	4081	struct pci_serial_quirk *quirk;
3734	4082	struct serial_private *priv;
3735	4083	const struct pciserial_board *board;
	4084	+ const struct pci_device_id *exclude;
3736	4085	struct pciserial_board tmp;
3737	4086	int rc;
3738	4087
..	..	@@ -3744,16 +4093,15 @@
3744	4093	}
3745	4094
3746	4095	if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3747		- dev_err(&dev->dev, "invalid driver_data: %ld\n",
3748		- ent->driver_data);
	4096	+ pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
3749	4097	return -EINVAL;
3750	4098	}
3751	4099
3752	4100	board = &pci_boards[ent->driver_data];
3753	4101
3754		- rc = serial_pci_is_blacklisted(dev);
3755		- if (rc)
3756		- return rc;
	4102	+ exclude = pci_match_id(blacklist, dev);
	4103	+ if (exclude)
	4104	+ return -ENODEV;
3757	4105
3758	4106	rc = pcim_enable_device(dev);
3759	4107	pci_save_state(dev);
..	..	@@ -3807,8 +4155,7 @@
3807	4155	#ifdef CONFIG_PM_SLEEP
3808	4156	static int pciserial_suspend_one(struct device *dev)
3809	4157	{
3810		- struct pci_dev *pdev = to_pci_dev(dev);
3811		- struct serial_private *priv = pci_get_drvdata(pdev);
	4158	+ struct serial_private *priv = dev_get_drvdata(dev);
3812	4159
3813	4160	if (priv)
3814	4161	pciserial_suspend_ports(priv);
..	..	@@ -3829,7 +4176,7 @@
3829	4176	err = pci_enable_device(pdev);
3830	4177	/* FIXME: We cannot simply error out here */
3831	4178	if (err)
3832		- dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
	4179	+ pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
3833	4180	pciserial_resume_ports(priv);
3834	4181	}
3835	4182	return 0;
..	..	@@ -3840,6 +4187,9 @@
3840	4187	pciserial_resume_one);
3841	4188
3842	4189	static const struct pci_device_id serial_pci_tbl[] = {
	4190	+ { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
	4191	+ PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
	4192	+ pbn_b0_4_921600 },
3843	4193	/* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3844	4194	{ PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3845	4195	PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
..	..	@@ -4023,13 +4373,6 @@
4023	4373	0x10b5, 0x106a, 0, 0,
4024	4374	pbn_plx_romulus },
4025	4375	/*
4026		- * EndRun Technologies. PCI express device range.
4027		- * EndRun PTP/1588 has 2 Native UARTs.
4028		- */
4029		- { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4030		- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031		- pbn_endrun_2_4000000 },
4032		- /*
4033	4376	* Quatech cards. These actually have configurable clocks but for
4034	4377	* now we just use the default.
4035	4378	*
..	..	@@ -4138,158 +4481,165 @@
4138	4481	*/
4139	4482	{ PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4140	4483	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4141		- pbn_b0_1_4000000 },
	4484	+ pbn_b0_1_3906250 },
4142	4485	{ PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4143	4486	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144		- pbn_b0_1_4000000 },
	4487	+ pbn_b0_1_3906250 },
4145	4488	{ PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4146	4489	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4147		- pbn_oxsemi_1_4000000 },
	4490	+ pbn_oxsemi_1_3906250 },
4148	4491	{ PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4149	4492	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4150		- pbn_oxsemi_1_4000000 },
	4493	+ pbn_oxsemi_1_3906250 },
4151	4494	{ PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4152	4495	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4153		- pbn_b0_1_4000000 },
	4496	+ pbn_b0_1_3906250 },
4154	4497	{ PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4155	4498	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4156		- pbn_b0_1_4000000 },
	4499	+ pbn_b0_1_3906250 },
4157	4500	{ PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4158	4501	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4159		- pbn_oxsemi_1_4000000 },
	4502	+ pbn_oxsemi_1_3906250 },
4160	4503	{ PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4161	4504	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4162		- pbn_oxsemi_1_4000000 },
	4505	+ pbn_oxsemi_1_3906250 },
4163	4506	{ PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4164	4507	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4165		- pbn_b0_1_4000000 },
	4508	+ pbn_b0_1_3906250 },
4166	4509	{ PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4167	4510	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4168		- pbn_b0_1_4000000 },
	4511	+ pbn_b0_1_3906250 },
4169	4512	{ PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4170	4513	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4171		- pbn_b0_1_4000000 },
	4514	+ pbn_b0_1_3906250 },
4172	4515	{ PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4173	4516	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4174		- pbn_b0_1_4000000 },
	4517	+ pbn_b0_1_3906250 },
4175	4518	{ PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4176	4519	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177		- pbn_oxsemi_2_4000000 },
	4520	+ pbn_oxsemi_2_3906250 },
4178	4521	{ PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4179	4522	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180		- pbn_oxsemi_2_4000000 },
	4523	+ pbn_oxsemi_2_3906250 },
4181	4524	{ PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4182	4525	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183		- pbn_oxsemi_4_4000000 },
	4526	+ pbn_oxsemi_4_3906250 },
4184	4527	{ PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4185	4528	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186		- pbn_oxsemi_4_4000000 },
	4529	+ pbn_oxsemi_4_3906250 },
4187	4530	{ PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4188	4531	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189		- pbn_oxsemi_8_4000000 },
	4532	+ pbn_oxsemi_8_3906250 },
4190	4533	{ PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4191	4534	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192		- pbn_oxsemi_8_4000000 },
	4535	+ pbn_oxsemi_8_3906250 },
4193	4536	{ PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4194	4537	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195		- pbn_oxsemi_1_4000000 },
	4538	+ pbn_oxsemi_1_3906250 },
4196	4539	{ PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4197	4540	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198		- pbn_oxsemi_1_4000000 },
	4541	+ pbn_oxsemi_1_3906250 },
4199	4542	{ PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4200	4543	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201		- pbn_oxsemi_1_4000000 },
	4544	+ pbn_oxsemi_1_3906250 },
4202	4545	{ PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4203	4546	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204		- pbn_oxsemi_1_4000000 },
	4547	+ pbn_oxsemi_1_3906250 },
4205	4548	{ PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4206	4549	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207		- pbn_oxsemi_1_4000000 },
	4550	+ pbn_oxsemi_1_3906250 },
4208	4551	{ PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4209	4552	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210		- pbn_oxsemi_1_4000000 },
	4553	+ pbn_oxsemi_1_3906250 },
4211	4554	{ PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4212	4555	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213		- pbn_oxsemi_1_4000000 },
	4556	+ pbn_oxsemi_1_3906250 },
4214	4557	{ PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4215	4558	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216		- pbn_oxsemi_1_4000000 },
	4559	+ pbn_oxsemi_1_3906250 },
4217	4560	{ PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4218	4561	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219		- pbn_oxsemi_1_4000000 },
	4562	+ pbn_oxsemi_1_3906250 },
4220	4563	{ PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4221	4564	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222		- pbn_oxsemi_1_4000000 },
	4565	+ pbn_oxsemi_1_3906250 },
4223	4566	{ PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4224	4567	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225		- pbn_oxsemi_1_4000000 },
	4568	+ pbn_oxsemi_1_3906250 },
4226	4569	{ PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4227	4570	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228		- pbn_oxsemi_1_4000000 },
	4571	+ pbn_oxsemi_1_3906250 },
4229	4572	{ PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4230	4573	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231		- pbn_oxsemi_1_4000000 },
	4574	+ pbn_oxsemi_1_3906250 },
4232	4575	{ PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4233	4576	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234		- pbn_oxsemi_1_4000000 },
	4577	+ pbn_oxsemi_1_3906250 },
4235	4578	{ PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4236	4579	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237		- pbn_oxsemi_1_4000000 },
	4580	+ pbn_oxsemi_1_3906250 },
4238	4581	{ PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4239	4582	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240		- pbn_oxsemi_1_4000000 },
	4583	+ pbn_oxsemi_1_3906250 },
4241	4584	{ PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4242	4585	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243		- pbn_oxsemi_1_4000000 },
	4586	+ pbn_oxsemi_1_3906250 },
4244	4587	{ PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4245	4588	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246		- pbn_oxsemi_1_4000000 },
	4589	+ pbn_oxsemi_1_3906250 },
4247	4590	{ PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4248	4591	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249		- pbn_oxsemi_1_4000000 },
	4592	+ pbn_oxsemi_1_3906250 },
4250	4593	{ PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4251	4594	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252		- pbn_oxsemi_1_4000000 },
	4595	+ pbn_oxsemi_1_3906250 },
4253	4596	{ PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4254	4597	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255		- pbn_oxsemi_1_4000000 },
	4598	+ pbn_oxsemi_1_3906250 },
4256	4599	{ PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4257	4600	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258		- pbn_oxsemi_1_4000000 },
	4601	+ pbn_oxsemi_1_3906250 },
4259	4602	{ PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4260	4603	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261		- pbn_oxsemi_1_4000000 },
	4604	+ pbn_oxsemi_1_3906250 },
4262	4605	{ PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4263	4606	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264		- pbn_oxsemi_1_4000000 },
	4607	+ pbn_oxsemi_1_3906250 },
4265	4608	{ PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4266	4609	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267		- pbn_oxsemi_1_4000000 },
	4610	+ pbn_oxsemi_1_3906250 },
4268	4611	{ PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4269	4612	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270		- pbn_oxsemi_1_4000000 },
	4613	+ pbn_oxsemi_1_3906250 },
4271	4614	/*
4272	4615	* Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4273	4616	*/
4274	4617	{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4275	4618	PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4276		- pbn_oxsemi_1_4000000 },
	4619	+ pbn_oxsemi_1_3906250 },
4277	4620	{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4278	4621	PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4279		- pbn_oxsemi_2_4000000 },
	4622	+ pbn_oxsemi_2_3906250 },
4280	4623	{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4281	4624	PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4282		- pbn_oxsemi_4_4000000 },
	4625	+ pbn_oxsemi_4_3906250 },
4283	4626	{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4284	4627	PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4285		- pbn_oxsemi_8_4000000 },
	4628	+ pbn_oxsemi_8_3906250 },
4286	4629
4287	4630	/*
4288	4631	* Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4289	4632	*/
4290	4633	{ PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4291	4634	PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4292		- pbn_oxsemi_2_4000000 },
	4635	+ pbn_oxsemi_2_3906250 },
	4636	+ /*
	4637	+ * EndRun Technologies. PCI express device range.
	4638	+ * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
	4639	+ */
	4640	+ { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
	4641	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	4642	+ pbn_oxsemi_2_3906250 },
4293	4643
4294	4644	/*
4295	4645	* SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
..	..	@@ -4363,22 +4713,22 @@
4363	4713	pbn_b0_4_921600 },
4364	4714	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4365	4715	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366		- pbn_oxsemi_1_4000000 },
	4716	+ pbn_titan_1_4000000 },
4367	4717	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4368	4718	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369		- pbn_oxsemi_2_4000000 },
	4719	+ pbn_titan_2_4000000 },
4370	4720	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4371	4721	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372		- pbn_oxsemi_4_4000000 },
	4722	+ pbn_titan_4_4000000 },
4373	4723	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4374	4724	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375		- pbn_oxsemi_8_4000000 },
	4725	+ pbn_titan_8_4000000 },
4376	4726	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4377	4727	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378		- pbn_oxsemi_2_4000000 },
	4728	+ pbn_titan_2_4000000 },
4379	4729	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4380	4730	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381		- pbn_oxsemi_2_4000000 },
	4731	+ pbn_titan_2_4000000 },
4382	4732	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4383	4733	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384	4734	pbn_b0_bt_2_921600 },
..	..	@@ -4480,17 +4830,29 @@
4480	4830	pbn_b0_bt_1_921600 },
4481	4831
4482	4832	/*
4483		- * SUNIX (TIMEDIA)
	4833	+ * Sunix PCI serial boards
4484	4834	*/
4485	4835	{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4486		- PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4487		- PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4488		- pbn_b0_bt_1_921600 },
4489		-
	4836	+ PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
	4837	+ pbn_sunix_pci_1s },
4490	4838	{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4491		- PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4492		- PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4493		- pbn_b0_bt_1_921600 },
	4839	+ PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
	4840	+ pbn_sunix_pci_2s },
	4841	+ { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
	4842	+ PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
	4843	+ pbn_sunix_pci_4s },
	4844	+ { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
	4845	+ PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
	4846	+ pbn_sunix_pci_4s },
	4847	+ { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
	4848	+ PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
	4849	+ pbn_sunix_pci_8s },
	4850	+ { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
	4851	+ PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
	4852	+ pbn_sunix_pci_8s },
	4853	+ { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
	4854	+ PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
	4855	+ pbn_sunix_pci_16s },
4494	4856
4495	4857	/*
4496	4858	* AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
..	..	@@ -4640,6 +5002,10 @@
4640	5002	{ PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4641	5003	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642	5004	pbn_b2_1_115200 },
	5005	+ /* HPE PCI serial device */
	5006	+ { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
	5007	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5008	+ pbn_b1_1_115200 },
4643	5009
4644	5010	{ PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4645	5011	PCI_ANY_ID, PCI_ANY_ID, 0, 0,
..	..	@@ -5110,6 +5476,46 @@
5110	5476	pbn_ni8430_4 },
5111	5477
5112	5478	/*
	5479	+ * MOXA
	5480	+ */
	5481	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
	5482	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5483	+ pbn_moxa8250_2p },
	5484	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
	5485	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5486	+ pbn_moxa8250_2p },
	5487	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
	5488	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5489	+ pbn_moxa8250_4p },
	5490	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
	5491	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5492	+ pbn_moxa8250_4p },
	5493	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
	5494	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5495	+ pbn_moxa8250_8p },
	5496	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
	5497	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5498	+ pbn_moxa8250_8p },
	5499	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
	5500	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5501	+ pbn_moxa8250_8p },
	5502	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
	5503	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5504	+ pbn_moxa8250_8p },
	5505	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
	5506	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5507	+ pbn_moxa8250_2p },
	5508	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
	5509	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5510	+ pbn_moxa8250_4p },
	5511	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
	5512	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5513	+ pbn_moxa8250_8p },
	5514	+ { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
	5515	+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	5516	+ pbn_moxa8250_8p },
	5517	+
	5518	+ /*
5113	5519	* ADDI-DATA GmbH communication cards <info@addi-data.com>
5114	5520	*/
5115	5521	{ PCI_VENDOR_ID_ADDIDATA,
..	..	@@ -5332,6 +5738,9 @@
5332	5738	PCI_ANY_ID, PCI_ANY_ID,
5333	5739	0, 0, pbn_wch384_4 },
5334	5740
	5741	+ { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
	5742	+ PCI_ANY_ID, PCI_ANY_ID,
	5743	+ 0, 0, pbn_wch384_8 },
5335	5744	/*
5336	5745	* Realtek RealManage
5337	5746	*/
..	..	@@ -5347,6 +5756,9 @@
5347	5756	{ PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5348	5757	{ PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5349	5758	{ PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
	5759	+ { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
	5760	+ { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
	5761	+ { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5350	5762
5351	5763	/* MKS Tenta SCOM-080x serial cards */
5352	5764	{ PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },