~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8	*
9	9	*/
10	10
	11	+#include <linux/clk.h>
11	12	#include <linux/device.h>
12	13	#include <linux/io.h>
13	14	#include <linux/module.h>
..	..	@@ -26,6 +27,7 @@
26	27	#include <linux/pm_qos.h>
27	28	#include <linux/pm_wakeirq.h>
28	29	#include <linux/dma-mapping.h>
	30	+#include <linux/sys_soc.h>
29	31
30	32	#include "8250.h"
31	33
..	..	@@ -39,6 +41,9 @@
39	41	* The same errata is applicable to AM335x and DRA7x processors too.
40	42	*/
41	43	#define UART_ERRATA_CLOCK_DISABLE (1 << 3)
	44	+#define UART_HAS_EFR2 BIT(4)
	45	+#define UART_HAS_RHR_IT_DIS BIT(5)
	46	+#define UART_RX_TIMEOUT_QUIRK BIT(6)
42	47
43	48	#define OMAP_UART_FCR_RX_TRIG 6
44	49	#define OMAP_UART_FCR_TX_TRIG 4
..	..	@@ -92,6 +97,17 @@
92	97	#define OMAP_UART_REV_52 0x0502
93	98	#define OMAP_UART_REV_63 0x0603
94	99
	100	+/* Interrupt Enable Register 2 */
	101	+#define UART_OMAP_IER2 0x1B
	102	+#define UART_OMAP_IER2_RHR_IT_DIS BIT(2)
	103	+
	104	+/* Enhanced features register 2 */
	105	+#define UART_OMAP_EFR2 0x23
	106	+#define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
	107	+
	108	+/* RX FIFO occupancy indicator */
	109	+#define UART_OMAP_RX_LVL 0x19
	110	+
95	111	struct omap8250_priv {
96	112	int line;
97	113	u8 habit;
..	..	@@ -104,6 +120,8 @@
104	120	u8 delayed_restore;
105	121	u16 quot;
106	122
	123	+ u8 tx_trigger;
	124	+ u8 rx_trigger;
107	125	bool is_suspending;
108	126	int wakeirq;
109	127	int wakeups_enabled;
..	..	@@ -117,6 +135,17 @@
117	135	bool throttled;
118	136	};
119	137
	138	+struct omap8250_dma_params {
	139	+ u32 rx_size;
	140	+ u8 rx_trigger;
	141	+ u8 tx_trigger;
	142	+};
	143	+
	144	+struct omap8250_platdata {
	145	+ struct omap8250_dma_params *dma_params;
	146	+ u8 habit;
	147	+};
	148	+
120	149	#ifdef CONFIG_SERIAL_8250_DMA
121	150	static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
122	151	#else
..	..	@@ -128,7 +157,11 @@
128	157	return readl(up->port.membase + (reg << up->port.regshift));
129	158	}
130	159
131		-static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
	160	+/*
	161	+ * Called on runtime PM resume path from omap8250_restore_regs(), and
	162	+ * omap8250_set_mctrl().
	163	+ */
	164	+static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
132	165	{
133	166	struct uart_8250_port *up = up_to_u8250p(port);
134	167	struct omap8250_priv *priv = up->port.private_data;
..	..	@@ -136,18 +169,34 @@
136	169
137	170	serial8250_do_set_mctrl(port, mctrl);
138	171
139		- /*
140		- * Turn off autoRTS if RTS is lowered and restore autoRTS setting
141		- * if RTS is raised
142		- */
143		- lcr = serial_in(up, UART_LCR);
144		- serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
145		- if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
146		- priv->efr \|= UART_EFR_RTS;
147		- else
148		- priv->efr &= ~UART_EFR_RTS;
149		- serial_out(up, UART_EFR, priv->efr);
150		- serial_out(up, UART_LCR, lcr);
	172	+ if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
	173	+ /*
	174	+ * Turn off autoRTS if RTS is lowered and restore autoRTS
	175	+ * setting if RTS is raised
	176	+ */
	177	+ lcr = serial_in(up, UART_LCR);
	178	+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
	179	+ if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
	180	+ priv->efr \|= UART_EFR_RTS;
	181	+ else
	182	+ priv->efr &= ~UART_EFR_RTS;
	183	+ serial_out(up, UART_EFR, priv->efr);
	184	+ serial_out(up, UART_LCR, lcr);
	185	+ }
	186	+}
	187	+
	188	+static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
	189	+{
	190	+ int err;
	191	+
	192	+ err = pm_runtime_resume_and_get(port->dev);
	193	+ if (err)
	194	+ return;
	195	+
	196	+ __omap8250_set_mctrl(port, mctrl);
	197	+
	198	+ pm_runtime_mark_last_busy(port->dev);
	199	+ pm_runtime_put_autosuspend(port->dev);
151	200	}
152	201
153	202	/*
..	..	@@ -162,27 +211,10 @@
162	211	static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
163	212	struct omap8250_priv *priv)
164	213	{
165		- u8 timeout = 255;
166		-
167	214	serial_out(up, UART_OMAP_MDR1, priv->mdr1);
168	215	udelay(2);
169	216	serial_out(up, UART_FCR, up->fcr \| UART_FCR_CLEAR_XMIT \|
170	217	UART_FCR_CLEAR_RCVR);
171		- /*
172		- * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
173		- * TX_FIFO_E bit is 1.
174		- */
175		- while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
176		- (UART_LSR_THRE \| UART_LSR_DR))) {
177		- timeout--;
178		- if (!timeout) {
179		- /* Should never happen. we warn and carry on */
180		- dev_crit(up->port.dev, "Errata i202: timedout %x\n",
181		- serial_in(up, UART_LSR));
182		- break;
183		- }
184		- udelay(1);
185		- }
186	218	}
187	219
188	220	static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
..	..	@@ -261,6 +293,7 @@
261	293	{
262	294	struct omap8250_priv *priv = up->port.private_data;
263	295	struct uart_8250_dma *dma = up->dma;
	296	+ u8 mcr = serial8250_in_MCR(up);
264	297
265	298	if (dma && dma->tx_running) {
266	299	/*
..	..	@@ -277,7 +310,7 @@
277	310	serial_out(up, UART_EFR, UART_EFR_ECB);
278	311
279	312	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
280		- serial8250_out_MCR(up, UART_MCR_TCRTLR);
	313	+ serial8250_out_MCR(up, mcr \| UART_MCR_TCRTLR);
281	314	serial_out(up, UART_FCR, up->fcr);
282	315
283	316	omap8250_update_scr(up, priv);
..	..	@@ -287,13 +320,14 @@
287	320	serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) \|
288	321	OMAP_UART_TCR_HALT(52));
289	322	serial_out(up, UART_TI752_TLR,
290		- TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX \|
291		- TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
	323	+ TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX \|
	324	+ TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
292	325
293	326	serial_out(up, UART_LCR, 0);
294	327
295	328	/* drop TCR + TLR access, we setup XON/XOFF later */
296		- serial8250_out_MCR(up, up->mcr);
	329	+ serial8250_out_MCR(up, mcr);
	330	+
297	331	serial_out(up, UART_IER, up->ier);
298	332
299	333	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
..	..	@@ -310,7 +344,10 @@
310	344
311	345	omap8250_update_mdr1(up, priv);
312	346
313		- up->port.ops->set_mctrl(&up->port, up->port.mctrl);
	347	+ __omap8250_set_mctrl(&up->port, up->port.mctrl);
	348	+
	349	+ if (up->port.rs485.flags & SER_RS485_ENABLED)
	350	+ serial8250_em485_stop_tx(up);
314	351	}
315	352
316	353	/*
..	..	@@ -427,8 +464,8 @@
427	464	* This is because threshold and trigger values are the same.
428	465	*/
429	466	up->fcr = UART_FCR_ENABLE_FIFO;
430		- up->fcr \|= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
431		- up->fcr \|= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
	467	+ up->fcr \|= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
	468	+ up->fcr \|= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
432	469
433	470	priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK \| OMAP_UART_SCR_TX_EMPTY \|
434	471	OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
..	..	@@ -443,7 +480,9 @@
443	480	priv->efr = 0;
444	481	up->port.status &= ~(UPSTAT_AUTOCTS \| UPSTAT_AUTORTS \| UPSTAT_AUTOXOFF);
445	482
446		- if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
	483	+ if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
	484	+ !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
	485	+ !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
447	486	/* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
448	487	up->port.status \|= UPSTAT_AUTOCTS \| UPSTAT_AUTORTS;
449	488	priv->efr \|= UART_EFR_CTS;
..	..	@@ -505,6 +544,11 @@
505	544	static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
506	545	struct omap8250_priv *priv)
507	546	{
	547	+ const struct soc_device_attribute k3_soc_devices[] = {
	548	+ { .family = "AM65X", },
	549	+ { .family = "J721E", .revision = "SR1.0" },
	550	+ { /* sentinel */ }
	551	+ };
508	552	u32 mvr, scheme;
509	553	u16 revision, major, minor;
510	554
..	..	@@ -552,6 +596,14 @@
552	596	default:
553	597	break;
554	598	}
	599	+
	600	+ /*
	601	+ * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
	602	+ * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
	603	+ * to enable errata workaround.
	604	+ */
	605	+ if (soc_device_match(k3_soc_devices))
	606	+ priv->habit &= ~UART_HAS_RHR_IT_DIS;
555	607	}
556	608
557	609	static void omap8250_uart_qos_work(struct work_struct *work)
..	..	@@ -559,7 +611,7 @@
559	611	struct omap8250_priv *priv;
560	612
561	613	priv = container_of(work, struct omap8250_priv, qos_work);
562		- pm_qos_update_request(&priv->pm_qos_request, priv->latency);
	614	+ cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
563	615	}
564	616
565	617	#ifdef CONFIG_SERIAL_8250_DMA
..	..	@@ -569,8 +621,9 @@
569	621	static irqreturn_t omap8250_irq(int irq, void *dev_id)
570	622	{
571	623	struct uart_port *port = dev_id;
	624	+ struct omap8250_priv *priv = port->private_data;
572	625	struct uart_8250_port *up = up_to_u8250p(port);
573		- unsigned int iir;
	626	+ unsigned int iir, lsr;
574	627	int ret;
575	628
576	629	#ifdef CONFIG_SERIAL_8250_DMA
..	..	@@ -581,8 +634,42 @@
581	634	#endif
582	635
583	636	serial8250_rpm_get(up);
	637	+ lsr = serial_port_in(port, UART_LSR);
584	638	iir = serial_port_in(port, UART_IIR);
585	639	ret = serial8250_handle_irq(port, iir);
	640	+
	641	+ /*
	642	+ * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
	643	+ * FIFO has been drained, in which case a dummy read of RX FIFO
	644	+ * is required to clear RX TIMEOUT condition.
	645	+ */
	646	+ if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
	647	+ (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
	648	+ serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
	649	+ serial_port_in(port, UART_RX);
	650	+ }
	651	+
	652	+ /* Stop processing interrupts on input overrun */
	653	+ if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
	654	+ unsigned long delay;
	655	+
	656	+ /* Synchronize UART_IER access against the console. */
	657	+ spin_lock(&port->lock);
	658	+ up->ier = port->serial_in(port, UART_IER);
	659	+ if (up->ier & (UART_IER_RLSI \| UART_IER_RDI)) {
	660	+ port->ops->stop_rx(port);
	661	+ } else {
	662	+ /* Keep restarting the timer until
	663	+ * the input overrun subsides.
	664	+ */
	665	+ cancel_delayed_work(&up->overrun_backoff);
	666	+ }
	667	+ spin_unlock(&port->lock);
	668	+
	669	+ delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
	670	+ schedule_delayed_work(&up->overrun_backoff, delay);
	671	+ }
	672	+
586	673	serial8250_rpm_put(up);
587	674
588	675	return IRQ_RETVAL(ret);
..	..	@@ -602,7 +689,6 @@
602	689
603	690	pm_runtime_get_sync(port->dev);
604	691
605		- up->mcr = 0;
606	692	serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
607	693
608	694	serial_out(up, UART_LCR, UART_LCR_WLEN8);
..	..	@@ -641,7 +727,7 @@
641	727	priv->wer \|= OMAP_UART_TX_WAKEUP_EN;
642	728	serial_out(up, UART_OMAP_WER, priv->wer);
643	729
644		- if (up->dma)
	730	+ if (up->dma && !(priv->habit & UART_HAS_EFR2))
645	731	up->dma->rx_dma(up);
646	732
647	733	pm_runtime_mark_last_busy(port->dev);
..	..	@@ -666,6 +752,8 @@
666	752	pm_runtime_get_sync(port->dev);
667	753
668	754	serial_out(up, UART_OMAP_WER, 0);
	755	+ if (priv->habit & UART_HAS_EFR2)
	756	+ serial_out(up, UART_OMAP_EFR2, 0x0);
669	757
670	758	up->ier = 0;
671	759	serial_out(up, UART_IER, 0);
..	..	@@ -689,49 +777,17 @@
689	777	static void omap_8250_throttle(struct uart_port *port)
690	778	{
691	779	struct omap8250_priv *priv = port->private_data;
692		- struct uart_8250_port *up = up_to_u8250p(port);
693	780	unsigned long flags;
694	781
695	782	pm_runtime_get_sync(port->dev);
696	783
697	784	spin_lock_irqsave(&port->lock, flags);
698		- up->ier &= ~(UART_IER_RLSI \| UART_IER_RDI);
699		- serial_out(up, UART_IER, up->ier);
	785	+ port->ops->stop_rx(port);
700	786	priv->throttled = true;
701	787	spin_unlock_irqrestore(&port->lock, flags);
702	788
703	789	pm_runtime_mark_last_busy(port->dev);
704	790	pm_runtime_put_autosuspend(port->dev);
705		-}
706		-
707		-static int omap_8250_rs485_config(struct uart_port *port,
708		- struct serial_rs485 *rs485)
709		-{
710		- struct uart_8250_port *up = up_to_u8250p(port);
711		-
712		- /* Clamp the delays to [0, 100ms] */
713		- rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
714		- rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
715		-
716		- port->rs485 = *rs485;
717		-
718		- /*
719		- * Both serial8250_em485_init and serial8250_em485_destroy
720		- * are idempotent
721		- */
722		- if (rs485->flags & SER_RS485_ENABLED) {
723		- int ret = serial8250_em485_init(up);
724		-
725		- if (ret) {
726		- rs485->flags &= ~SER_RS485_ENABLED;
727		- port->rs485.flags &= ~SER_RS485_ENABLED;
728		- }
729		- return ret;
730		- }
731		-
732		- serial8250_em485_destroy(up);
733		-
734		- return 0;
735	791	}
736	792
737	793	static void omap_8250_unthrottle(struct uart_port *port)
..	..	@@ -747,6 +803,7 @@
747	803	if (up->dma)
748	804	up->dma->rx_dma(up);
749	805	up->ier \|= UART_IER_RLSI \| UART_IER_RDI;
	806	+ port->read_status_mask \|= UART_LSR_DR;
750	807	serial_out(up, UART_IER, up->ier);
751	808	spin_unlock_irqrestore(&port->lock, flags);
752	809
..	..	@@ -757,35 +814,60 @@
757	814	#ifdef CONFIG_SERIAL_8250_DMA
758	815	static int omap_8250_rx_dma(struct uart_8250_port *p);
759	816
	817	+/* Must be called while priv->rx_dma_lock is held */
760	818	static void __dma_rx_do_complete(struct uart_8250_port *p)
761	819	{
762		- struct omap8250_priv *priv = p->port.private_data;
763	820	struct uart_8250_dma *dma = p->dma;
764	821	struct tty_port *tty_port = &p->port.state->port;
	822	+ struct omap8250_priv *priv = p->port.private_data;
	823	+ struct dma_chan *rxchan = dma->rxchan;
	824	+ dma_cookie_t cookie;
765	825	struct dma_tx_state state;
766	826	int count;
767		- unsigned long flags;
768	827	int ret;
769		-
770		- spin_lock_irqsave(&priv->rx_dma_lock, flags);
	828	+ u32 reg;
771	829
772	830	if (!dma->rx_running)
773		- goto unlock;
	831	+ goto out;
774	832
	833	+ cookie = dma->rx_cookie;
775	834	dma->rx_running = 0;
776		- dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
777	835
778		- count = dma->rx_size - state.residue;
779		- if (count < dma->rx_size)
780		- dmaengine_terminate_async(dma->rxchan);
	836	+ /* Re-enable RX FIFO interrupt now that transfer is complete */
	837	+ if (priv->habit & UART_HAS_RHR_IT_DIS) {
	838	+ reg = serial_in(p, UART_OMAP_IER2);
	839	+ reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
	840	+ serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
	841	+ }
	842	+
	843	+ dmaengine_tx_status(rxchan, cookie, &state);
	844	+
	845	+ count = dma->rx_size - state.residue + state.in_flight_bytes;
	846	+ if (count < dma->rx_size) {
	847	+ dmaengine_terminate_async(rxchan);
	848	+
	849	+ /*
	850	+ * Poll for teardown to complete which guarantees in
	851	+ * flight data is drained.
	852	+ */
	853	+ if (state.in_flight_bytes) {
	854	+ int poll_count = 25;
	855	+
	856	+ while (dmaengine_tx_status(rxchan, cookie, NULL) &&
	857	+ poll_count--)
	858	+ cpu_relax();
	859	+
	860	+ if (poll_count == -1)
	861	+ dev_err(p->port.dev, "teardown incomplete\n");
	862	+ }
	863	+ }
781	864	if (!count)
782		- goto unlock;
	865	+ goto out;
783	866	ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
784	867
785	868	p->port.icount.rx += ret;
786	869	p->port.icount.buf_overrun += count - ret;
787		-unlock:
788		- spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
	870	+out:
789	871
790	872	tty_flip_buffer_push(tty_port);
791	873	}
..	..	@@ -811,8 +893,12 @@
811	893	return;
812	894	}
813	895	__dma_rx_do_complete(p);
814		- if (!priv->throttled)
815		- omap_8250_rx_dma(p);
	896	+ if (!priv->throttled) {
	897	+ p->ier \|= UART_IER_RLSI \| UART_IER_RDI;
	898	+ serial_out(p, UART_IER, p->ier);
	899	+ if (!(priv->habit & UART_HAS_EFR2))
	900	+ omap_8250_rx_dma(p);
	901	+ }
816	902
817	903	spin_unlock_irqrestore(&p->port.lock, flags);
818	904	}
..	..	@@ -838,9 +924,8 @@
838	924	if (WARN_ON_ONCE(ret))
839	925	priv->rx_dma_broken = true;
840	926	}
841		- spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
842		-
843	927	__dma_rx_do_complete(p);
	928	+ spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
844	929	}
845	930
846	931	static int omap_8250_rx_dma(struct uart_8250_port *p)
..	..	@@ -850,14 +935,27 @@
850	935	int err = 0;
851	936	struct dma_async_tx_descriptor *desc;
852	937	unsigned long flags;
	938	+ u32 reg;
853	939
854	940	if (priv->rx_dma_broken)
855	941	return -EINVAL;
856	942
857	943	spin_lock_irqsave(&priv->rx_dma_lock, flags);
858	944
859		- if (dma->rx_running)
	945	+ if (dma->rx_running) {
	946	+ enum dma_status state;
	947	+
	948	+ state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
	949	+ if (state == DMA_COMPLETE) {
	950	+ /*
	951	+ * Disable RX interrupts to allow RX DMA completion
	952	+ * callback to run.
	953	+ */
	954	+ p->ier &= ~(UART_IER_RLSI \| UART_IER_RDI);
	955	+ serial_out(p, UART_IER, p->ier);
	956	+ }
860	957	goto out;
	958	+ }
861	959
862	960	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
863	961	dma->rx_size, DMA_DEV_TO_MEM,
..	..	@@ -872,6 +970,17 @@
872	970	desc->callback_param = p;
873	971
874	972	dma->rx_cookie = dmaengine_submit(desc);
	973	+
	974	+ /*
	975	+ * Disable RX FIFO interrupt while RX DMA is enabled, else
	976	+ * spurious interrupt may be raised when data is in the RX FIFO
	977	+ * but is yet to be drained by DMA.
	978	+ */
	979	+ if (priv->habit & UART_HAS_RHR_IT_DIS) {
	980	+ reg = serial_in(p, UART_OMAP_IER2);
	981	+ reg \|= UART_OMAP_IER2_RHR_IT_DIS;
	982	+ serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
	983	+ }
875	984
876	985	dma_async_issue_pending(dma->rxchan);
877	986	out:
..	..	@@ -915,15 +1024,13 @@
915	1024	ret = omap_8250_tx_dma(p);
916	1025	if (ret)
917	1026	en_thri = true;
918		-
919	1027	} else if (p->capabilities & UART_CAP_RPM) {
920	1028	en_thri = true;
921	1029	}
922	1030
923	1031	if (en_thri) {
924	1032	dma->tx_err = 1;
925		- p->ier \|= UART_IER_THRI;
926		- serial_port_out(&p->port, UART_IER, p->ier);
	1033	+ serial8250_set_THRI(p);
927	1034	}
928	1035
929	1036	spin_unlock_irqrestore(&p->port.lock, flags);
..	..	@@ -951,10 +1058,7 @@
951	1058	ret = -EBUSY;
952	1059	goto err;
953	1060	}
954		- if (p->ier & UART_IER_THRI) {
955		- p->ier &= ~UART_IER_THRI;
956		- serial_out(p, UART_IER, p->ier);
957		- }
	1061	+ serial8250_clear_THRI(p);
958	1062	return 0;
959	1063	}
960	1064
..	..	@@ -1012,10 +1116,7 @@
1012	1116	if (dma->tx_err)
1013	1117	dma->tx_err = 0;
1014	1118
1015		- if (p->ier & UART_IER_THRI) {
1016		- p->ier &= ~UART_IER_THRI;
1017		- serial_out(p, UART_IER, p->ier);
1018		- }
	1119	+ serial8250_clear_THRI(p);
1019	1120	if (skip_byte)
1020	1121	serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1021	1122	return 0;
..	..	@@ -1036,6 +1137,46 @@
1036	1137	return omap_8250_rx_dma(up);
1037	1138	}
1038	1139
	1140	+static unsigned char omap_8250_handle_rx_dma(struct uart_8250_port *up,
	1141	+ u8 iir, unsigned char status)
	1142	+{
	1143	+ if ((status & (UART_LSR_DR \| UART_LSR_BI)) &&
	1144	+ (iir & UART_IIR_RDI)) {
	1145	+ if (handle_rx_dma(up, iir)) {
	1146	+ status = serial8250_rx_chars(up, status);
	1147	+ omap_8250_rx_dma(up);
	1148	+ }
	1149	+ }
	1150	+
	1151	+ return status;
	1152	+}
	1153	+
	1154	+static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
	1155	+ unsigned char status)
	1156	+{
	1157	+ /*
	1158	+ * Queue a new transfer if FIFO has data.
	1159	+ */
	1160	+ if ((status & (UART_LSR_DR \| UART_LSR_BI)) &&
	1161	+ (up->ier & UART_IER_RDI)) {
	1162	+ omap_8250_rx_dma(up);
	1163	+ serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
	1164	+ } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
	1165	+ /*
	1166	+ * Disable RX timeout, read IIR to clear
	1167	+ * current timeout condition, clear EFR2 to
	1168	+ * periodic timeouts, re-enable interrupts.
	1169	+ */
	1170	+ up->ier &= ~(UART_IER_RLSI \| UART_IER_RDI);
	1171	+ serial_out(up, UART_IER, up->ier);
	1172	+ omap_8250_rx_dma_flush(up);
	1173	+ serial_in(up, UART_IIR);
	1174	+ serial_out(up, UART_OMAP_EFR2, 0x0);
	1175	+ up->ier \|= UART_IER_RLSI \| UART_IER_RDI;
	1176	+ serial_out(up, UART_IER, up->ier);
	1177	+ }
	1178	+}
	1179	+
1039	1180	/*
1040	1181	* This is mostly serial8250_handle_irq(). We have a slightly different DMA
1041	1182	* hoook for RX/TX and need different logic for them in the ISR. Therefore we
..	..	@@ -1044,6 +1185,7 @@
1044	1185	static int omap_8250_dma_handle_irq(struct uart_port *port)
1045	1186	{
1046	1187	struct uart_8250_port *up = up_to_u8250p(port);
	1188	+ struct omap8250_priv *priv = up->port.private_data;
1047	1189	unsigned char status;
1048	1190	unsigned long flags;
1049	1191	u8 iir;
..	..	@@ -1053,19 +1195,18 @@
1053	1195	iir = serial_port_in(port, UART_IIR);
1054	1196	if (iir & UART_IIR_NO_INT) {
1055	1197	serial8250_rpm_put(up);
1056		- return 0;
	1198	+ return IRQ_HANDLED;
1057	1199	}
1058	1200
1059	1201	spin_lock_irqsave(&port->lock, flags);
1060	1202
1061	1203	status = serial_port_in(port, UART_LSR);
1062	1204
1063		- if (status & (UART_LSR_DR \| UART_LSR_BI)) {
1064		- if (handle_rx_dma(up, iir)) {
1065		- status = serial8250_rx_chars(up, status);
1066		- omap_8250_rx_dma(up);
1067		- }
1068		- }
	1205	+ if (priv->habit & UART_HAS_EFR2)
	1206	+ am654_8250_handle_rx_dma(up, iir, status);
	1207	+ else
	1208	+ status = omap_8250_handle_rx_dma(up, iir, status);
	1209	+
1069	1210	serial8250_modem_status(up);
1070	1211	if (status & UART_LSR_THRE && up->dma->tx_err) {
1071	1212	if (uart_tx_stopped(&up->port) \|\|
..	..	@@ -1082,7 +1223,7 @@
1082	1223	}
1083	1224	}
1084	1225
1085		- spin_unlock_irqrestore(&port->lock, flags);
	1226	+ uart_unlock_and_check_sysrq(port, flags);
1086	1227	serial8250_rpm_put(up);
1087	1228	return 1;
1088	1229	}
..	..	@@ -1107,33 +1248,63 @@
1107	1248	return 0;
1108	1249	}
1109	1250
1110		-static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1111		-static const u8 am3352_habit = OMAP_DMA_TX_KICK \| UART_ERRATA_CLOCK_DISABLE;
1112		-static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
	1251	+static struct omap8250_dma_params am654_dma = {
	1252	+ .rx_size = SZ_2K,
	1253	+ .rx_trigger = 1,
	1254	+ .tx_trigger = TX_TRIGGER,
	1255	+};
	1256	+
	1257	+static struct omap8250_dma_params am33xx_dma = {
	1258	+ .rx_size = RX_TRIGGER,
	1259	+ .rx_trigger = RX_TRIGGER,
	1260	+ .tx_trigger = TX_TRIGGER,
	1261	+};
	1262	+
	1263	+static struct omap8250_platdata am654_platdata = {
	1264	+ .dma_params = &am654_dma,
	1265	+ .habit = UART_HAS_EFR2 \| UART_HAS_RHR_IT_DIS \|
	1266	+ UART_RX_TIMEOUT_QUIRK,
	1267	+};
	1268	+
	1269	+static struct omap8250_platdata am33xx_platdata = {
	1270	+ .dma_params = &am33xx_dma,
	1271	+ .habit = OMAP_DMA_TX_KICK \| UART_ERRATA_CLOCK_DISABLE,
	1272	+};
	1273	+
	1274	+static struct omap8250_platdata omap4_platdata = {
	1275	+ .dma_params = &am33xx_dma,
	1276	+ .habit = UART_ERRATA_CLOCK_DISABLE,
	1277	+};
1113	1278
1114	1279	static const struct of_device_id omap8250_dt_ids[] = {
1115		- { .compatible = "ti,am654-uart" },
	1280	+ { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1116	1281	{ .compatible = "ti,omap2-uart" },
1117	1282	{ .compatible = "ti,omap3-uart" },
1118		- { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1119		- { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1120		- { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1121		- { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
	1283	+ { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
	1284	+ { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
	1285	+ { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
	1286	+ { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1122	1287	{},
1123	1288	};
1124	1289	MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1125	1290
1126	1291	static int omap8250_probe(struct platform_device *pdev)
1127	1292	{
1128		- struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1129		- struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	1293	+ struct device_node *np = pdev->dev.of_node;
1130	1294	struct omap8250_priv *priv;
	1295	+ const struct omap8250_platdata *pdata;
1131	1296	struct uart_8250_port up;
1132		- int ret;
	1297	+ struct resource *regs;
1133	1298	void __iomem *membase;
	1299	+ int irq, ret;
1134	1300
1135		- if (!regs \|\| !irq) {
1136		- dev_err(&pdev->dev, "missing registers or irq\n");
	1301	+ irq = platform_get_irq(pdev, 0);
	1302	+ if (irq < 0)
	1303	+ return irq;
	1304	+
	1305	+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	1306	+ if (!regs) {
	1307	+ dev_err(&pdev->dev, "missing registers\n");
1137	1308	return -EINVAL;
1138	1309	}
1139	1310
..	..	@@ -1141,7 +1312,7 @@
1141	1312	if (!priv)
1142	1313	return -ENOMEM;
1143	1314
1144		- membase = devm_ioremap_nocache(&pdev->dev, regs->start,
	1315	+ membase = devm_ioremap(&pdev->dev, regs->start,
1145	1316	resource_size(regs));
1146	1317	if (!membase)
1147	1318	return -ENODEV;
..	..	@@ -1150,7 +1321,7 @@
1150	1321	up.port.dev = &pdev->dev;
1151	1322	up.port.mapbase = regs->start;
1152	1323	up.port.membase = membase;
1153		- up.port.irq = irq->start;
	1324	+ up.port.irq = irq;
1154	1325	/*
1155	1326	* It claims to be 16C750 compatible however it is a little different.
1156	1327	* It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
..	..	@@ -1185,28 +1356,39 @@
1185	1356	up.port.shutdown = omap_8250_shutdown;
1186	1357	up.port.throttle = omap_8250_throttle;
1187	1358	up.port.unthrottle = omap_8250_unthrottle;
1188		- up.port.rs485_config = omap_8250_rs485_config;
	1359	+ up.port.rs485_config = serial8250_em485_config;
	1360	+ up.rs485_start_tx = serial8250_em485_start_tx;
	1361	+ up.rs485_stop_tx = serial8250_em485_stop_tx;
	1362	+ up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1189	1363
1190		- if (pdev->dev.of_node) {
1191		- const struct of_device_id *id;
1192		-
1193		- ret = of_alias_get_id(pdev->dev.of_node, "serial");
1194		-
1195		- of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1196		- &up.port.uartclk);
1197		- priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1198		-
1199		- id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1200		- if (id && id->data)
1201		- priv->habit \|= (u8 )id->data;
1202		- } else {
1203		- ret = pdev->id;
1204		- }
	1364	+ ret = of_alias_get_id(np, "serial");
1205	1365	if (ret < 0) {
1206		- dev_err(&pdev->dev, "failed to get alias/pdev id\n");
	1366	+ dev_err(&pdev->dev, "failed to get alias\n");
1207	1367	return ret;
1208	1368	}
1209	1369	up.port.line = ret;
	1370	+
	1371	+ if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
	1372	+ struct clk *clk;
	1373	+
	1374	+ clk = devm_clk_get(&pdev->dev, NULL);
	1375	+ if (IS_ERR(clk)) {
	1376	+ if (PTR_ERR(clk) == -EPROBE_DEFER)
	1377	+ return -EPROBE_DEFER;
	1378	+ } else {
	1379	+ up.port.uartclk = clk_get_rate(clk);
	1380	+ }
	1381	+ }
	1382	+
	1383	+ if (of_property_read_u32(np, "overrun-throttle-ms",
	1384	+ &up.overrun_backoff_time_ms) != 0)
	1385	+ up.overrun_backoff_time_ms = 0;
	1386	+
	1387	+ priv->wakeirq = irq_of_parse_and_map(np, 1);
	1388	+
	1389	+ pdata = of_device_get_match_data(&pdev->dev);
	1390	+ if (pdata)
	1391	+ priv->habit \|= pdata->habit;
1210	1392
1211	1393	if (!up.port.uartclk) {
1212	1394	up.port.uartclk = DEFAULT_CLK_SPEED;
..	..	@@ -1215,10 +1397,9 @@
1215	1397	DEFAULT_CLK_SPEED);
1216	1398	}
1217	1399
1218		- priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1219		- priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1220		- pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1221		- priv->latency);
	1400	+ priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
	1401	+ priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
	1402	+ cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1222	1403	INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1223	1404
1224	1405	spin_lock_init(&priv->rx_dma_lock);
..	..	@@ -1226,7 +1407,16 @@
1226	1407	device_init_wakeup(&pdev->dev, true);
1227	1408	pm_runtime_enable(&pdev->dev);
1228	1409	pm_runtime_use_autosuspend(&pdev->dev);
1229		- pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
	1410	+
	1411	+ /*
	1412	+ * Disable runtime PM until autosuspend delay unless specifically
	1413	+ * enabled by the user via sysfs. This is the historic way to
	1414	+ * prevent an unsafe default policy with lossy characters on wake-up.
	1415	+ * For serdev devices this is not needed, the policy can be managed by
	1416	+ * the serdev driver.
	1417	+ */
	1418	+ if (!of_get_available_child_count(pdev->dev.of_node))
	1419	+ pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1230	1420
1231	1421	pm_runtime_irq_safe(&pdev->dev);
1232	1422
..	..	@@ -1234,25 +1424,38 @@
1234	1424
1235	1425	omap_serial_fill_features_erratas(&up, priv);
1236	1426	up.port.handle_irq = omap8250_no_handle_irq;
	1427	+ priv->rx_trigger = RX_TRIGGER;
	1428	+ priv->tx_trigger = TX_TRIGGER;
1237	1429	#ifdef CONFIG_SERIAL_8250_DMA
1238		- if (pdev->dev.of_node) {
1239		- /*
1240		- * Oh DMA support. If there are no DMA properties in the DT then
1241		- * we will fall back to a generic DMA channel which does not
1242		- * really work here. To ensure that we do not get a generic DMA
1243		- * channel assigned, we have the the_no_dma_filter_fn() here.
1244		- * To avoid "failed to request DMA" messages we check for DMA
1245		- * properties in DT.
1246		- */
1247		- ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1248		- if (ret == 2) {
1249		- up.dma = &priv->omap8250_dma;
1250		- priv->omap8250_dma.fn = the_no_dma_filter_fn;
1251		- priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1252		- priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1253		- priv->omap8250_dma.rx_size = RX_TRIGGER;
1254		- priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1255		- priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
	1430	+ /*
	1431	+ * Oh DMA support. If there are no DMA properties in the DT then
	1432	+ * we will fall back to a generic DMA channel which does not
	1433	+ * really work here. To ensure that we do not get a generic DMA
	1434	+ * channel assigned, we have the the_no_dma_filter_fn() here.
	1435	+ * To avoid "failed to request DMA" messages we check for DMA
	1436	+ * properties in DT.
	1437	+ */
	1438	+ ret = of_property_count_strings(np, "dma-names");
	1439	+ if (ret == 2) {
	1440	+ struct omap8250_dma_params *dma_params = NULL;
	1441	+
	1442	+ up.dma = &priv->omap8250_dma;
	1443	+ up.dma->fn = the_no_dma_filter_fn;
	1444	+ up.dma->tx_dma = omap_8250_tx_dma;
	1445	+ up.dma->rx_dma = omap_8250_rx_dma;
	1446	+ if (pdata)
	1447	+ dma_params = pdata->dma_params;
	1448	+
	1449	+ if (dma_params) {
	1450	+ up.dma->rx_size = dma_params->rx_size;
	1451	+ up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
	1452	+ up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
	1453	+ priv->rx_trigger = dma_params->rx_trigger;
	1454	+ priv->tx_trigger = dma_params->tx_trigger;
	1455	+ } else {
	1456	+ up.dma->rx_size = RX_TRIGGER;
	1457	+ up.dma->rxconf.src_maxburst = RX_TRIGGER;
	1458	+ up.dma->txconf.dst_maxburst = TX_TRIGGER;
1256	1459	}
1257	1460	}
1258	1461	#endif
..	..	@@ -1269,19 +1472,27 @@
1269	1472	err:
1270	1473	pm_runtime_dont_use_autosuspend(&pdev->dev);
1271	1474	pm_runtime_put_sync(&pdev->dev);
	1475	+ flush_work(&priv->qos_work);
1272	1476	pm_runtime_disable(&pdev->dev);
	1477	+ cpu_latency_qos_remove_request(&priv->pm_qos_request);
1273	1478	return ret;
1274	1479	}
1275	1480
1276	1481	static int omap8250_remove(struct platform_device *pdev)
1277	1482	{
1278	1483	struct omap8250_priv *priv = platform_get_drvdata(pdev);
	1484	+ int err;
	1485	+
	1486	+ err = pm_runtime_resume_and_get(&pdev->dev);
	1487	+ if (err)
	1488	+ return err;
1279	1489
1280	1490	pm_runtime_dont_use_autosuspend(&pdev->dev);
1281	1491	pm_runtime_put_sync(&pdev->dev);
	1492	+ flush_work(&priv->qos_work);
1282	1493	pm_runtime_disable(&pdev->dev);
1283	1494	serial8250_unregister_port(priv->line);
1284		- pm_qos_remove_request(&priv->pm_qos_request);
	1495	+ cpu_latency_qos_remove_request(&priv->pm_qos_request);
1285	1496	device_init_wakeup(&pdev->dev, false);
1286	1497	return 0;
1287	1498	}
..	..	@@ -1310,25 +1521,35 @@
1310	1521	{
1311	1522	struct omap8250_priv *priv = dev_get_drvdata(dev);
1312	1523	struct uart_8250_port *up = serial8250_get_port(priv->line);
	1524	+ int err;
1313	1525
1314	1526	serial8250_suspend_port(priv->line);
1315	1527
1316		- pm_runtime_get_sync(dev);
	1528	+ err = pm_runtime_resume_and_get(dev);
	1529	+ if (err)
	1530	+ return err;
1317	1531	if (!device_may_wakeup(dev))
1318	1532	priv->wer = 0;
1319	1533	serial_out(up, UART_OMAP_WER, priv->wer);
1320		- pm_runtime_mark_last_busy(dev);
1321		- pm_runtime_put_autosuspend(dev);
1322		-
	1534	+ err = pm_runtime_force_suspend(dev);
1323	1535	flush_work(&priv->qos_work);
1324		- return 0;
	1536	+
	1537	+ return err;
1325	1538	}
1326	1539
1327	1540	static int omap8250_resume(struct device *dev)
1328	1541	{
1329	1542	struct omap8250_priv *priv = dev_get_drvdata(dev);
	1543	+ int err;
1330	1544
	1545	+ err = pm_runtime_force_resume(dev);
	1546	+ if (err)
	1547	+ return err;
1331	1548	serial8250_resume_port(priv->line);
	1549	+ /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */
	1550	+ pm_runtime_mark_last_busy(dev);
	1551	+ pm_runtime_put_autosuspend(dev);
	1552	+
1332	1553	return 0;
1333	1554	}
1334	1555	#else
..	..	@@ -1431,7 +1652,7 @@
1431	1652	if (up->dma && up->dma->rxchan)
1432	1653	omap_8250_rx_dma_flush(up);
1433	1654
1434		- priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
	1655	+ priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1435	1656	schedule_work(&priv->qos_work);
1436	1657
1437	1658	return 0;
..	..	@@ -1451,7 +1672,7 @@
1451	1672	if (omap8250_lost_context(up))
1452	1673	omap8250_restore_regs(up);
1453	1674
1454		- if (up->dma && up->dma->rxchan)
	1675	+ if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1455	1676	omap_8250_rx_dma(up);
1456	1677
1457	1678	priv->latency = priv->calc_latency;