forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920
kernel/drivers/tty/serial/8250/8250_of.c
....@@ -7,7 +7,6 @@
77 #include <linux/console.h>
88 #include <linux/module.h>
99 #include <linux/slab.h>
10
-#include <linux/delay.h>
1110 #include <linux/serial_core.h>
1211 #include <linux/serial_reg.h>
1312 #include <linux/of_address.h>
....@@ -26,37 +25,16 @@
2625 int line;
2726 };
2827
29
-#ifdef CONFIG_ARCH_TEGRA
30
-static void tegra_serial_handle_break(struct uart_port *p)
31
-{
32
- unsigned int status, tmout = 10000;
33
-
34
- do {
35
- status = p->serial_in(p, UART_LSR);
36
- if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
37
- status = p->serial_in(p, UART_RX);
38
- else
39
- break;
40
- if (--tmout == 0)
41
- break;
42
- udelay(1);
43
- } while (1);
44
-}
45
-#else
46
-static inline void tegra_serial_handle_break(struct uart_port *port)
47
-{
48
-}
49
-#endif
50
-
5128 /*
5229 * Fill a struct uart_port for a given device node
5330 */
5431 static int of_platform_serial_setup(struct platform_device *ofdev,
55
- int type, struct uart_port *port,
32
+ int type, struct uart_8250_port *up,
5633 struct of_serial_info *info)
5734 {
5835 struct resource resource;
5936 struct device_node *np = ofdev->dev.of_node;
37
+ struct uart_port *port = &up->port;
6038 u32 clk, spd, prop;
6139 int ret, irq;
6240
....@@ -70,9 +48,10 @@
7048 /* Get clk rate through clk driver if present */
7149 info->clk = devm_clk_get(&ofdev->dev, NULL);
7250 if (IS_ERR(info->clk)) {
73
- dev_warn(&ofdev->dev,
74
- "clk or clock-frequency not defined\n");
7551 ret = PTR_ERR(info->clk);
52
+ if (ret != -EPROBE_DEFER)
53
+ dev_warn(&ofdev->dev,
54
+ "failed to get clock: %d\n", ret);
7655 goto err_pmruntime;
7756 }
7857
....@@ -185,12 +164,11 @@
185164 port->flags |= UPF_SKIP_TEST;
186165
187166 port->dev = &ofdev->dev;
167
+ port->rs485_config = serial8250_em485_config;
168
+ up->rs485_start_tx = serial8250_em485_start_tx;
169
+ up->rs485_stop_tx = serial8250_em485_stop_tx;
188170
189171 switch (type) {
190
- case PORT_TEGRA:
191
- port->handle_break = tegra_serial_handle_break;
192
- break;
193
-
194172 case PORT_RT2880:
195173 port->iotype = UPIO_AU;
196174 break;
....@@ -198,8 +176,10 @@
198176
199177 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
200178 (of_device_is_compatible(np, "fsl,ns16550") ||
201
- of_device_is_compatible(np, "fsl,16550-FIFO64")))
179
+ of_device_is_compatible(np, "fsl,16550-FIFO64"))) {
202180 port->handle_irq = fsl8250_handle_irq;
181
+ port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
182
+ }
203183
204184 return 0;
205185 err_unprepare:
....@@ -213,18 +193,16 @@
213193 /*
214194 * Try to register a serial port
215195 */
216
-static const struct of_device_id of_platform_serial_table[];
217196 static int of_platform_serial_probe(struct platform_device *ofdev)
218197 {
219
- const struct of_device_id *match;
220198 struct of_serial_info *info;
221199 struct uart_8250_port port8250;
200
+ unsigned int port_type;
222201 u32 tx_threshold;
223
- int port_type;
224202 int ret;
225203
226
- match = of_match_device(of_platform_serial_table, &ofdev->dev);
227
- if (!match)
204
+ port_type = (unsigned long)of_device_get_match_data(&ofdev->dev);
205
+ if (port_type == PORT_UNKNOWN)
228206 return -EINVAL;
229207
230208 if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas"))
....@@ -234,9 +212,8 @@
234212 if (info == NULL)
235213 return -ENOMEM;
236214
237
- port_type = (unsigned long)match->data;
238215 memset(&port8250, 0, sizeof(port8250));
239
- ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info);
216
+ ret = of_platform_serial_setup(ofdev, port_type, &port8250, info);
240217 if (ret)
241218 goto err_free;
242219
....@@ -336,9 +313,9 @@
336313 { .compatible = "ns16550", .data = (void *)PORT_16550, },
337314 { .compatible = "ns16750", .data = (void *)PORT_16750, },
338315 { .compatible = "ns16850", .data = (void *)PORT_16850, },
339
- { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
340316 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
341317 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
318
+ { .compatible = "intel,xscale-uart", .data = (void *)PORT_XSCALE, },
342319 { .compatible = "altr,16550-FIFO32",
343320 .data = (void *)PORT_ALTR_16550_F32, },
344321 { .compatible = "altr,16550-FIFO64",