forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/tty/serial/8250/8250_exar.c
....@@ -19,18 +19,19 @@
1919 #include <linux/string.h>
2020 #include <linux/tty.h>
2121 #include <linux/8250_pci.h>
22
+#include <linux/delay.h>
2223 
2324 #include <asm/byteorder.h>
2425 
2526 #include "8250.h"
2627 
27
-#define PCI_DEVICE_ID_ACCES_COM_2S		0x1052
28
-#define PCI_DEVICE_ID_ACCES_COM_4S		0x105d
29
-#define PCI_DEVICE_ID_ACCES_COM_8S		0x106c
30
-#define PCI_DEVICE_ID_ACCES_COM232_8		0x10a8
31
-#define PCI_DEVICE_ID_ACCES_COM_2SM		0x10d2
32
-#define PCI_DEVICE_ID_ACCES_COM_4SM		0x10db
33
-#define PCI_DEVICE_ID_ACCES_COM_8SM		0x10ea
28
+#define PCI_DEVICE_ID_ACCESSIO_COM_2S		0x1052
29
+#define PCI_DEVICE_ID_ACCESSIO_COM_4S		0x105d
30
+#define PCI_DEVICE_ID_ACCESSIO_COM_8S		0x106c
31
+#define PCI_DEVICE_ID_ACCESSIO_COM232_8		0x10a8
32
+#define PCI_DEVICE_ID_ACCESSIO_COM_2SM		0x10d2
33
+#define PCI_DEVICE_ID_ACCESSIO_COM_4SM		0x10db
34
+#define PCI_DEVICE_ID_ACCESSIO_COM_8SM		0x10ea
3435 
3536 #define PCI_DEVICE_ID_COMMTECH_4224PCI335	0x0002
3637 #define PCI_DEVICE_ID_COMMTECH_4222PCI335	0x0004
....@@ -39,11 +40,23 @@
3940 #define PCI_DEVICE_ID_COMMTECH_4224PCIE		0x0020
4041 #define PCI_DEVICE_ID_COMMTECH_4228PCIE		0x0021
4142 #define PCI_DEVICE_ID_COMMTECH_4222PCIE		0x0022
43
+
4244 #define PCI_DEVICE_ID_EXAR_XR17V4358		0x4358
4345 #define PCI_DEVICE_ID_EXAR_XR17V8358		0x8358
4446 
47
+#define PCI_SUBDEVICE_ID_USR_2980		0x0128
48
+#define PCI_SUBDEVICE_ID_USR_2981		0x0129
49
+
50
+#define PCI_DEVICE_ID_SEALEVEL_710xC		0x1001
51
+#define PCI_DEVICE_ID_SEALEVEL_720xC		0x1002
52
+#define PCI_DEVICE_ID_SEALEVEL_740xC		0x1004
53
+#define PCI_DEVICE_ID_SEALEVEL_780xC		0x1008
54
+#define PCI_DEVICE_ID_SEALEVEL_716xC		0x1010
55
+
4556 #define UART_EXAR_INT0		0x80
4657 #define UART_EXAR_8XMODE	0x88	/* 8X sampling rate select */
58
+#define UART_EXAR_SLEEP		0x8b	/* Sleep mode */
59
+#define UART_EXAR_DVID		0x8d	/* Device identification */
4760 
4861 #define UART_EXAR_FCTR		0x08	/* Feature Control Register */
4962 #define UART_FCTR_EXAR_IRDA	0x10	/* IrDa data encode select */
....@@ -132,8 +145,81 @@
132145 	unsigned int		nr;
133146 	struct exar8250_board	*board;
134147 	void __iomem		*virt;
135
-	int			line[0];
148
+	int			line[];
136149 };
150
+
151
+static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
152
+{
153
+	/*
154
+	 * Exar UARTs have a SLEEP register that enables or disables each UART
155
+	 * to enter sleep mode separately. On the XR17V35x the register
156
+	 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
157
+	 * the UART channel may only write to the corresponding bit.
158
+	 */
159
+	serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
160
+}
161
+
162
+/*
163
+ * XR17V35x UARTs have an extra fractional divisor register (DLD)
164
+ * Calculate divisor with extra 4-bit fractional portion
165
+ */
166
+static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
167
+					 unsigned int *frac)
168
+{
169
+	unsigned int quot_16;
170
+
171
+	quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
172
+	*frac = quot_16 & 0x0f;
173
+
174
+	return quot_16 >> 4;
175
+}
176
+
177
+static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
178
+				 unsigned int quot, unsigned int quot_frac)
179
+{
180
+	serial8250_do_set_divisor(p, baud, quot, quot_frac);
181
+
182
+	/* Preserve bits not related to baudrate; DLD[7:4]. */
183
+	quot_frac |= serial_port_in(p, 0x2) & 0xf0;
184
+	serial_port_out(p, 0x2, quot_frac);
185
+}
186
+
187
+static int xr17v35x_startup(struct uart_port *port)
188
+{
189
+	/*
190
+	 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
191
+	 * MCR [7:5] and MSR [7:0]
192
+	 */
193
+	serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
194
+
195
+	/*
196
+	 * Make sure all interrups are masked until initialization is
197
+	 * complete and the FIFOs are cleared
198
+	 */
199
+	serial_port_out(port, UART_IER, 0);
200
+
201
+	return serial8250_do_startup(port);
202
+}
203
+
204
+static void exar_shutdown(struct uart_port *port)
205
+{
206
+	unsigned char lsr;
207
+	bool tx_complete = false;
208
+	struct uart_8250_port *up = up_to_u8250p(port);
209
+	struct circ_buf *xmit = &port->state->xmit;
210
+	int i = 0;
211
+
212
+	do {
213
+		lsr = serial_in(up, UART_LSR);
214
+		if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
215
+			tx_complete = true;
216
+		else
217
+			tx_complete = false;
218
+		usleep_range(1000, 1100);
219
+	} while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
220
+
221
+	serial8250_do_shutdown(port);
222
+}
137223 
138224 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
139225 			 int idx, unsigned int offset,
....@@ -141,11 +227,34 @@
141227 {
142228 	const struct exar8250_board *board = priv->board;
143229 	unsigned int bar = 0;
230
+	unsigned char status;
144231 
145232 	port->port.iotype = UPIO_MEM;
146233 	port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
147234 	port->port.membase = priv->virt + offset;
148235 	port->port.regshift = board->reg_shift;
236
+
237
+	/*
238
+	 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
239
+	 * with when DLAB is set which will cause the device to incorrectly match
240
+	 * and assign port type to PORT_16650. The EFR for this UART is found
241
+	 * at offset 0x09. Instead check the Deice ID (DVID) register
242
+	 * for a 2, 4 or 8 port UART.
243
+	 */
244
+	status = readb(port->port.membase + UART_EXAR_DVID);
245
+	if (status == 0x82 || status == 0x84 || status == 0x88) {
246
+		port->port.type = PORT_XR17V35X;
247
+
248
+		port->port.get_divisor = xr17v35x_get_divisor;
249
+		port->port.set_divisor = xr17v35x_set_divisor;
250
+
251
+		port->port.startup = xr17v35x_startup;
252
+	} else {
253
+		port->port.type = PORT_XR17D15X;
254
+	}
255
+
256
+	port->port.pm = exar_pm;
257
+	port->port.shutdown = exar_shutdown;
149258 
150259 	return 0;
151260 }
....@@ -379,12 +488,15 @@
379488 	.register_gpio = iot2040_register_gpio,
380489 };
381490 
491
+/*
492
+ * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
493
+ * IOT2020 doesn't have. Therefore it is sufficient to match on the common
494
+ * board name after the device was found.
495
+ */
382496 static const struct dmi_system_id exar_platforms[] = {
383497 	{
384498 		.matches = {
385499 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
386
-			DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
387
-					"6ES7647-0AA00-1YA2"),
388500 		},
389501 		.driver_data = (void *)&iot2040_platform,
390502 	},
....@@ -449,6 +561,16 @@
449561 	port->port.private_data = NULL;
450562 }
451563 
564
+static inline void exar_misc_clear(struct exar8250 *priv)
565
+{
566
+	/* Clear all PCI interrupts by reading INT0. No effect on IIR */
567
+	readb(priv->virt + UART_EXAR_INT0);
568
+
569
+	/* Clear INT0 for Expansion Interface slave ports, too */
570
+	if (priv->board->num_ports > 8)
571
+		readb(priv->virt + 0x2000 + UART_EXAR_INT0);
572
+}
573
+
452574 /*
453575  * These Exar UARTs have an extra interrupt indicator that could fire for a
454576  * few interrupts that are not presented/cleared through IIR.  One of which is
....@@ -460,14 +582,7 @@
460582  */
461583 static irqreturn_t exar_misc_handler(int irq, void *data)
462584 {
463
-	struct exar8250 *priv = data;
464
-
465
-	/* Clear all PCI interrupts by reading INT0. No effect on IIR */
466
-	readb(priv->virt + UART_EXAR_INT0);
467
-
468
-	/* Clear INT0 for Expansion Interface slave ports, too */
469
-	if (priv->board->num_ports > 8)
470
-		readb(priv->virt + 0x2000 + UART_EXAR_INT0);
585
+	exar_misc_clear(data);
471586 
472587 	return IRQ_HANDLED;
473588 }
....@@ -491,11 +606,16 @@
491606 
492607 	maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
493608 
494
-	nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
609
+	if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
610
+		nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
611
+	else if (board->num_ports)
612
+		nr_ports = board->num_ports;
613
+	else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL)
614
+		nr_ports = pcidev->device & 0xff;
615
+	else
616
+		nr_ports = pcidev->device & 0x0f;
495617 
496
-	priv = devm_kzalloc(&pcidev->dev, sizeof(*priv) +
497
-			    sizeof(unsigned int) * nr_ports,
498
-			    GFP_KERNEL);
618
+	priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
499619 	if (!priv)
500620 		return -ENOMEM;
501621 
....@@ -511,8 +631,7 @@
511631 		return rc;
512632 
513633 	memset(&uart, 0, sizeof(uart));
514
-	uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ
515
-			  | UPF_EXAR_EFR;
634
+	uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
516635 	uart.port.irq = pci_irq_vector(pcidev, 0);
517636 	uart.port.dev = &pcidev->dev;
518637 
....@@ -520,6 +639,9 @@
520639 			 IRQF_SHARED, "exar_uart", priv);
521640 	if (rc)
522641 		return rc;
642
+
643
+	/* Clear interrupts */
644
+	exar_misc_clear(priv);
523645 
524646 	for (i = 0; i < nr_ports && i < maxnr; i++) {
525647 		rc = board->setup(priv, pcidev, &uart, i);
....@@ -576,9 +698,10 @@
576698 
577699 static int __maybe_unused exar_resume(struct device *dev)
578700 {
579
-	struct pci_dev *pcidev = to_pci_dev(dev);
580
-	struct exar8250 *priv = pci_get_drvdata(pcidev);
701
+	struct exar8250 *priv = dev_get_drvdata(dev);
581702 	unsigned int i;
703
+
704
+	exar_misc_clear(priv);
582705 
583706 	for (i = 0; i < priv->nr; i++)
584707 		if (priv->line[i] >= 0)
....@@ -588,22 +711,6 @@
588711 }
589712 
590713 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
591
-
592
-static const struct exar8250_board acces_com_2x = {
593
-	.num_ports	= 2,
594
-	.setup		= pci_xr17c154_setup,
595
-};
596
-
597
-static const struct exar8250_board acces_com_4x = {
598
-	.num_ports	= 4,
599
-	.setup		= pci_xr17c154_setup,
600
-};
601
-
602
-static const struct exar8250_board acces_com_8x = {
603
-	.num_ports	= 8,
604
-	.setup		= pci_xr17c154_setup,
605
-};
606
-
607714 
608715 static const struct exar8250_board pbn_fastcom335_2 = {
609716 	.num_ports	= 2,
....@@ -677,9 +784,7 @@
677784 		(kernel_ulong_t)&bd					\
678785 	}
679786 
680
-#define EXAR_DEVICE(vend, devid, bd) {					\
681
-	PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd	\
682
-	}
787
+#define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
683788 
684789 #define IBM_DEVICE(devid, sdevid, bd) {			\
685790 	PCI_DEVICE_SUB(					\
....@@ -690,15 +795,23 @@
690795 		(kernel_ulong_t)&bd			\
691796 	}
692797 
693
-static const struct pci_device_id exar_pci_tbl[] = {
694
-	EXAR_DEVICE(ACCESSIO, ACCES_COM_2S, acces_com_2x),
695
-	EXAR_DEVICE(ACCESSIO, ACCES_COM_4S, acces_com_4x),
696
-	EXAR_DEVICE(ACCESSIO, ACCES_COM_8S, acces_com_8x),
697
-	EXAR_DEVICE(ACCESSIO, ACCES_COM232_8, acces_com_8x),
698
-	EXAR_DEVICE(ACCESSIO, ACCES_COM_2SM, acces_com_2x),
699
-	EXAR_DEVICE(ACCESSIO, ACCES_COM_4SM, acces_com_4x),
700
-	EXAR_DEVICE(ACCESSIO, ACCES_COM_8SM, acces_com_8x),
798
+#define USR_DEVICE(devid, sdevid, bd) {			\
799
+	PCI_DEVICE_SUB(					\
800
+		PCI_VENDOR_ID_USR,			\
801
+		PCI_DEVICE_ID_EXAR_##devid,		\
802
+		PCI_VENDOR_ID_EXAR,			\
803
+		PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0,	\
804
+		(kernel_ulong_t)&bd			\
805
+	}
701806 
807
+static const struct pci_device_id exar_pci_tbl[] = {
808
+	EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
809
+	EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
810
+	EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
811
+	EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
812
+	EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
813
+	EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
814
+	EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
702815 
703816 	CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
704817 	CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
....@@ -715,25 +828,35 @@
715828 
716829 	IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
717830 
831
+	/* USRobotics USR298x-OEM PCI Modems */
832
+	USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
833
+	USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
834
+
718835 	/* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
719
-	EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
720
-	EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
721
-	EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
836
+	EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
837
+	EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
838
+	EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
722839 
723840 	/* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
724
-	EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
725
-	EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
726
-	EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
727
-	EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
728
-	EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
729
-	EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_fastcom35x_2),
730
-	EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_fastcom35x_4),
731
-	EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_fastcom35x_8),
841
+	EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
842
+	EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
843
+	EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
844
+	EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
845
+	EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
846
+	EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
847
+	EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
848
+	EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
732849 
733
-	EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
734
-	EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
735
-	EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
736
-	EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
850
+	EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
851
+	EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
852
+	EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
853
+	EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
854
+
855
+	EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x),
856
+	EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x),
857
+	EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x),
858
+	EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x),
859
+	EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x),
737860 	{ 0, }
738861 };
739862 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);