forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/soc/rockchip/pm_domains.c
....@@ -1,11 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Rockchip Generic power domain support.
34  *
45  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96  */
107 
118 #include <linux/module.h>
....@@ -30,16 +27,22 @@
3027 #include <dt-bindings/power/rv1126-power.h>
3128 #include <dt-bindings/power/rk1808-power.h>
3229 #include <dt-bindings/power/rk3036-power.h>
30
+#include <dt-bindings/power/rk3066-power.h>
3331 #include <dt-bindings/power/rk3128-power.h>
32
+#include <dt-bindings/power/rk3188-power.h>
3433 #include <dt-bindings/power/rk3228-power.h>
3534 #include <dt-bindings/power/rk3288-power.h>
3635 #include <dt-bindings/power/rk3328-power.h>
3736 #include <dt-bindings/power/rk3366-power.h>
3837 #include <dt-bindings/power/rk3368-power.h>
3938 #include <dt-bindings/power/rk3399-power.h>
39
+#include <dt-bindings/power/rk3528-power.h>
40
+#include <dt-bindings/power/rk3562-power.h>
4041 #include <dt-bindings/power/rk3568-power.h>
42
+#include <dt-bindings/power/rk3588-power.h>
4143 
4244 struct rockchip_domain_info {
45
+	const char *name;
4346 	int pwr_mask;
4447 	int status_mask;
4548 	int req_mask;
....@@ -48,9 +51,15 @@
4851 	bool active_wakeup;
4952 	int pwr_w_mask;
5053 	int req_w_mask;
54
+	int mem_status_mask;
55
+	int repair_status_mask;
56
+	int clk_ungate_mask;
57
+	int clk_ungate_w_mask;
58
+	int mem_num;
5159 	bool keepon_startup;
5260 	bool always_on;
5361 	u32 pwr_offset;
62
+	u32 mem_offset;
5463 	u32 req_offset;
5564 };
5665 
....@@ -60,6 +69,12 @@
6069 	u32 req_offset;
6170 	u32 idle_offset;
6271 	u32 ack_offset;
72
+	u32 mem_pwr_offset;
73
+	u32 chain_status_offset;
74
+	u32 mem_status_offset;
75
+	u32 repair_status_offset;
76
+	u32 clk_ungate_offset;
77
+	u32 mem_sd_offset;
6378 
6479 	u32 core_pwrcnt_offset;
6580 	u32 gpu_pwrcnt_offset;
....@@ -78,17 +93,26 @@
7893 #define QOS_SATURATION		0x14
7994 #define QOS_EXTCONTROL		0x18
8095 
96
+#define SHAPING_NBPKTMAX0	0x0
97
+
8198 struct rockchip_pm_domain {
8299 	struct generic_pm_domain genpd;
83100 	const struct rockchip_domain_info *info;
84101 	struct rockchip_pmu *pmu;
85102 	int num_qos;
103
+	int num_shaping;
86104 	struct regmap **qos_regmap;
105
+	struct regmap **shaping_regmap;
87106 	u32 *qos_save_regs[MAX_QOS_REGS_NUM];
107
+	u32 *shaping_save_regs;
108
+	bool *qos_is_need_init[MAX_QOS_REGS_NUM];
109
+	bool *shaping_is_need_init;
88110 	int num_clks;
89111 	struct clk_bulk_data *clks;
90112 	bool is_ignore_pwr;
91113 	bool is_qos_saved;
114
+	bool is_qos_need_init;
115
+	bool is_shaping_need_init;
92116 	struct regulator *supply;
93117 };
94118 
....@@ -122,8 +146,9 @@
122146 
123147 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
124148 
125
-#define DOMAIN(pwr, status, req, idle, ack, wakeup, keepon)	\
149
+#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup, keepon)	\
126150 {							\
151
+	.name = _name,					\
127152 	.pwr_mask = (pwr),				\
128153 	.status_mask = (status),			\
129154 	.req_mask = (req),				\
....@@ -133,8 +158,9 @@
133158 	.keepon_startup = (keepon),			\
134159 }
135160 
136
-#define DOMAIN_M(pwr, status, req, idle, ack, wakeup, keepon)	\
161
+#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup, keepon)	\
137162 {							\
163
+	.name = _name,					\
138164 	.pwr_w_mask = (pwr) << 16,			\
139165 	.pwr_mask = (pwr),				\
140166 	.status_mask = (status),			\
....@@ -146,8 +172,40 @@
146172 	.keepon_startup = keepon,			\
147173 }
148174 
149
-#define DOMAIN_M_O(pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon)	\
175
+#define DOMAIN_M_A(pwr, status, req, idle, ack, always, wakeup, keepon)	\
150176 {							\
177
+	.pwr_w_mask = (pwr) << 16,			\
178
+	.pwr_mask = (pwr),				\
179
+	.status_mask = (status),			\
180
+	.req_w_mask = (req) << 16,			\
181
+	.req_mask = (req),				\
182
+	.idle_mask = (idle),				\
183
+	.ack_mask = (ack),				\
184
+	.always_on = always,				\
185
+	.active_wakeup = wakeup,			\
186
+	.keepon_startup = keepon,			\
187
+}
188
+
189
+#define DOMAIN_M_C_SD(_name, pwr, status, req, idle, ack, clk, mem, wakeup, keepon)	\
190
+{							\
191
+	.name = _name,					\
192
+	.pwr_w_mask = (pwr) << 16,			\
193
+	.pwr_mask = (pwr),				\
194
+	.status_mask = (status),			\
195
+	.req_w_mask = (req) << 16,			\
196
+	.req_mask = (req),				\
197
+	.idle_mask = (idle),				\
198
+	.ack_mask = (ack),				\
199
+	.clk_ungate_mask = (clk),			\
200
+	.clk_ungate_w_mask = (clk) << 16,		\
201
+	.mem_num = (mem),				\
202
+	.active_wakeup = wakeup,			\
203
+	.keepon_startup = keepon,			\
204
+}
205
+
206
+#define DOMAIN_M_O(_name, pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon)	\
207
+{							\
208
+	.name = _name,					\
151209 	.pwr_w_mask = (pwr) << 16,			\
152210 	.pwr_mask = (pwr),				\
153211 	.status_mask = (status),			\
....@@ -161,8 +219,28 @@
161219 	.req_offset = r_offset,				\
162220 }
163221 
164
-#define DOMAIN_RK3036(req, ack, idle, wakeup)		\
222
+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, keepon)	\
165223 {							\
224
+	.name = _name,					\
225
+	.pwr_offset = p_offset,				\
226
+	.pwr_w_mask = (pwr) << 16,			\
227
+	.pwr_mask = (pwr),				\
228
+	.status_mask = (status),			\
229
+	.mem_offset = m_offset,				\
230
+	.mem_status_mask = (m_status),			\
231
+	.repair_status_mask = (r_status),		\
232
+	.req_offset = r_offset,				\
233
+	.req_w_mask = (req) << 16,			\
234
+	.req_mask = (req),				\
235
+	.idle_mask = (idle),				\
236
+	.ack_mask = (ack),				\
237
+	.active_wakeup = wakeup,			\
238
+	.keepon_startup = keepon,			\
239
+}
240
+
241
+#define DOMAIN_RK3036(_name, req, ack, idle, wakeup)	\
242
+{							\
243
+	.name = _name,					\
166244 	.req_mask = (req),				\
167245 	.req_w_mask = (req) << 16,			\
168246 	.ack_mask = (ack),				\
....@@ -170,47 +248,62 @@
170248 	.active_wakeup = wakeup,			\
171249 }
172250 
173
-#define DOMAIN_PX30(pwr, status, req, wakeup)		\
174
-	DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup, false)
251
+#define DOMAIN_PX30(name, pwr, status, req, wakeup)		\
252
+	DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup, false)
175253 
176
-#define DOMAIN_PX30_PROTECT(pwr, status, req, wakeup)	\
177
-	DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup, true)
254
+#define DOMAIN_PX30_PROTECT(name, pwr, status, req, wakeup)	\
255
+	DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup, true)
178256 
179
-#define DOMAIN_RV1126(pwr, req, idle, wakeup)		\
180
-	DOMAIN_M(pwr, pwr, req, idle, idle, wakeup, false)
257
+#define DOMAIN_RV1126(name, pwr, req, idle, wakeup)		\
258
+	DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup, false)
181259 
182
-#define DOMAIN_RV1126_PROTECT(pwr, req, idle, wakeup)	\
183
-	DOMAIN_M(pwr, pwr, req, idle, idle, wakeup, true)
260
+#define DOMAIN_RV1126_PROTECT(name, pwr, req, idle, wakeup)	\
261
+	DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup, true)
184262 
185
-#define DOMAIN_RV1126_O(pwr, req, idle, r_offset, wakeup)	\
186
-	DOMAIN_M_O(pwr, pwr, 0, req, idle, idle, r_offset, wakeup, false)
263
+#define DOMAIN_RV1126_O(name, pwr, req, idle, r_offset, wakeup)	\
264
+	DOMAIN_M_O(name, pwr, pwr, 0, req, idle, idle, r_offset, wakeup, false)
187265 
188
-#define DOMAIN_RK3288(pwr, status, req, wakeup)		\
189
-	DOMAIN(pwr, status, req, req, (req) << 16, wakeup, false)
266
+#define DOMAIN_RK3288(name, pwr, status, req, wakeup)		\
267
+	DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup, false)
190268 
191
-#define DOMAIN_RK3288_PROTECT(pwr, status, req, wakeup)	\
192
-	DOMAIN(pwr, status, req, req, (req) << 16, wakeup, true)
269
+#define DOMAIN_RK3288_PROTECT(name, pwr, status, req, wakeup)	\
270
+	DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup, true)
193271 
194
-#define DOMAIN_RK3328(pwr, status, req, wakeup)		\
195
-	DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup, false)
272
+#define DOMAIN_RK3328(name, pwr, status, req, wakeup)		\
273
+	DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup, false)
196274 
197
-#define DOMAIN_RK3368(pwr, status, req, wakeup)		\
198
-	DOMAIN(pwr, status, req, (req) << 16, req, wakeup, false)
275
+#define DOMAIN_RK3368(name, pwr, status, req, wakeup)		\
276
+	DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup, false)
199277 
200
-#define DOMAIN_RK3368_PROTECT(pwr, status, req, wakeup)	\
201
-	DOMAIN(pwr, status, req, (req) << 16, req, wakeup, true)
278
+#define DOMAIN_RK3368_PROTECT(name, pwr, status, req, wakeup)	\
279
+	DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup, true)
202280 
203
-#define DOMAIN_RK3399(pwr, status, req, wakeup)		\
204
-	DOMAIN(pwr, status, req, req, req, wakeup, false)
281
+#define DOMAIN_RK3399(name, pwr, status, req, wakeup)		\
282
+	DOMAIN(name, pwr, status, req, req, req, wakeup, false)
205283 
206
-#define DOMAIN_RK3399_PROTECT(pwr, status, req, wakeup)	\
207
-	DOMAIN(pwr, status, req, req, req, wakeup, true)
284
+#define DOMAIN_RK3399_PROTECT(name, pwr, status, req, wakeup)	\
285
+	DOMAIN(name, pwr, status, req, req, req, wakeup, true)
208286 
209
-#define DOMAIN_RK3568(pwr, req, wakeup)		\
210
-	DOMAIN_M(pwr, pwr, req, req, req, wakeup, false)
287
+#define DOMAIN_RK3528(pwr, req, always, wakeup) \
288
+	DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false)
211289 
212
-#define DOMAIN_RK3568_PROTECT(pwr, req, wakeup)		\
213
-	DOMAIN_M(pwr, pwr, req, req, req, wakeup, true)
290
+#define DOMAIN_RK3562(name, pwr, req, mem, wakeup)		\
291
+	DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, false)
292
+
293
+#define DOMAIN_RK3562_PROTECT(name, pwr, req, mem, wakeup)		\
294
+	DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, true)
295
+
296
+#define DOMAIN_RK3568(name, pwr, req, wakeup)			\
297
+	DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false)
298
+
299
+#define DOMAIN_RK3568_PROTECT(name, pwr, req, wakeup)		\
300
+	DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, true)
301
+
302
+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup)	\
303
+	DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, false)
304
+
305
+#define DOMAIN_RK3588_P(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup)	\
306
+	DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, true)
214307 
215308 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
216309 {
....@@ -228,6 +321,42 @@
228321 
229322 	regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
230323 	return val;
324
+}
325
+
326
+static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
327
+{
328
+	const struct rockchip_domain_info *pd_info = pd->info;
329
+	struct rockchip_pmu *pmu = pd->pmu;
330
+	unsigned int val;
331
+
332
+	if (!pd_info->clk_ungate_mask)
333
+		return 0;
334
+	if (!pmu->info->clk_ungate_offset)
335
+		return 0;
336
+
337
+	val = ungate ? (pd_info->clk_ungate_mask | pd_info->clk_ungate_w_mask) :
338
+			pd_info->clk_ungate_w_mask;
339
+	regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
340
+
341
+	return 0;
342
+}
343
+
344
+static int rockchip_pmu_mem_shut_down(struct rockchip_pm_domain *pd, bool sd)
345
+{
346
+	const struct rockchip_domain_info *pd_info = pd->info;
347
+	struct rockchip_pmu *pmu = pd->pmu;
348
+	unsigned int i;
349
+
350
+	if (!pd_info->mem_num)
351
+		return 0;
352
+	if (!pmu->info->mem_sd_offset)
353
+		return 0;
354
+
355
+	for (i = 0; i < pd_info->mem_num; i++)
356
+		regmap_write(pmu->regmap, pmu->info->mem_sd_offset,
357
+			     (sd << i) | (1 << (i + 16)));
358
+
359
+	return 0;
231360 }
232361 
233362 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
....@@ -308,6 +437,45 @@
308437 }
309438 EXPORT_SYMBOL(rockchip_pmu_idle_request);
310439 
440
+static int rockchip_pmu_save_shaping(struct rockchip_pm_domain *pd)
441
+{
442
+	int i;
443
+
444
+	for (i = 0; i < pd->num_shaping; i++)
445
+		regmap_read(pd->shaping_regmap[i], SHAPING_NBPKTMAX0,
446
+			    &pd->shaping_save_regs[i]);
447
+
448
+	return 0;
449
+}
450
+
451
+static int rockchip_pmu_restore_shaping(struct rockchip_pm_domain *pd)
452
+{
453
+	int i;
454
+
455
+	for (i = 0; i < pd->num_shaping; i++)
456
+		regmap_write(pd->shaping_regmap[i], SHAPING_NBPKTMAX0,
457
+			     pd->shaping_save_regs[i]);
458
+
459
+	return 0;
460
+}
461
+
462
+static void rockchip_pmu_init_shaping(struct rockchip_pm_domain *pd)
463
+{
464
+	int i;
465
+
466
+	if (!pd->is_shaping_need_init)
467
+		return;
468
+
469
+	for (i = 0; i < pd->num_shaping; i++)
470
+		if (pd->shaping_is_need_init[i])
471
+			regmap_write(pd->shaping_regmap[i], SHAPING_NBPKTMAX0,
472
+				     pd->shaping_save_regs[i]);
473
+
474
+	kfree(pd->shaping_is_need_init);
475
+	pd->shaping_is_need_init = NULL;
476
+	pd->is_shaping_need_init = false;
477
+}
478
+
311479 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
312480 {
313481 	int i;
....@@ -329,7 +497,8 @@
329497 			    QOS_EXTCONTROL,
330498 			    &pd->qos_save_regs[4][i]);
331499 	}
332
-	return 0;
500
+
501
+	return rockchip_pmu_save_shaping(pd);
333502 }
334503 
335504 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
....@@ -354,7 +523,48 @@
354523 			     pd->qos_save_regs[4][i]);
355524 	}
356525 
357
-	return 0;
526
+	return rockchip_pmu_restore_shaping(pd);
527
+}
528
+
529
+static void rockchip_pmu_init_qos(struct rockchip_pm_domain *pd)
530
+{
531
+	int i;
532
+
533
+	rockchip_pmu_init_shaping(pd);
534
+
535
+	if (!pd->is_qos_need_init)
536
+		return;
537
+
538
+	for (i = 0; i < pd->num_qos; i++) {
539
+		if (pd->qos_is_need_init[0][i])
540
+			regmap_write(pd->qos_regmap[i],
541
+				     QOS_PRIORITY,
542
+				     pd->qos_save_regs[0][i]);
543
+
544
+		if (pd->qos_is_need_init[1][i])
545
+			regmap_write(pd->qos_regmap[i],
546
+				     QOS_MODE,
547
+				     pd->qos_save_regs[1][i]);
548
+
549
+		if (pd->qos_is_need_init[2][i])
550
+			regmap_write(pd->qos_regmap[i],
551
+				     QOS_BANDWIDTH,
552
+				     pd->qos_save_regs[2][i]);
553
+
554
+		if (pd->qos_is_need_init[3][i])
555
+			regmap_write(pd->qos_regmap[i],
556
+				     QOS_SATURATION,
557
+				     pd->qos_save_regs[3][i]);
558
+
559
+		if (pd->qos_is_need_init[4][i])
560
+			regmap_write(pd->qos_regmap[i],
561
+				     QOS_EXTCONTROL,
562
+				     pd->qos_save_regs[4][i]);
563
+	}
564
+
565
+	kfree(pd->qos_is_need_init[0]);
566
+	pd->qos_is_need_init[0] = NULL;
567
+	pd->is_qos_need_init = false;
358568 }
359569 
360570 int rockchip_save_qos(struct device *dev)
....@@ -403,10 +613,88 @@
403613 }
404614 EXPORT_SYMBOL(rockchip_restore_qos);
405615 
616
+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
617
+{
618
+	struct rockchip_pmu *pmu = pd->pmu;
619
+	unsigned int val;
620
+
621
+	regmap_read(pmu->regmap,
622
+		    pmu->info->mem_status_offset + pd->info->mem_offset, &val);
623
+
624
+	/* 1'b0: power on, 1'b1: power off */
625
+	return !(val & pd->info->mem_status_mask);
626
+}
627
+
628
+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
629
+{
630
+	struct rockchip_pmu *pmu = pd->pmu;
631
+	unsigned int val;
632
+
633
+	regmap_read(pmu->regmap,
634
+		    pmu->info->chain_status_offset + pd->info->mem_offset, &val);
635
+
636
+	/* 1'b1: power on, 1'b0: power off */
637
+	return val & pd->info->mem_status_mask;
638
+}
639
+
640
+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
641
+{
642
+	struct rockchip_pmu *pmu = pd->pmu;
643
+	struct generic_pm_domain *genpd = &pd->genpd;
644
+	bool is_on;
645
+	int ret = 0;
646
+
647
+	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
648
+					is_on == true, 0, 10000);
649
+	if (ret) {
650
+		dev_err(pmu->dev,
651
+			"failed to get chain status '%s', target_on=1, val=%d\n",
652
+			genpd->name, is_on);
653
+		goto error;
654
+	}
655
+
656
+	udelay(60);
657
+
658
+	regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
659
+		     (pd->info->pwr_mask | pd->info->pwr_w_mask));
660
+	dsb(sy);
661
+
662
+	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
663
+					is_on == false, 0, 10000);
664
+	if (ret) {
665
+		dev_err(pmu->dev,
666
+			"failed to get mem status '%s', target_on=0, val=%d\n",
667
+			genpd->name, is_on);
668
+		goto error;
669
+	}
670
+
671
+	regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
672
+		     pd->info->pwr_w_mask);
673
+	dsb(sy);
674
+
675
+	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
676
+					is_on == true, 0, 10000);
677
+	if (ret) {
678
+		dev_err(pmu->dev,
679
+			"failed to get mem status '%s', target_on=1, val=%d\n",
680
+			genpd->name, is_on);
681
+	}
682
+
683
+error:
684
+
685
+	return ret;
686
+}
687
+
406688 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
407689 {
408690 	struct rockchip_pmu *pmu = pd->pmu;
409691 	unsigned int val;
692
+
693
+	if (pd->info->repair_status_mask) {
694
+		regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
695
+		/* 1'b1: power on, 1'b0: power off */
696
+		return val & pd->info->repair_status_mask;
697
+	}
410698 
411699 	/* check idle status for idle-only domains */
412700 	if (pd->info->status_mask == 0)
....@@ -424,15 +712,19 @@
424712 	struct rockchip_pmu *pmu = pd->pmu;
425713 	struct generic_pm_domain *genpd = &pd->genpd;
426714 	u32 pd_pwr_offset = 0;
427
-	bool is_on;
715
+	bool is_on, is_mem_on = false;
428716 	int ret = 0;
717
+
718
+	if (pd->info->pwr_mask == 0)
719
+		return 0;
720
+
721
+	if (on && pd->info->mem_status_mask)
722
+		is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
429723 
430724 	if (pd->info->pwr_offset)
431725 		pd_pwr_offset = pd->info->pwr_offset;
432726 
433
-	if (pd->info->pwr_mask == 0)
434
-		return 0;
435
-	else if (pd->info->pwr_w_mask)
727
+	if (pd->info->pwr_w_mask)
436728 		regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
437729 			     on ? pd->info->pwr_w_mask :
438730 			     (pd->info->pwr_mask | pd->info->pwr_w_mask));
....@@ -442,6 +734,12 @@
442734 				   on ? 0 : -1U);
443735 
444736 	dsb(sy);
737
+
738
+	if (is_mem_on) {
739
+		ret = rockchip_pmu_domain_mem_reset(pd);
740
+		if (ret)
741
+			goto error;
742
+	}
445743 
446744 	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
447745 					is_on == on, 0, 10000);
....@@ -467,8 +765,8 @@
467765 	if (pm_domain_always_on && !power_on)
468766 		return 0;
469767 
470
-	if (!power_on && (soc_is_px30s())) {
471
-		if (genpd->name && !strcmp(genpd->name, "pd_gpu"))
768
+	if (!power_on && soc_is_px30s()) {
769
+		if (genpd->name && !strcmp(genpd->name, "gpu"))
472770 			return 0;
473771 	}
474772 
....@@ -496,6 +794,7 @@
496794 			rockchip_pmu_unlock(pd);
497795 			return ret;
498796 		}
797
+		rockchip_pmu_ungate_clk(pd, true);
499798 
500799 		if (!power_on) {
501800 			rockchip_pmu_save_qos(pd);
....@@ -508,6 +807,7 @@
508807 					genpd->name);
509808 				goto out;
510809 			}
810
+			rockchip_pmu_mem_shut_down(pd, true);
511811 		}
512812 
513813 		ret = rockchip_do_pmu_set_power_domain(pd, power_on);
....@@ -518,6 +818,7 @@
518818 		}
519819 
520820 		if (power_on) {
821
+			rockchip_pmu_mem_shut_down(pd, false);
521822 			/* if powering up, leave idle mode */
522823 			ret = rockchip_pmu_set_idle_request(pd, false);
523824 			if (ret) {
....@@ -528,9 +829,12 @@
528829 
529830 			if (pd->is_qos_saved)
530831 				rockchip_pmu_restore_qos(pd);
832
+			if (pd->is_qos_need_init || pd->is_shaping_need_init)
833
+				rockchip_pmu_init_qos(pd);
531834 		}
532835 
533836 out:
837
+		rockchip_pmu_ungate_clk(pd, false);
534838 		clk_bulk_disable(pd->num_clks, pd->clks);
535839 
536840 		if (!power_on && !IS_ERR(pd->supply))
....@@ -658,44 +962,31 @@
658962 	pm_clk_destroy(dev);
659963 }
660964 
661
-static void rockchip_pd_qos_init(struct rockchip_pm_domain *pd,
662
-				 bool **qos_is_need_init)
965
+static void rockchip_pd_qos_init(struct rockchip_pm_domain *pd)
663966 {
664
-	int i, is_pd_on;
967
+	int is_pd_on, ret = 0;
968
+
969
+	if (!pd->is_qos_need_init) {
970
+		kfree(pd->qos_is_need_init[0]);
971
+		pd->qos_is_need_init[0] = NULL;
972
+	}
973
+	if (!pd->is_shaping_need_init) {
974
+		kfree(pd->shaping_is_need_init);
975
+		pd->shaping_is_need_init = NULL;
976
+	}
977
+	if (!pd->is_qos_need_init && !pd->is_shaping_need_init)
978
+		return;
665979 
666980 	is_pd_on = rockchip_pmu_domain_is_on(pd);
667
-	if (!is_pd_on)
668
-		rockchip_pd_power(pd, true);
669
-
670
-	for (i = 0; i < pd->num_qos; i++) {
671
-		if (qos_is_need_init[0][i])
672
-			regmap_write(pd->qos_regmap[i],
673
-				     QOS_PRIORITY,
674
-				     pd->qos_save_regs[0][i]);
675
-
676
-		if (qos_is_need_init[1][i])
677
-			regmap_write(pd->qos_regmap[i],
678
-				     QOS_MODE,
679
-				     pd->qos_save_regs[1][i]);
680
-
681
-		if (qos_is_need_init[2][i])
682
-			regmap_write(pd->qos_regmap[i],
683
-				     QOS_BANDWIDTH,
684
-				     pd->qos_save_regs[2][i]);
685
-
686
-		if (qos_is_need_init[3][i])
687
-			regmap_write(pd->qos_regmap[i],
688
-				     QOS_SATURATION,
689
-				     pd->qos_save_regs[3][i]);
690
-
691
-		if (qos_is_need_init[4][i])
692
-			regmap_write(pd->qos_regmap[i],
693
-				     QOS_EXTCONTROL,
694
-				     pd->qos_save_regs[4][i]);
981
+	if (is_pd_on) {
982
+		ret = clk_bulk_enable(pd->num_clks, pd->clks);
983
+		if (ret < 0) {
984
+			dev_err(pd->pmu->dev, "failed to enable clocks\n");
985
+			return;
986
+		}
987
+		rockchip_pmu_init_qos(pd);
988
+		clk_bulk_disable(pd->num_clks, pd->clks);
695989 	}
696
-
697
-	if (!is_pd_on)
698
-		rockchip_pd_power(pd, false);
699990 }
700991 
701992 static int rockchip_pd_add_alwasy_on_flag(struct rockchip_pm_domain *pd)
....@@ -718,6 +1009,79 @@
7181009 	return 0;
7191010 }
7201011 
1012
+static int rockchip_pd_of_get_shaping(struct rockchip_pm_domain *pd,
1013
+				      struct device_node *node)
1014
+{
1015
+	struct rockchip_pmu *pmu = pd->pmu;
1016
+	struct device_node *shaping_node;
1017
+	int num_shaping = 0, num_shaping_reg = 0;
1018
+	int error, i;
1019
+	u32 val;
1020
+
1021
+	num_shaping = of_count_phandle_with_args(node, "pm_shaping", NULL);
1022
+
1023
+	for (i = 0; i < num_shaping; i++) {
1024
+		shaping_node = of_parse_phandle(node, "pm_shaping", i);
1025
+		if (shaping_node && of_device_is_available(shaping_node))
1026
+			pd->num_shaping++;
1027
+		of_node_put(shaping_node);
1028
+	}
1029
+
1030
+	if (pd->num_shaping > 0) {
1031
+		pd->shaping_regmap = devm_kcalloc(pmu->dev, pd->num_shaping,
1032
+						  sizeof(*pd->shaping_regmap),
1033
+						  GFP_KERNEL);
1034
+		if (!pd->shaping_regmap)
1035
+			return -ENOMEM;
1036
+		pd->shaping_save_regs = devm_kmalloc(pmu->dev, sizeof(u32) *
1037
+						     pd->num_shaping,
1038
+						     GFP_KERNEL);
1039
+		if (!pd->shaping_save_regs)
1040
+			return -ENOMEM;
1041
+		pd->shaping_is_need_init = kcalloc(pd->num_shaping, sizeof(bool),
1042
+						   GFP_KERNEL);
1043
+		if (!pd->shaping_is_need_init)
1044
+			return -ENOMEM;
1045
+		for (i = 0; i < num_shaping; i++) {
1046
+			shaping_node = of_parse_phandle(node, "pm_shaping", i);
1047
+			if (!shaping_node) {
1048
+				error = -ENODEV;
1049
+				goto err_free_init;
1050
+			}
1051
+			if (of_device_is_available(shaping_node)) {
1052
+				pd->shaping_regmap[num_shaping_reg] =
1053
+					syscon_node_to_regmap(shaping_node);
1054
+				if (IS_ERR(pd->shaping_regmap[num_shaping_reg])) {
1055
+					of_node_put(shaping_node);
1056
+					error =  -ENODEV;
1057
+					goto err_free_init;
1058
+				}
1059
+				if (!of_property_read_u32(shaping_node,
1060
+							  "shaping-init",
1061
+							  &val)) {
1062
+					pd->shaping_save_regs[i] = val;
1063
+					pd->shaping_is_need_init[i] = true;
1064
+					pd->is_shaping_need_init = true;
1065
+				}
1066
+				num_shaping_reg++;
1067
+			}
1068
+			of_node_put(shaping_node);
1069
+			if (num_shaping_reg > pd->num_shaping) {
1070
+				error =  -EINVAL;
1071
+				goto err_free_init;
1072
+			}
1073
+		}
1074
+	}
1075
+
1076
+	return 0;
1077
+
1078
+err_free_init:
1079
+	kfree(pd->shaping_is_need_init);
1080
+	pd->shaping_is_need_init = NULL;
1081
+
1082
+	return error;
1083
+}
1084
+
7211085 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
7221086 				      struct device_node *node)
7231087 {
....@@ -728,27 +1092,27 @@
7281092 	int i, j;
7291093 	u32 id, val;
7301094 	int error;
731
-	bool *qos_is_need_init[MAX_QOS_REGS_NUM] = { NULL };
732
-	bool is_qos_need_init = false;
7331095 
7341096 	error = of_property_read_u32(node, "reg", &id);
7351097 	if (error) {
7361098 		dev_err(pmu->dev,
737
-			"%s: failed to retrieve domain id (reg): %d\n",
738
-			node->name, error);
1099
+			"%pOFn: failed to retrieve domain id (reg): %d\n",
1100
+			node, error);
7391101 		return -EINVAL;
7401102 	}
7411103 
7421104 	if (id >= pmu->info->num_domains) {
743
-		dev_err(pmu->dev, "%s: invalid domain id %d\n",
744
-			node->name, id);
1105
+		dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
1106
+			node, id);
7451107 		return -EINVAL;
7461108 	}
1109
+	if (pmu->genpd_data.domains[id])
1110
+		return 0;
7471111 
7481112 	pd_info = &pmu->info->domain_info[id];
7491113 	if (!pd_info) {
750
-		dev_err(pmu->dev, "%s: undefined domain id %d\n",
751
-			node->name, id);
1114
+		dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
1115
+			node, id);
7521116 		return -EINVAL;
7531117 	}
7541118 
....@@ -768,8 +1132,8 @@
7681132 		if (!pd->clks)
7691133 			return -ENOMEM;
7701134 	} else {
771
-		dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n",
772
-			node->name, pd->num_clks);
1135
+		dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
1136
+			node, pd->num_clks);
7731137 		pd->num_clks = 0;
7741138 	}
7751139 
....@@ -778,8 +1142,8 @@
7781142 		if (IS_ERR(pd->clks[i].clk)) {
7791143 			error = PTR_ERR(pd->clks[i].clk);
7801144 			dev_err(pmu->dev,
781
-				"%s: failed to get clk at index %d: %d\n",
782
-				node->name, i, error);
1145
+				"%pOFn: failed to get clk at index %d: %d\n",
1146
+				node, i, error);
7831147 			return error;
7841148 		}
7851149 	}
....@@ -815,18 +1179,19 @@
8151179 			error = -ENOMEM;
8161180 			goto err_unprepare_clocks;
8171181 		}
818
-		qos_is_need_init[0] = kzalloc(sizeof(bool) *
819
-					      MAX_QOS_REGS_NUM *
820
-					      pd->num_qos,
821
-					      GFP_KERNEL);
822
-		if (!qos_is_need_init[0]) {
1182
+		pd->qos_is_need_init[0] = kzalloc(sizeof(bool) *
1183
+						  MAX_QOS_REGS_NUM *
1184
+						  pd->num_qos,
1185
+						  GFP_KERNEL);
1186
+		if (!pd->qos_is_need_init[0]) {
8231187 			error = -ENOMEM;
8241188 			goto err_unprepare_clocks;
8251189 		}
8261190 		for (i = 1; i < MAX_QOS_REGS_NUM; i++) {
8271191 			pd->qos_save_regs[i] = pd->qos_save_regs[i - 1] +
8281192 					       num_qos;
829
-			qos_is_need_init[i] = qos_is_need_init[i - 1] + num_qos;
1193
+			pd->qos_is_need_init[i] = pd->qos_is_need_init[i - 1] +
1194
+						  num_qos;
8301195 		}
8311196 
8321197 		for (j = 0; j < num_qos; j++) {
....@@ -847,71 +1212,72 @@
8471212 							  "priority-init",
8481213 							  &val)) {
8491214 					pd->qos_save_regs[0][j] = val;
850
-					qos_is_need_init[0][j] = true;
851
-					is_qos_need_init = true;
1215
+					pd->qos_is_need_init[0][j] = true;
1216
+					pd->is_qos_need_init = true;
8521217 				}
8531218 
8541219 				if (!of_property_read_u32(qos_node,
8551220 							  "mode-init",
8561221 							  &val)) {
8571222 					pd->qos_save_regs[1][j] = val;
858
-					qos_is_need_init[1][j] = true;
859
-					is_qos_need_init = true;
1223
+					pd->qos_is_need_init[1][j] = true;
1224
+					pd->is_qos_need_init = true;
8601225 				}
8611226 
8621227 				if (!of_property_read_u32(qos_node,
8631228 							  "bandwidth-init",
8641229 							  &val)) {
8651230 					pd->qos_save_regs[2][j] = val;
866
-					qos_is_need_init[2][j] = true;
867
-					is_qos_need_init = true;
1231
+					pd->qos_is_need_init[2][j] = true;
1232
+					pd->is_qos_need_init = true;
8681233 				}
8691234 
8701235 				if (!of_property_read_u32(qos_node,
8711236 							  "saturation-init",
8721237 							  &val)) {
8731238 					pd->qos_save_regs[3][j] = val;
874
-					qos_is_need_init[3][j] = true;
875
-					is_qos_need_init = true;
1239
+					pd->qos_is_need_init[3][j] = true;
1240
+					pd->is_qos_need_init = true;
8761241 				}
8771242 
8781243 				if (!of_property_read_u32(qos_node,
8791244 							  "extcontrol-init",
8801245 							  &val)) {
8811246 					pd->qos_save_regs[4][j] = val;
882
-					qos_is_need_init[4][j] = true;
883
-					is_qos_need_init = true;
1247
+					pd->qos_is_need_init[4][j] = true;
1248
+					pd->is_qos_need_init = true;
8841249 				}
8851250 
8861251 				num_qos_reg++;
8871252 			}
8881253 			of_node_put(qos_node);
889
-			if (num_qos_reg > pd->num_qos)
1254
+			if (num_qos_reg > pd->num_qos) {
1255
+				error = -EINVAL;
8901256 				goto err_unprepare_clocks;
1257
+			}
8911258 		}
8921259 	}
8931260 
894
-	pd->genpd.name = node->name;
1261
+	error = rockchip_pd_of_get_shaping(pd, node);
1262
+	if (error)
1263
+		goto err_unprepare_clocks;
1264
+
1265
+	if (pd->info->name)
1266
+		pd->genpd.name = pd->info->name;
1267
+	else
1268
+		pd->genpd.name = kbasename(node->full_name);
8951269 	pd->genpd.power_off = rockchip_pd_power_off;
8961270 	pd->genpd.power_on = rockchip_pd_power_on;
8971271 	pd->genpd.attach_dev = rockchip_pd_attach_dev;
8981272 	pd->genpd.detach_dev = rockchip_pd_detach_dev;
8991273 	if (pd_info->active_wakeup)
9001274 		pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
901
-	if (pd_info->always_on) {
902
-		if (rockchip_pd_add_alwasy_on_flag(pd))
1275
+	if (pd_info->always_on || pd_info->keepon_startup) {
1276
+		error = rockchip_pd_add_alwasy_on_flag(pd);
1277
+		if (error)
9031278 			goto err_unprepare_clocks;
9041279 	}
905
-#ifndef MODULE
906
-	if (pd_info->keepon_startup) {
907
-		if (rockchip_pd_add_alwasy_on_flag(pd))
908
-			goto err_unprepare_clocks;
909
-	}
910
-#endif
911
-	if (is_qos_need_init)
912
-		rockchip_pd_qos_init(pd, &qos_is_need_init[0]);
913
-
914
-	kfree(qos_is_need_init[0]);
1280
+	rockchip_pd_qos_init(pd);
9151281 
9161282 	pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
9171283 
....@@ -919,7 +1285,8 @@
9191285 	return 0;
9201286 
9211287 err_unprepare_clocks:
922
-	kfree(qos_is_need_init[0]);
1288
+	kfree(pd->qos_is_need_init[0]);
1289
+	pd->qos_is_need_init[0] = NULL;
9231290 	clk_bulk_unprepare(pd->num_clks, pd->clks);
9241291 err_put_clocks:
9251292 	clk_bulk_put(pd->num_clks, pd->clks);
....@@ -991,24 +1358,24 @@
9911358 		error = of_property_read_u32(parent, "reg", &idx);
9921359 		if (error) {
9931360 			dev_err(pmu->dev,
994
-				"%s: failed to retrieve domain id (reg): %d\n",
995
-				parent->name, error);
1361
+				"%pOFn: failed to retrieve domain id (reg): %d\n",
1362
+				parent, error);
9961363 			goto err_out;
9971364 		}
9981365 		parent_domain = pmu->genpd_data.domains[idx];
9991366 
10001367 		error = rockchip_pm_add_one_domain(pmu, np);
10011368 		if (error) {
1002
-			dev_err(pmu->dev, "failed to handle node %s: %d\n",
1003
-				np->name, error);
1369
+			dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
1370
+				np, error);
10041371 			goto err_out;
10051372 		}
10061373 
10071374 		error = of_property_read_u32(np, "reg", &idx);
10081375 		if (error) {
10091376 			dev_err(pmu->dev,
1010
-				"%s: failed to retrieve domain id (reg): %d\n",
1011
-				np->name, error);
1377
+				"%pOFn: failed to retrieve domain id (reg): %d\n",
1378
+				np, error);
10121379 			goto err_out;
10131380 		}
10141381 		child_domain = pmu->genpd_data.domains[idx];
....@@ -1044,37 +1411,15 @@
10441411 	return error;
10451412 }
10461413 
1047
-#ifndef MODULE
1048
-static void rockchip_pd_keepon_do_release(struct generic_pm_domain *genpd,
1049
-					  struct rockchip_pm_domain *pd)
1050
-{
1051
-	struct pm_domain_data *pm_data;
1052
-	int enable_count;
1053
-
1054
-	pd->genpd.flags &= (~GENPD_FLAG_ALWAYS_ON);
1055
-	list_for_each_entry(pm_data, &genpd->dev_list, list_node) {
1056
-		if (!atomic_read(&pm_data->dev->power.usage_count)) {
1057
-			enable_count = 0;
1058
-			if (!pm_runtime_enabled(pm_data->dev)) {
1059
-				pm_runtime_enable(pm_data->dev);
1060
-				enable_count = 1;
1061
-			}
1062
-			pm_runtime_get_sync(pm_data->dev);
1063
-			pm_runtime_put_sync(pm_data->dev);
1064
-			if (enable_count)
1065
-				pm_runtime_disable(pm_data->dev);
1066
-		}
1067
-	}
1068
-}
1069
-
1070
-static int __init rockchip_pd_keepon_release(void)
1414
+#ifdef MODULE
1415
+void rockchip_pd_disable_unused(void)
10711416 {
10721417 	struct generic_pm_domain *genpd;
10731418 	struct rockchip_pm_domain *pd;
10741419 	int i;
10751420 
10761421 	if (!g_pmu)
1077
-		return 0;
1422
+		return;
10781423 
10791424 	for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
10801425 		genpd = g_pmu->genpd_data.domains[i];
....@@ -1082,10 +1427,44 @@
10821427 			pd = to_rockchip_pd(genpd);
10831428 			if (pd->info->always_on)
10841429 				continue;
1085
-			if (pd->info->keepon_startup)
1086
-				rockchip_pd_keepon_do_release(genpd, pd);
1430
+			if (pd->info->keepon_startup &&
1431
+			    (genpd->flags & GENPD_FLAG_ALWAYS_ON))
1432
+				genpd->flags &= (~GENPD_FLAG_ALWAYS_ON);
1433
+			queue_work(pm_wq, &genpd->power_off_work);
10871434 		}
10881435 	}
1436
+}
1437
+EXPORT_SYMBOL_GPL(rockchip_pd_disable_unused);
1438
+#else
1439
+static void rockchip_pd_keepon_do_release(void)
1440
+{
1441
+	struct generic_pm_domain *genpd;
1442
+	struct rockchip_pm_domain *pd;
1443
+	int i;
1444
+
1445
+	if (!g_pmu)
1446
+		return;
1447
+
1448
+	for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
1449
+		genpd = g_pmu->genpd_data.domains[i];
1450
+		if (genpd) {
1451
+			pd = to_rockchip_pd(genpd);
1452
+			if (pd->info->always_on)
1453
+				continue;
1454
+			if (!pd->info->keepon_startup)
1455
+				continue;
1456
+			if (!(genpd->flags & GENPD_FLAG_ALWAYS_ON))
1457
+				continue;
1458
+			genpd->flags &= (~GENPD_FLAG_ALWAYS_ON);
1459
+			queue_work(pm_wq, &genpd->power_off_work);
1460
+		}
1461
+	}
1462
+}
1463
+
1464
+static int __init rockchip_pd_keepon_release(void)
1465
+{
1466
+	rockchip_pd_keepon_do_release();
1467
+
10891468 	return 0;
10901469 }
10911470 late_initcall_sync(rockchip_pd_keepon_release);
....@@ -1093,14 +1472,32 @@
10931472 
10941473 static void __iomem *pd_base;
10951474 
1475
+static void dump_offset(const char *name, u32 offset)
1476
+{
1477
+	if (!offset)
1478
+		return;
1479
+
1480
+	pr_warn("%-9s 0x%04x: ", name, offset);
1481
+	print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 4, pd_base + offset, 16, false);
1482
+}
1483
+
10961484 void rockchip_dump_pmu(void)
10971485 {
1098
-	if (pd_base) {
1099
-		pr_warn("PMU:\n");
1100
-		print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1101
-			       32, 4, pd_base,
1102
-			       0x100, false);
1103
-	}
1486
+	if (!pd_base)
1487
+		return;
1488
+
1489
+	pr_warn("PMU:\n");
1490
+	dump_offset("pwr", g_pmu->info->pwr_offset);
1491
+	dump_offset("status", g_pmu->info->status_offset);
1492
+	dump_offset("req", g_pmu->info->req_offset);
1493
+	dump_offset("idle", g_pmu->info->idle_offset);
1494
+	dump_offset("ack", g_pmu->info->ack_offset);
1495
+	dump_offset("mem_pwr", g_pmu->info->mem_pwr_offset);
1496
+	dump_offset("chain_st", g_pmu->info->chain_status_offset);
1497
+	dump_offset("mem_st", g_pmu->info->mem_status_offset);
1498
+	dump_offset("repair_st", g_pmu->info->repair_status_offset);
1499
+	dump_offset("clkungate", g_pmu->info->clk_ungate_offset);
1500
+	dump_offset("mem_sd", g_pmu->info->mem_sd_offset);
11041501 }
11051502 EXPORT_SYMBOL_GPL(rockchip_dump_pmu);
11061503 
....@@ -1190,16 +1587,16 @@
11901587 	for_each_available_child_of_node(np, node) {
11911588 		error = rockchip_pm_add_one_domain(pmu, node);
11921589 		if (error) {
1193
-			dev_err(dev, "failed to handle node %s: %d\n",
1194
-				node->name, error);
1590
+			dev_err(dev, "failed to handle node %pOFn: %d\n",
1591
+				node, error);
11951592 			of_node_put(node);
11961593 			goto err_out;
11971594 		}
11981595 
11991596 		error = rockchip_pm_add_subdomain(pmu, node);
12001597 		if (error < 0) {
1201
-			dev_err(dev, "failed to handle subdomain node %s: %d\n",
1202
-				node->name, error);
1598
+			dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
1599
+				node, error);
12031600 			of_node_put(node);
12041601 			goto err_out;
12051602 		}
....@@ -1228,145 +1625,217 @@
12281625 }
12291626 
12301627 static const struct rockchip_domain_info px30_pm_domains[] = {
1231
-	[PX30_PD_USB]		= DOMAIN_PX30(BIT(5),  BIT(5),  BIT(10), true),
1232
-	[PX30_PD_SDCARD]	= DOMAIN_PX30(BIT(8),  BIT(8),  BIT(9),  false),
1233
-	[PX30_PD_GMAC]		= DOMAIN_PX30(BIT(10), BIT(10), BIT(6),  false),
1234
-	[PX30_PD_MMC_NAND]	= DOMAIN_PX30(BIT(11), BIT(11), BIT(5),  false),
1235
-	[PX30_PD_VPU]		= DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false),
1236
-	[PX30_PD_VO]		= DOMAIN_PX30_PROTECT(BIT(13), BIT(13), BIT(7),  false),
1237
-	[PX30_PD_VI]		= DOMAIN_PX30_PROTECT(BIT(14), BIT(14), BIT(8),  false),
1238
-	[PX30_PD_GPU]		= DOMAIN_PX30(BIT(15), BIT(15), BIT(2),  false),
1628
+	[PX30_PD_USB]		= DOMAIN_PX30("usb",        BIT(5),  BIT(5),  BIT(10), true),
1629
+	[PX30_PD_SDCARD]	= DOMAIN_PX30("sdcard",     BIT(8),  BIT(8),  BIT(9),  false),
1630
+	[PX30_PD_GMAC]		= DOMAIN_PX30("gmac",       BIT(10), BIT(10), BIT(6),  false),
1631
+	[PX30_PD_MMC_NAND]	= DOMAIN_PX30("mmc_nand",   BIT(11), BIT(11), BIT(5),  false),
1632
+	[PX30_PD_VPU]		= DOMAIN_PX30("vpu",        BIT(12), BIT(12), BIT(14), false),
1633
+	[PX30_PD_VO]		= DOMAIN_PX30_PROTECT("vo", BIT(13), BIT(13), BIT(7),  false),
1634
+	[PX30_PD_VI]		= DOMAIN_PX30_PROTECT("vi", BIT(14), BIT(14), BIT(8),  false),
1635
+	[PX30_PD_GPU]		= DOMAIN_PX30("gpu",        BIT(15), BIT(15), BIT(2),  false),
12391636 };
12401637 
12411638 static const struct rockchip_domain_info rv1126_pm_domains[] = {
1242
-	[RV1126_PD_CRYPTO]	= DOMAIN_RV1126_O(BIT(10), BIT(4), BIT(20), 0x4, false),
1243
-	[RV1126_PD_VEPU]	= DOMAIN_RV1126(BIT(2),  BIT(9),  BIT(9), false),
1244
-	[RV1126_PD_VI]		= DOMAIN_RV1126(BIT(4),  BIT(6),  BIT(6),  false),
1245
-	[RV1126_PD_VO]		= DOMAIN_RV1126_PROTECT(BIT(5), BIT(7), BIT(7),  false),
1246
-	[RV1126_PD_ISPP]	= DOMAIN_RV1126(BIT(1), BIT(8), BIT(8),  false),
1247
-	[RV1126_PD_VDPU]	= DOMAIN_RV1126(BIT(3), BIT(10), BIT(10), false),
1248
-	[RV1126_PD_NVM]		= DOMAIN_RV1126(BIT(7), BIT(11), BIT(11),  false),
1249
-	[RV1126_PD_SDIO]	= DOMAIN_RV1126(BIT(8), BIT(13), BIT(13),  false),
1250
-	[RV1126_PD_USB]		= DOMAIN_RV1126(BIT(9), BIT(15), BIT(15),  true),
1251
-	[RV1126_PD_NPU]		= DOMAIN_RV1126_O(BIT(0), BIT(2), BIT(18), 0x4, false),
1639
+	[RV1126_PD_CRYPTO]	= DOMAIN_RV1126_O("crypto",   BIT(10), BIT(4),  BIT(20), 0x4, false),
1640
+	[RV1126_PD_VEPU]	= DOMAIN_RV1126("vepu",       BIT(2),  BIT(9),  BIT(9),  false),
1641
+	[RV1126_PD_VI]		= DOMAIN_RV1126("vi",         BIT(4),  BIT(6),  BIT(6),  false),
1642
+	[RV1126_PD_VO]		= DOMAIN_RV1126_PROTECT("vo", BIT(5),  BIT(7),  BIT(7),  false),
1643
+	[RV1126_PD_ISPP]	= DOMAIN_RV1126("ispp",       BIT(1),  BIT(8),  BIT(8),  false),
1644
+	[RV1126_PD_VDPU]	= DOMAIN_RV1126("vdpu",       BIT(3),  BIT(10), BIT(10), false),
1645
+	[RV1126_PD_NVM]		= DOMAIN_RV1126("nvm",        BIT(7),  BIT(11), BIT(11), false),
1646
+	[RV1126_PD_SDIO]	= DOMAIN_RV1126("sdio",       BIT(8),  BIT(13), BIT(13), false),
1647
+	[RV1126_PD_USB]		= DOMAIN_RV1126("usb",        BIT(9),  BIT(15), BIT(15), true),
1648
+	[RV1126_PD_NPU]		= DOMAIN_RV1126_O("npu",      BIT(0),  BIT(2),  BIT(18), 0x4, false),
12521649 };
12531650 
12541651 static const struct rockchip_domain_info rk1808_pm_domains[] = {
1255
-	[RK1808_VD_NPU]		= DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false),
1256
-	[RK1808_PD_PCIE]	= DOMAIN_PX30(BIT(9),  BIT(9),  BIT(4), true),
1257
-	[RK1808_PD_VPU]		= DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false),
1258
-	[RK1808_PD_VIO]		= DOMAIN_PX30_PROTECT(BIT(14), BIT(14), BIT(8), false),
1652
+	[RK1808_VD_NPU]		= DOMAIN_PX30("npu",         BIT(15), BIT(15), BIT(2), false),
1653
+	[RK1808_PD_PCIE]	= DOMAIN_PX30("pcie",        BIT(9),  BIT(9),  BIT(4), true),
1654
+	[RK1808_PD_VPU]		= DOMAIN_PX30("vpu",         BIT(13), BIT(13), BIT(7), false),
1655
+	[RK1808_PD_VIO]		= DOMAIN_PX30_PROTECT("vio", BIT(14), BIT(14), BIT(8), false),
12591656 };
12601657 
12611658 static const struct rockchip_domain_info rk3036_pm_domains[] = {
1262
-	[RK3036_PD_MSCH]	= DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true),
1263
-	[RK3036_PD_CORE]	= DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false),
1264
-	[RK3036_PD_PERI]	= DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false),
1265
-	[RK3036_PD_VIO]		= DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false),
1266
-	[RK3036_PD_VPU]		= DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false),
1267
-	[RK3036_PD_GPU]		= DOMAIN_RK3036(BIT(9),  BIT(21), BIT(28), false),
1268
-	[RK3036_PD_SYS]		= DOMAIN_RK3036(BIT(8),  BIT(22), BIT(29), false),
1659
+	[RK3036_PD_MSCH]	= DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
1660
+	[RK3036_PD_CORE]	= DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
1661
+	[RK3036_PD_PERI]	= DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
1662
+	[RK3036_PD_VIO]		= DOMAIN_RK3036("vio",  BIT(11), BIT(19), BIT(26), false),
1663
+	[RK3036_PD_VPU]		= DOMAIN_RK3036("vpu",  BIT(10), BIT(20), BIT(27), false),
1664
+	[RK3036_PD_GPU]		= DOMAIN_RK3036("gpu",  BIT(9),  BIT(21), BIT(28), false),
1665
+	[RK3036_PD_SYS]		= DOMAIN_RK3036("sys",  BIT(8),  BIT(22), BIT(29), false),
1666
+};
1667
+
1668
+static const struct rockchip_domain_info rk3066_pm_domains[] = {
1669
+	[RK3066_PD_GPU]		= DOMAIN("gpu",   BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false, false),
1670
+	[RK3066_PD_VIDEO]	= DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false, false),
1671
+	[RK3066_PD_VIO]		= DOMAIN("vio",   BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false, true),
1672
+	[RK3066_PD_PERI]	= DOMAIN("peri",  BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false, false),
1673
+	[RK3066_PD_CPU]		= DOMAIN("cpu",   0,      BIT(5), BIT(1), BIT(26), BIT(31), false, false),
12691674 };
12701675 
12711676 static const struct rockchip_domain_info rk3128_pm_domains[] = {
1272
-	[RK3128_PD_CORE]	= DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false),
1273
-	[RK3128_PD_MSCH]	= DOMAIN_RK3288(0,      0,      BIT(6), true),
1274
-	[RK3128_PD_VIO]		= DOMAIN_RK3288_PROTECT(BIT(3), BIT(3), BIT(2), false),
1275
-	[RK3128_PD_VIDEO]	= DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false),
1276
-	[RK3128_PD_GPU]		= DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false),
1677
+	[RK3128_PD_CORE]        = DOMAIN_RK3288("core",        BIT(0), BIT(0), BIT(4), false),
1678
+	[RK3128_PD_MSCH]        = DOMAIN_RK3288("msch",        0,      0,      BIT(6), true),
1679
+	[RK3128_PD_VIO]         = DOMAIN_RK3288_PROTECT("vio", BIT(3), BIT(3), BIT(2), false),
1680
+	[RK3128_PD_VIDEO]       = DOMAIN_RK3288("video",       BIT(2), BIT(2), BIT(1), false),
1681
+	[RK3128_PD_GPU]         = DOMAIN_RK3288("gpu",         BIT(1), BIT(1), BIT(3), false),
1682
+};
1683
+
1684
+static const struct rockchip_domain_info rk3188_pm_domains[] = {
1685
+	[RK3188_PD_GPU]         = DOMAIN("gpu",   BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false, false),
1686
+	[RK3188_PD_VIDEO]	= DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false, false),
1687
+	[RK3188_PD_VIO]		= DOMAIN("vio",   BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false, true),
1688
+	[RK3188_PD_PERI]	= DOMAIN("peri",  BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false, false),
1689
+	[RK3188_PD_CPU]		= DOMAIN("cpu",   BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false, false),
12771690 };
12781691 
12791692 static const struct rockchip_domain_info rk3228_pm_domains[] = {
1280
-	[RK3228_PD_CORE]	= DOMAIN_RK3036(BIT(0),  BIT(0),  BIT(16), true),
1281
-	[RK3228_PD_MSCH]	= DOMAIN_RK3036(BIT(1),  BIT(1),  BIT(17), true),
1282
-	[RK3228_PD_BUS]		= DOMAIN_RK3036(BIT(2),  BIT(2),  BIT(18), true),
1283
-	[RK3228_PD_SYS]		= DOMAIN_RK3036(BIT(3),  BIT(3),  BIT(19), true),
1284
-	[RK3228_PD_VIO]		= DOMAIN_RK3036(BIT(4),  BIT(4),  BIT(20), false),
1285
-	[RK3228_PD_VOP]		= DOMAIN_RK3036(BIT(5),  BIT(5),  BIT(21), false),
1286
-	[RK3228_PD_VPU]		= DOMAIN_RK3036(BIT(6),  BIT(6),  BIT(22), false),
1287
-	[RK3228_PD_RKVDEC]	= DOMAIN_RK3036(BIT(7),  BIT(7),  BIT(23), false),
1288
-	[RK3228_PD_GPU]		= DOMAIN_RK3036(BIT(8),  BIT(8),  BIT(24), false),
1289
-	[RK3228_PD_PERI]	= DOMAIN_RK3036(BIT(9),  BIT(9),  BIT(25), true),
1290
-	[RK3228_PD_GMAC]	= DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false),
1693
+	[RK3228_PD_CORE]	= DOMAIN_RK3036("core", BIT(0),  BIT(0),  BIT(16), true),
1694
+	[RK3228_PD_MSCH]	= DOMAIN_RK3036("msch", BIT(1),  BIT(1),  BIT(17), true),
1695
+	[RK3228_PD_BUS]		= DOMAIN_RK3036("bus",  BIT(2),  BIT(2),  BIT(18), true),
1696
+	[RK3228_PD_SYS]		= DOMAIN_RK3036("sys",  BIT(3),  BIT(3),  BIT(19), true),
1697
+	[RK3228_PD_VIO]		= DOMAIN_RK3036("vio",  BIT(4),  BIT(4),  BIT(20), false),
1698
+	[RK3228_PD_VOP]		= DOMAIN_RK3036("vop",  BIT(5),  BIT(5),  BIT(21), false),
1699
+	[RK3228_PD_VPU]		= DOMAIN_RK3036("vpu",  BIT(6),  BIT(6),  BIT(22), false),
1700
+	[RK3228_PD_RKVDEC]	= DOMAIN_RK3036("vdec", BIT(7),  BIT(7),  BIT(23), false),
1701
+	[RK3228_PD_GPU]		= DOMAIN_RK3036("gpu",  BIT(8),  BIT(8),  BIT(24), false),
1702
+	[RK3228_PD_PERI]	= DOMAIN_RK3036("peri", BIT(9),  BIT(9),  BIT(25), true),
1703
+	[RK3228_PD_GMAC]	= DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
12911704 };
12921705 
12931706 static const struct rockchip_domain_info rk3288_pm_domains[] = {
1294
-	[RK3288_PD_VIO]		= DOMAIN_RK3288_PROTECT(BIT(7),  BIT(7),  BIT(4), false),
1295
-	[RK3288_PD_HEVC]	= DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false),
1296
-	[RK3288_PD_VIDEO]	= DOMAIN_RK3288(BIT(8),  BIT(8),  BIT(3), false),
1297
-	[RK3288_PD_GPU]		= DOMAIN_RK3288(BIT(9),  BIT(9),  BIT(2), false),
1707
+	[RK3288_PD_VIO]		= DOMAIN_RK3288_PROTECT("vio", BIT(7),  BIT(7),  BIT(4), false),
1708
+	[RK3288_PD_HEVC]	= DOMAIN_RK3288("hevc",        BIT(14), BIT(10), BIT(9), false),
1709
+	[RK3288_PD_VIDEO]	= DOMAIN_RK3288("video",       BIT(8),  BIT(8),  BIT(3), false),
1710
+	[RK3288_PD_GPU]		= DOMAIN_RK3288("gpu",         BIT(9),  BIT(9),  BIT(2), false),
12981711 };
12991712 
13001713 static const struct rockchip_domain_info rk3328_pm_domains[] = {
1301
-	[RK3328_PD_CORE]	= DOMAIN_RK3328(0, BIT(0), BIT(0), false),
1302
-	[RK3328_PD_GPU]		= DOMAIN_RK3328(0, BIT(1), BIT(1), false),
1303
-	[RK3328_PD_BUS]		= DOMAIN_RK3328(0, BIT(2), BIT(2), true),
1304
-	[RK3328_PD_MSCH]	= DOMAIN_RK3328(0, BIT(3), BIT(3), true),
1305
-	[RK3328_PD_PERI]	= DOMAIN_RK3328(0, BIT(4), BIT(4), true),
1306
-	[RK3328_PD_VIDEO]	= DOMAIN_RK3328(0, BIT(5), BIT(5), false),
1307
-	[RK3328_PD_HEVC]	= DOMAIN_RK3328(0, BIT(6), BIT(6), false),
1308
-	[RK3328_PD_VIO]		= DOMAIN_RK3328(0, BIT(8), BIT(8), false),
1309
-	[RK3328_PD_VPU]		= DOMAIN_RK3328(0, BIT(9), BIT(9), false),
1714
+	[RK3328_PD_CORE]	= DOMAIN_RK3328("core",  0, BIT(0), BIT(0), false),
1715
+	[RK3328_PD_GPU]		= DOMAIN_RK3328("gpu",   0, BIT(1), BIT(1), false),
1716
+	[RK3328_PD_BUS]		= DOMAIN_RK3328("bus",   0, BIT(2), BIT(2), true),
1717
+	[RK3328_PD_MSCH]	= DOMAIN_RK3328("msch",  0, BIT(3), BIT(3), true),
1718
+	[RK3328_PD_PERI]	= DOMAIN_RK3328("peri",  0, BIT(4), BIT(4), true),
1719
+	[RK3328_PD_VIDEO]	= DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1720
+	[RK3328_PD_HEVC]	= DOMAIN_RK3328("hevc",  0, BIT(6), BIT(6), false),
1721
+	[RK3328_PD_VIO]		= DOMAIN_RK3328("vio",   0, BIT(8), BIT(8), false),
1722
+	[RK3328_PD_VPU]		= DOMAIN_RK3328("vpu",   0, BIT(9), BIT(9), false),
13101723 };
13111724 
13121725 static const struct rockchip_domain_info rk3366_pm_domains[] = {
1313
-	[RK3366_PD_PERI]	= DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true),
1314
-	[RK3366_PD_VIO]		= DOMAIN_RK3368_PROTECT(BIT(14), BIT(14), BIT(8), false),
1315
-	[RK3366_PD_VIDEO]	= DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false),
1316
-	[RK3366_PD_RKVDEC]	= DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false),
1317
-	[RK3366_PD_WIFIBT]	= DOMAIN_RK3368(BIT(8),  BIT(8),  BIT(9), false),
1318
-	[RK3366_PD_VPU]		= DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false),
1319
-	[RK3366_PD_GPU]		= DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false),
1726
+	[RK3366_PD_PERI]	= DOMAIN_RK3368("peri",        BIT(10), BIT(10), BIT(6), true),
1727
+	[RK3366_PD_VIO]		= DOMAIN_RK3368_PROTECT("vio", BIT(14), BIT(14), BIT(8), false),
1728
+	[RK3366_PD_VIDEO]	= DOMAIN_RK3368("video",       BIT(13), BIT(13), BIT(7), false),
1729
+	[RK3366_PD_RKVDEC]	= DOMAIN_RK3368("rkvdec",      BIT(11), BIT(11), BIT(7), false),
1730
+	[RK3366_PD_WIFIBT]	= DOMAIN_RK3368("wifibt",      BIT(8),  BIT(8),  BIT(9), false),
1731
+	[RK3366_PD_VPU]		= DOMAIN_RK3368("vpu",         BIT(12), BIT(12), BIT(7), false),
1732
+	[RK3366_PD_GPU]		= DOMAIN_RK3368("gpu",         BIT(15), BIT(15), BIT(2), false),
13201733 };
13211734 
13221735 static const struct rockchip_domain_info rk3368_pm_domains[] = {
1323
-	[RK3368_PD_PERI]	= DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true),
1324
-	[RK3368_PD_VIO]		= DOMAIN_RK3368_PROTECT(BIT(15), BIT(14), BIT(8), false),
1325
-	[RK3368_PD_VIDEO]	= DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false),
1326
-	[RK3368_PD_GPU_0]	= DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false),
1327
-	[RK3368_PD_GPU_1]	= DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false),
1736
+	[RK3368_PD_PERI]	= DOMAIN_RK3368("peri",        BIT(13), BIT(12), BIT(6), true),
1737
+	[RK3368_PD_VIO]		= DOMAIN_RK3368_PROTECT("vio", BIT(15), BIT(14), BIT(8), false),
1738
+	[RK3368_PD_VIDEO]	= DOMAIN_RK3368("video",       BIT(14), BIT(13), BIT(7), false),
1739
+	[RK3368_PD_GPU_0]	= DOMAIN_RK3368("gpu_0",       BIT(16), BIT(15), BIT(2), false),
1740
+	[RK3368_PD_GPU_1]	= DOMAIN_RK3368("gpu_1",       BIT(17), BIT(16), BIT(2), false),
13281741 };
13291742 
13301743 static const struct rockchip_domain_info rk3399_pm_domains[] = {
1331
-	[RK3399_PD_TCPD0]	= DOMAIN_RK3399(BIT(8),  BIT(8),  0,	   false),
1332
-	[RK3399_PD_TCPD1]	= DOMAIN_RK3399(BIT(9),  BIT(9),  0,	   false),
1333
-	[RK3399_PD_CCI]		= DOMAIN_RK3399(BIT(10), BIT(10), 0,	   true),
1334
-	[RK3399_PD_CCI0]	= DOMAIN_RK3399(0,	 0,	  BIT(15), true),
1335
-	[RK3399_PD_CCI1]	= DOMAIN_RK3399(0,	 0,	  BIT(16), true),
1336
-	[RK3399_PD_PERILP]	= DOMAIN_RK3399(BIT(11), BIT(11), BIT(1),  true),
1337
-	[RK3399_PD_PERIHP]	= DOMAIN_RK3399(BIT(12), BIT(12), BIT(2),  true),
1338
-	[RK3399_PD_CENTER]	= DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true),
1339
-	[RK3399_PD_VIO]		= DOMAIN_RK3399_PROTECT(BIT(14), BIT(14), BIT(17), false),
1340
-	[RK3399_PD_GPU]		= DOMAIN_RK3399(BIT(15), BIT(15), BIT(0),  false),
1341
-	[RK3399_PD_VCODEC]	= DOMAIN_RK3399(BIT(16), BIT(16), BIT(3),  false),
1342
-	[RK3399_PD_VDU]		= DOMAIN_RK3399(BIT(17), BIT(17), BIT(4),  false),
1343
-	[RK3399_PD_RGA]		= DOMAIN_RK3399(BIT(18), BIT(18), BIT(5),  false),
1344
-	[RK3399_PD_IEP]		= DOMAIN_RK3399(BIT(19), BIT(19), BIT(6),  false),
1345
-	[RK3399_PD_VO]		= DOMAIN_RK3399_PROTECT(BIT(20), BIT(20), 0,	   false),
1346
-	[RK3399_PD_VOPB]	= DOMAIN_RK3399_PROTECT(0,	 0,	  BIT(7),  false),
1347
-	[RK3399_PD_VOPL]	= DOMAIN_RK3399_PROTECT(0, 	 0,	  BIT(8),  false),
1348
-	[RK3399_PD_ISP0]	= DOMAIN_RK3399(BIT(22), BIT(22), BIT(9),  false),
1349
-	[RK3399_PD_ISP1]	= DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false),
1350
-	[RK3399_PD_HDCP]	= DOMAIN_RK3399_PROTECT(BIT(24), BIT(24), BIT(11), false),
1351
-	[RK3399_PD_GMAC]	= DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true),
1352
-	[RK3399_PD_EMMC]	= DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true),
1353
-	[RK3399_PD_USB3]	= DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true),
1354
-	[RK3399_PD_EDP]		= DOMAIN_RK3399_PROTECT(BIT(28), BIT(28), BIT(22), false),
1355
-	[RK3399_PD_GIC]		= DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true),
1356
-	[RK3399_PD_SD]		= DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true),
1357
-	[RK3399_PD_SDIOAUDIO]	= DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true),
1744
+	[RK3399_PD_TCPD0]	= DOMAIN_RK3399("tcpd0",        BIT(8),  BIT(8),  0,       false),
1745
+	[RK3399_PD_TCPD1]	= DOMAIN_RK3399("tcpd1",        BIT(9),  BIT(9),  0,       false),
1746
+	[RK3399_PD_CCI]		= DOMAIN_RK3399("cci",          BIT(10), BIT(10), 0,       true),
1747
+	[RK3399_PD_CCI0]	= DOMAIN_RK3399("cci0",         0,       0,       BIT(15), true),
1748
+	[RK3399_PD_CCI1]	= DOMAIN_RK3399("cci1",         0,       0,       BIT(16), true),
1749
+	[RK3399_PD_PERILP]	= DOMAIN_RK3399("perilp",       BIT(11), BIT(11), BIT(1),  true),
1750
+	[RK3399_PD_PERIHP]	= DOMAIN_RK3399("perihp",       BIT(12), BIT(12), BIT(2),  true),
1751
+	[RK3399_PD_CENTER]	= DOMAIN_RK3399("center",       BIT(13), BIT(13), BIT(14), true),
1752
+	[RK3399_PD_VIO]		= DOMAIN_RK3399_PROTECT("vio",  BIT(14), BIT(14), BIT(17), false),
1753
+	[RK3399_PD_GPU]		= DOMAIN_RK3399("gpu",          BIT(15), BIT(15), BIT(0),  false),
1754
+	[RK3399_PD_VCODEC]	= DOMAIN_RK3399("vcodec",       BIT(16), BIT(16), BIT(3),  false),
1755
+	[RK3399_PD_VDU]		= DOMAIN_RK3399("vdu",          BIT(17), BIT(17), BIT(4),  false),
1756
+	[RK3399_PD_RGA]		= DOMAIN_RK3399("rga",          BIT(18), BIT(18), BIT(5),  false),
1757
+	[RK3399_PD_IEP]		= DOMAIN_RK3399("iep",          BIT(19), BIT(19), BIT(6),  false),
1758
+	[RK3399_PD_VO]		= DOMAIN_RK3399_PROTECT("vo",   BIT(20), BIT(20), 0,       false),
1759
+	[RK3399_PD_VOPB]	= DOMAIN_RK3399_PROTECT("vopb", 0,       0,       BIT(7),  false),
1760
+	[RK3399_PD_VOPL]	= DOMAIN_RK3399_PROTECT("vopl", 0,       0,       BIT(8),  false),
1761
+	[RK3399_PD_ISP0]	= DOMAIN_RK3399("isp0",         BIT(22), BIT(22), BIT(9),  false),
1762
+	[RK3399_PD_ISP1]	= DOMAIN_RK3399("isp1",         BIT(23), BIT(23), BIT(10), false),
1763
+	[RK3399_PD_HDCP]	= DOMAIN_RK3399_PROTECT("hdcp", BIT(24), BIT(24), BIT(11), false),
1764
+	[RK3399_PD_GMAC]	= DOMAIN_RK3399("gmac",         BIT(25), BIT(25), BIT(23), true),
1765
+	[RK3399_PD_EMMC]	= DOMAIN_RK3399("emmc",         BIT(26), BIT(26), BIT(24), true),
1766
+	[RK3399_PD_USB3]	= DOMAIN_RK3399("usb3",         BIT(27), BIT(27), BIT(12), true),
1767
+	[RK3399_PD_EDP]		= DOMAIN_RK3399_PROTECT("edp",  BIT(28), BIT(28), BIT(22), false),
1768
+	[RK3399_PD_GIC]		= DOMAIN_RK3399("gic",          BIT(29), BIT(29), BIT(27), true),
1769
+	[RK3399_PD_SD]		= DOMAIN_RK3399("sd",           BIT(30), BIT(30), BIT(28), true),
1770
+	[RK3399_PD_SDIOAUDIO]	= DOMAIN_RK3399("sdioaudio",    BIT(31), BIT(31), BIT(29), true),
1771
+};
1772
+
1773
+static const struct rockchip_domain_info rk3528_pm_domains[] = {
1774
+	[RK3528_PD_PMU]		= DOMAIN_RK3528(0, BIT(0), true, false),
1775
+	[RK3528_PD_BUS]		= DOMAIN_RK3528(0, BIT(1), true, false),
1776
+	[RK3528_PD_DDR]		= DOMAIN_RK3528(0, BIT(2), true, false),
1777
+	[RK3528_PD_MSCH]	= DOMAIN_RK3528(0, BIT(3), true, false),
1778
+	[RK3528_PD_GPU]		= DOMAIN_RK3528(BIT(0), BIT(4), true, false),
1779
+	[RK3528_PD_RKVDEC]	= DOMAIN_RK3528(0, BIT(5), true, false),
1780
+	[RK3528_PD_RKVENC]	= DOMAIN_RK3528(0, BIT(6), true, false),
1781
+	[RK3528_PD_VO]		= DOMAIN_RK3528(0,  BIT(7), true, false),
1782
+	[RK3528_PD_VPU]		= DOMAIN_RK3528(0, BIT(8), true, false),
1783
+};
1784
+
1785
+static const struct rockchip_domain_info rk3562_pm_domains[] = {
1786
+	[RK3562_PD_GPU]		= DOMAIN_RK3562("gpu",         BIT(0), BIT(1), 0, false),
1787
+	[RK3562_PD_NPU]		= DOMAIN_RK3562("npu",         BIT(1), BIT(2), 0, false),
1788
+	[RK3562_PD_VDPU]	= DOMAIN_RK3562("vdpu",        BIT(2), BIT(6), 0, false),
1789
+	[RK3562_PD_VEPU]	= DOMAIN_RK3562("vepu",        BIT(3), BIT(7), 0, false),
1790
+	[RK3562_PD_RGA]		= DOMAIN_RK3562("rga",         BIT(4), BIT(5), 0, false),
1791
+	[RK3562_PD_VI]		= DOMAIN_RK3562("vi",          BIT(5), BIT(3), 0, false),
1792
+	[RK3562_PD_VO]		= DOMAIN_RK3562_PROTECT("vo",  BIT(6), BIT(4), 16, false),
1793
+	[RK3562_PD_PHP]		= DOMAIN_RK3562("php",         BIT(7), BIT(8), 0, false),
13581794 };
13591795 
13601796 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1361
-	[RK3568_PD_NPU]		= DOMAIN_RK3568(BIT(1), BIT(2), false),
1362
-	[RK3568_PD_GPU]		= DOMAIN_RK3568(BIT(0), BIT(1), false),
1363
-	[RK3568_PD_VI]		= DOMAIN_RK3568(BIT(6), BIT(3), false),
1364
-	[RK3568_PD_VO]		= DOMAIN_RK3568_PROTECT(BIT(7),  BIT(4), false),
1365
-	[RK3568_PD_RGA]		= DOMAIN_RK3568(BIT(5),  BIT(5), false),
1366
-	[RK3568_PD_VPU]		= DOMAIN_RK3568(BIT(2), BIT(6), false),
1367
-	[RK3568_PD_RKVDEC]	= DOMAIN_RK3568(BIT(4), BIT(8), false),
1368
-	[RK3568_PD_RKVENC]	= DOMAIN_RK3568(BIT(3), BIT(7), false),
1369
-	[RK3568_PD_PIPE]	= DOMAIN_RK3568(BIT(8), BIT(11), false),
1797
+	[RK3568_PD_NPU]		= DOMAIN_RK3568("npu",        BIT(1), BIT(2),  false),
1798
+	[RK3568_PD_GPU]		= DOMAIN_RK3568("gpu",        BIT(0), BIT(1),  false),
1799
+	[RK3568_PD_VI]		= DOMAIN_RK3568("vi",         BIT(6), BIT(3),  false),
1800
+	[RK3568_PD_VO]		= DOMAIN_RK3568_PROTECT("vo", BIT(7), BIT(4),  false),
1801
+	[RK3568_PD_RGA]		= DOMAIN_RK3568("rga",        BIT(5), BIT(5),  false),
1802
+	[RK3568_PD_VPU]		= DOMAIN_RK3568("vpu",        BIT(2), BIT(6),  false),
1803
+	[RK3568_PD_RKVDEC]	= DOMAIN_RK3568("rkvdec",     BIT(4), BIT(8),  false),
1804
+	[RK3568_PD_RKVENC]	= DOMAIN_RK3568("rkvenc",     BIT(3), BIT(7),  false),
1805
+	[RK3568_PD_PIPE]	= DOMAIN_RK3568("pipe",       BIT(8), BIT(11), false),
1806
+};
1807
+
1808
+static const struct rockchip_domain_info rk3588_pm_domains[] = {
1809
+					     /* name   p_offset pwr   status  m_offset m_status r_status r_offset req  idle     wakeup */
1810
+	[RK3588_PD_GPU]		= DOMAIN_RK3588("gpu",     0x0, BIT(0),  0,       0x0, 0,       BIT(1),  0x0, BIT(0),  BIT(0),  false),
1811
+	[RK3588_PD_NPU]		= DOMAIN_RK3588("npu",     0x0, BIT(1),  BIT(1),  0x0, 0,       0,       0x0, 0,       0,       false),
1812
+	[RK3588_PD_VCODEC]	= DOMAIN_RK3588("vcodec",  0x0, BIT(2),  BIT(2),  0x0, 0,       0,       0x0, 0,       0,       false),
1813
+	[RK3588_PD_NPUTOP]	= DOMAIN_RK3588("nputop",  0x0, BIT(3),  0,       0x0, BIT(11), BIT(2),  0x0, BIT(1),  BIT(1),  false),
1814
+	[RK3588_PD_NPU1]	= DOMAIN_RK3588("npu1",    0x0, BIT(4),  0,       0x0, BIT(12), BIT(3),  0x0, BIT(2),  BIT(2),  false),
1815
+	[RK3588_PD_NPU2]	= DOMAIN_RK3588("npu2",    0x0, BIT(5),  0,       0x0, BIT(13), BIT(4),  0x0, BIT(3),  BIT(3),  false),
1816
+	[RK3588_PD_VENC0]	= DOMAIN_RK3588("venc0",   0x0, BIT(6),  0,       0x0, BIT(14), BIT(5),  0x0, BIT(4),  BIT(4),  false),
1817
+	[RK3588_PD_VENC1]	= DOMAIN_RK3588("venc1",   0x0, BIT(7),  0,       0x0, BIT(15), BIT(6),  0x0, BIT(5),  BIT(5),  false),
1818
+	[RK3588_PD_RKVDEC0]	= DOMAIN_RK3588("rkvdec0", 0x0, BIT(8),  0,       0x0, BIT(16), BIT(7),  0x0, BIT(6),  BIT(6),  false),
1819
+	[RK3588_PD_RKVDEC1]	= DOMAIN_RK3588("rkvdec1", 0x0, BIT(9),  0,       0x0, BIT(17), BIT(8),  0x0, BIT(7),  BIT(7),  false),
1820
+	[RK3588_PD_VDPU]	= DOMAIN_RK3588("vdpu",    0x0, BIT(10), 0,       0x0, BIT(18), BIT(9),  0x0, BIT(8),  BIT(8),  false),
1821
+	[RK3588_PD_RGA30]	= DOMAIN_RK3588("rga30",   0x0, BIT(11), 0,       0x0, BIT(19), BIT(10), 0x0, 0,       0,       false),
1822
+	[RK3588_PD_AV1]		= DOMAIN_RK3588("av1",     0x0, BIT(12), 0,       0x0, BIT(20), BIT(11), 0x0, BIT(9),  BIT(9),  false),
1823
+	[RK3588_PD_VI]		= DOMAIN_RK3588("vi",      0x0, BIT(13), 0,       0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
1824
+	[RK3588_PD_FEC]		= DOMAIN_RK3588("fec",     0x0, BIT(14), 0,       0x0, BIT(22), BIT(13), 0x0, 0,       0,       false),
1825
+	[RK3588_PD_ISP1]	= DOMAIN_RK3588("isp1",    0x0, BIT(15), 0,       0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
1826
+	[RK3588_PD_RGA31]	= DOMAIN_RK3588("rga31",   0x4, BIT(0),  0,       0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
1827
+	[RK3588_PD_VOP]		= DOMAIN_RK3588_P("vop",   0x4, BIT(1),  0,       0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
1828
+	[RK3588_PD_VO0]		= DOMAIN_RK3588_P("vo0",   0x4, BIT(2),  0,       0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
1829
+	[RK3588_PD_VO1]		= DOMAIN_RK3588_P("vo1",   0x4, BIT(3),  0,       0x0, BIT(27), BIT(18), 0x4, BIT(0),  BIT(16), false),
1830
+	[RK3588_PD_AUDIO]	= DOMAIN_RK3588("audio",   0x4, BIT(4),  0,       0x0, BIT(28), BIT(19), 0x4, BIT(1),  BIT(17), false),
1831
+	[RK3588_PD_PHP]		= DOMAIN_RK3588("php",     0x4, BIT(5),  0,       0x0, BIT(29), BIT(20), 0x4, BIT(5),  BIT(21), false),
1832
+	[RK3588_PD_GMAC]	= DOMAIN_RK3588("gmac",    0x4, BIT(6),  0,       0x0, BIT(30), BIT(21), 0x0, 0,       0,       false),
1833
+	[RK3588_PD_PCIE]	= DOMAIN_RK3588("pcie",    0x4, BIT(7),  0,       0x0, BIT(31), BIT(22), 0x0, 0,       0,       true),
1834
+	[RK3588_PD_NVM]		= DOMAIN_RK3588("nvm",     0x4, BIT(8),  BIT(24), 0x4, 0,       0,       0x4, BIT(2),  BIT(18), false),
1835
+	[RK3588_PD_NVM0]	= DOMAIN_RK3588("nvm0",    0x4, BIT(9),  0,       0x4, BIT(1),  BIT(23), 0x0, 0,       0,       false),
1836
+	[RK3588_PD_SDIO]	= DOMAIN_RK3588("sdio",    0x4, BIT(10), 0,       0x4, BIT(2),  BIT(24), 0x4, BIT(3),  BIT(19), false),
1837
+	[RK3588_PD_USB]		= DOMAIN_RK3588("usb",     0x4, BIT(11), 0,       0x4, BIT(3),  BIT(25), 0x4, BIT(4),  BIT(20), true),
1838
+	[RK3588_PD_SDMMC]	= DOMAIN_RK3588("sdmmc",   0x4, BIT(13), 0,       0x4, BIT(5),  BIT(26), 0x0, 0,       0,       false),
13701839 };
13711840 
13721841 static const struct rockchip_pmu_info px30_pmu = {
....@@ -1378,17 +1847,6 @@
13781847 
13791848 	.num_domains = ARRAY_SIZE(px30_pm_domains),
13801849 	.domain_info = px30_pm_domains,
1381
-};
1382
-
1383
-static const struct rockchip_pmu_info rv1126_pmu = {
1384
-	.pwr_offset = 0x110,
1385
-	.status_offset = 0x108,
1386
-	.req_offset = 0xc0,
1387
-	.idle_offset = 0xd8,
1388
-	.ack_offset = 0xd0,
1389
-
1390
-	.num_domains = ARRAY_SIZE(rv1126_pm_domains),
1391
-	.domain_info = rv1126_pm_domains,
13921850 };
13931851 
13941852 static const struct rockchip_pmu_info rk1808_pmu = {
....@@ -1411,6 +1869,17 @@
14111869 	.domain_info = rk3036_pm_domains,
14121870 };
14131871 
1872
+static const struct rockchip_pmu_info rk3066_pmu = {
1873
+	.pwr_offset = 0x08,
1874
+	.status_offset = 0x0c,
1875
+	.req_offset = 0x38, /* PMU_MISC_CON1 */
1876
+	.idle_offset = 0x0c,
1877
+	.ack_offset = 0x0c,
1878
+
1879
+	.num_domains = ARRAY_SIZE(rk3066_pm_domains),
1880
+	.domain_info = rk3066_pm_domains,
1881
+};
1882
+
14141883 static const struct rockchip_pmu_info rk3128_pmu = {
14151884 	.pwr_offset = 0x04,
14161885 	.status_offset = 0x08,
....@@ -1420,6 +1889,17 @@
14201889 
14211890 	.num_domains = ARRAY_SIZE(rk3128_pm_domains),
14221891 	.domain_info = rk3128_pm_domains,
1892
+};
1893
+
1894
+static const struct rockchip_pmu_info rk3188_pmu = {
1895
+	.pwr_offset = 0x08,
1896
+	.status_offset = 0x0c,
1897
+	.req_offset = 0x38, /* PMU_MISC_CON1 */
1898
+	.idle_offset = 0x0c,
1899
+	.ack_offset = 0x0c,
1900
+
1901
+	.num_domains = ARRAY_SIZE(rk3188_pm_domains),
1902
+	.domain_info = rk3188_pm_domains,
14231903 };
14241904 
14251905 static const struct rockchip_pmu_info rk3228_pmu = {
....@@ -1498,14 +1978,34 @@
14981978 	.idle_offset = 0x64,
14991979 	.ack_offset = 0x68,
15001980 
1501
-	.core_pwrcnt_offset = 0xac,
1502
-	.gpu_pwrcnt_offset = 0xac,
1503
-
1504
-	.core_power_transition_time = 6, /* 0.25us */
1505
-	.gpu_power_transition_time = 6, /* 0.25us */
1981
+	/* ARM Trusted Firmware manages power transition times */
15061982 
15071983 	.num_domains = ARRAY_SIZE(rk3399_pm_domains),
15081984 	.domain_info = rk3399_pm_domains,
1985
+};
1986
+
1987
+static const struct rockchip_pmu_info rk3528_pmu = {
1988
+	.pwr_offset = 0x1210,
1989
+	.status_offset = 0x1230,
1990
+	.req_offset = 0x1110,
1991
+	.idle_offset = 0x1128,
1992
+	.ack_offset = 0x1120,
1993
+
1994
+	.num_domains = ARRAY_SIZE(rk3528_pm_domains),
1995
+	.domain_info = rk3528_pm_domains,
1996
+};
1997
+
1998
+static const struct rockchip_pmu_info rk3562_pmu = {
1999
+	.pwr_offset = 0x210,
2000
+	.status_offset = 0x230,
2001
+	.req_offset = 0x110,
2002
+	.idle_offset = 0x128,
2003
+	.ack_offset = 0x120,
2004
+	.clk_ungate_offset = 0x140,
2005
+	.mem_sd_offset = 0x300,
2006
+
2007
+	.num_domains = ARRAY_SIZE(rk3562_pm_domains),
2008
+	.domain_info = rk3562_pm_domains,
15092009 };
15102010 
15112011 static const struct rockchip_pmu_info rk3568_pmu = {
....@@ -1519,79 +2019,103 @@
15192019 	.domain_info = rk3568_pm_domains,
15202020 };
15212021 
2022
+static const struct rockchip_pmu_info rk3588_pmu = {
2023
+	.pwr_offset = 0x14c,
2024
+	.status_offset = 0x180,
2025
+	.req_offset = 0x10c,
2026
+	.idle_offset = 0x120,
2027
+	.ack_offset = 0x118,
2028
+	.mem_pwr_offset = 0x1a0,
2029
+	.chain_status_offset = 0x1f0,
2030
+	.mem_status_offset = 0x1f8,
2031
+	.repair_status_offset = 0x290,
2032
+
2033
+	.num_domains = ARRAY_SIZE(rk3588_pm_domains),
2034
+	.domain_info = rk3588_pm_domains,
2035
+};
2036
+
2037
+static const struct rockchip_pmu_info rv1126_pmu = {
2038
+	.pwr_offset = 0x110,
2039
+	.status_offset = 0x108,
2040
+	.req_offset = 0xc0,
2041
+	.idle_offset = 0xd8,
2042
+	.ack_offset = 0xd0,
2043
+
2044
+	.num_domains = ARRAY_SIZE(rv1126_pm_domains),
2045
+	.domain_info = rv1126_pm_domains,
2046
+};
2047
+
15222048 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1523
-#ifdef CONFIG_CPU_PX30
15242049 	{
15252050 		.compatible = "rockchip,px30-power-controller",
15262051 		.data = (void *)&px30_pmu,
15272052 	},
1528
-#endif
1529
-#ifdef CONFIG_CPU_RV1126
1530
-	{
1531
-		.compatible = "rockchip,rv1126-power-controller",
1532
-		.data = (void *)&rv1126_pmu,
1533
-	},
1534
-#endif
1535
-#ifdef CONFIG_CPU_RK1808
15362053 	{
15372054 		.compatible = "rockchip,rk1808-power-controller",
15382055 		.data = (void *)&rk1808_pmu,
15392056 	},
1540
-#endif
1541
-#ifdef CONFIG_CPU_RK3036
15422057 	{
15432058 		.compatible = "rockchip,rk3036-power-controller",
15442059 		.data = (void *)&rk3036_pmu,
15452060 	},
1546
-#endif
1547
-#ifdef CONFIG_CPU_RK312X
2061
+	{
2062
+		.compatible = "rockchip,rk3066-power-controller",
2063
+		.data = (void *)&rk3066_pmu,
2064
+	},
15482065 	{
15492066 		.compatible = "rockchip,rk3128-power-controller",
15502067 		.data = (void *)&rk3128_pmu,
15512068 	},
1552
-#endif
1553
-#ifdef CONFIG_CPU_RK322X
2069
+	{
2070
+		.compatible = "rockchip,rk3188-power-controller",
2071
+		.data = (void *)&rk3188_pmu,
2072
+	},
15542073 	{
15552074 		.compatible = "rockchip,rk3228-power-controller",
15562075 		.data = (void *)&rk3228_pmu,
15572076 	},
1558
-#endif
1559
-#ifdef CONFIG_CPU_RK3288
15602077 	{
15612078 		.compatible = "rockchip,rk3288-power-controller",
15622079 		.data = (void *)&rk3288_pmu,
15632080 	},
1564
-#endif
1565
-#ifdef CONFIG_CPU_RK3328
15662081 	{
15672082 		.compatible = "rockchip,rk3328-power-controller",
15682083 		.data = (void *)&rk3328_pmu,
15692084 	},
1570
-#endif
1571
-#ifdef CONFIG_CPU_RK3366
15722085 	{
15732086 		.compatible = "rockchip,rk3366-power-controller",
15742087 		.data = (void *)&rk3366_pmu,
15752088 	},
1576
-#endif
1577
-#ifdef CONFIG_CPU_RK3368
15782089 	{
15792090 		.compatible = "rockchip,rk3368-power-controller",
15802091 		.data = (void *)&rk3368_pmu,
15812092 	},
1582
-#endif
1583
-#ifdef CONFIG_CPU_RK3399
15842093 	{
15852094 		.compatible = "rockchip,rk3399-power-controller",
15862095 		.data = (void *)&rk3399_pmu,
15872096 	},
2097
+#ifdef CONFIG_CPU_RK3528
2098
+	{
2099
+		.compatible = "rockchip,rk3528-power-controller",
2100
+		.data = (void *)&rk3528_pmu,
2101
+	},
15882102 #endif
1589
-#ifdef CONFIG_CPU_RK3568
2103
+	{
2104
+		.compatible = "rockchip,rk3562-power-controller",
2105
+		.data = (void *)&rk3562_pmu,
2106
+	},
15902107 	{
15912108 		.compatible = "rockchip,rk3568-power-controller",
15922109 		.data = (void *)&rk3568_pmu,
15932110 	},
1594
-#endif
2111
+	{
2112
+		.compatible = "rockchip,rk3588-power-controller",
2113
+		.data = (void *)&rk3588_pmu,
2114
+	},
2115
+	{
2116
+		.compatible = "rockchip,rv1126-power-controller",
2117
+		.data = (void *)&rv1126_pmu,
2118
+	},
15952119 	{ /* sentinel */ },
15962120 };
15972121 MODULE_DEVICE_TABLE(of, rockchip_pm_domain_dt_match);
....@@ -1624,4 +2148,3 @@
16242148 
16252149 MODULE_DESCRIPTION("ROCKCHIP PM Domain Driver");
16262150 MODULE_LICENSE("GPL");
1627
-MODULE_ALIAS("platform:rockchip-pm-domain");