add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/soc/bcm/brcmstb/pm/pm-arm.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  * ARM-specific support for Broadcom STB S2/S3/S5 power management
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  *
..
..
@@ -8,15 +9,6 @@
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  *     treat this mode like a soft power-off, with wakeup allowed from AON
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  *
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  * Copyright © 2014-2017 Broadcom
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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12
  */
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13
 
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 #define pr_fmt(fmt) "brcmstb-pm: " fmt
..
..
@@ -689,13 +681,14 @@
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 	const struct of_device_id *of_id = NULL;
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 	struct device_node *dn;
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 	void __iomem *base;
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-	int ret, i;
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+	int ret, i, s;
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685
 
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 	/* AON ctrl registers */
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 	base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL);
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 	if (IS_ERR(base)) {
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 		pr_err("error mapping AON_CTRL\n");
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-		return PTR_ERR(base);
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+		ret = PTR_ERR(base);
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+		goto aon_err;
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 	}
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 	ctrl.aon_ctrl_base = base;
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694
 
..
..
@@ -705,8 +698,10 @@
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 		/* Assume standard offset */
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 		ctrl.aon_sram = ctrl.aon_ctrl_base +
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 				     AON_CTRL_SYSTEM_DATA_RAM_OFS;
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+		s = 0;
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 	} else {
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 		ctrl.aon_sram = base;
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+		s = 1;
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 	}
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706
 
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 	writel_relaxed(0, ctrl.aon_sram + AON_REG_PANIC);
..
..
@@ -716,7 +711,8 @@
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 				     (const void **)&ddr_phy_data);
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 	if (IS_ERR(base)) {
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 		pr_err("error mapping DDR PHY\n");
719
-		return PTR_ERR(base);
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+		ret = PTR_ERR(base);
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+		goto ddr_phy_err;
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 	}
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 	ctrl.support_warm_boot = ddr_phy_data->supports_warm_boot;
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 	ctrl.pll_status_offset = ddr_phy_data->pll_status_offset;
..
..
@@ -736,17 +732,20 @@
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 	for_each_matching_node(dn, ddr_shimphy_dt_ids) {
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733
 		i = ctrl.num_memc;
738
734
 		if (i >= MAX_NUM_MEMC) {
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+			of_node_put(dn);
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 			pr_warn("too many MEMCs (max %d)\n", MAX_NUM_MEMC);
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737
 			break;
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 		}
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739
 
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 		base = of_io_request_and_map(dn, 0, dn->full_name);
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741
 		if (IS_ERR(base)) {
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+			of_node_put(dn);
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743
 			if (!ctrl.support_warm_boot)
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 				break;
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 			pr_err("error mapping DDR SHIMPHY %d\n", i);
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-			return PTR_ERR(base);
747
+			ret = PTR_ERR(base);
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+			goto ddr_shimphy_err;
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749
 		}
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 		ctrl.memcs[i].ddr_shimphy_base = base;
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 		ctrl.num_memc++;
..
..
@@ -757,14 +756,18 @@
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 	for_each_matching_node(dn, brcmstb_memc_of_match) {
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 		base = of_iomap(dn, 0);
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 		if (!base) {
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+			of_node_put(dn);
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 			pr_err("error mapping DDR Sequencer %d\n", i);
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-			return -ENOMEM;
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+			ret = -ENOMEM;
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+			goto brcmstb_memc_err;
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 		}
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764
 
764
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 		of_id = of_match_node(brcmstb_memc_of_match, dn);
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 		if (!of_id) {
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 			iounmap(base);
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-			return -EINVAL;
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+			of_node_put(dn);
769
+			ret = -EINVAL;
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+			goto brcmstb_memc_err;
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 		}
769
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 		ddr_seq_data = of_id->data;
..
..
@@ -784,20 +787,24 @@
784
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 	dn = of_find_matching_node(NULL, sram_dt_ids);
785
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 	if (!dn) {
786
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 		pr_err("SRAM not found\n");
787
-		return -EINVAL;
790
+		ret = -EINVAL;
791
+		goto brcmstb_memc_err;
788
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 	}
789
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790
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 	ret = brcmstb_init_sram(dn);
795
+	of_node_put(dn);
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 	if (ret) {
792
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 		pr_err("error setting up SRAM for PM\n");
793
-		return ret;
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+		goto brcmstb_memc_err;
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799
 	}
795
800
 
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 	ctrl.pdev = pdev;
797
802
 
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 	ctrl.s3_params = kmalloc(sizeof(*ctrl.s3_params), GFP_KERNEL);
799
-	if (!ctrl.s3_params)
800
-		return -ENOMEM;
804
+	if (!ctrl.s3_params) {
805
+		ret = -ENOMEM;
806
+		goto s3_params_err;
807
+	}
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 	ctrl.s3_params_pa = dma_map_single(&pdev->dev, ctrl.s3_params,
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809
 					   sizeof(*ctrl.s3_params),
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 					   DMA_TO_DEVICE);
..
..
@@ -817,7 +824,21 @@
817
824
 
818
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 out:
819
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 	kfree(ctrl.s3_params);
827
+s3_params_err:
828
+	iounmap(ctrl.boot_sram);
829
+brcmstb_memc_err:
830
+	for (i--; i >= 0; i--)
831
+		iounmap(ctrl.memcs[i].ddr_ctrl);
832
+ddr_shimphy_err:
833
+	for (i = 0; i < ctrl.num_memc; i++)
834
+		iounmap(ctrl.memcs[i].ddr_shimphy_base);
820
835
 
836
+	iounmap(ctrl.memcs[0].ddr_phy_base);
837
+ddr_phy_err:
838
+	iounmap(ctrl.aon_ctrl_base);
839
+	if (s)
840
+		iounmap(ctrl.aon_sram);
841
+aon_err:
821
842
 	pr_warn("PM: initialization failed with code %d\n", ret);
822
843
 
823
844
 	return ret;