.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
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1 | 2 | /* |
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2 | 3 | * driver for Microsemi PQI-based storage controllers |
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3 | | - * Copyright (c) 2016-2017 Microsemi Corporation |
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| 4 | + * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries |
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| 5 | + * Copyright (c) 2016-2018 Microsemi Corporation |
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4 | 6 | * Copyright (c) 2016 PMC-Sierra, Inc. |
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5 | 7 | * |
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6 | | - * This program is free software; you can redistribute it and/or modify |
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7 | | - * it under the terms of the GNU General Public License as published by |
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8 | | - * the Free Software Foundation; version 2 of the License. |
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9 | | - * |
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10 | | - * This program is distributed in the hope that it will be useful, |
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11 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | | - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
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13 | | - * NON INFRINGEMENT. See the GNU General Public License for more details. |
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14 | | - * |
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15 | | - * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com |
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| 8 | + * Questions/Comments/Bugfixes to storagedev@microchip.com |
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16 | 9 | * |
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17 | 10 | */ |
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18 | 11 | |
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.. | .. |
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34 | 27 | #define SIS_REENABLE_SIS_MODE 0x1 |
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35 | 28 | #define SIS_ENABLE_MSIX 0x40 |
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36 | 29 | #define SIS_ENABLE_INTX 0x80 |
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| 30 | +#define SIS_SOFT_RESET 0x100 |
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37 | 31 | #define SIS_CMD_READY 0x200 |
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38 | 32 | #define SIS_TRIGGER_SHUTDOWN 0x800000 |
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39 | 33 | #define SIS_PQI_RESET_QUIESCE 0x1000000 |
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.. | .. |
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90 | 84 | unsigned long timeout; |
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91 | 85 | u32 status; |
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92 | 86 | |
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93 | | - timeout = (timeout_secs * HZ) + jiffies; |
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| 87 | + timeout = (timeout_secs * PQI_HZ) + jiffies; |
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94 | 88 | |
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95 | 89 | while (1) { |
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96 | 90 | status = readl(&ctrl_info->registers->sis_firmware_status); |
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.. | .. |
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202 | 196 | * the top of the loop in order to give the controller time to start |
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203 | 197 | * processing the command before we start polling. |
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204 | 198 | */ |
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205 | | - timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * HZ) + jiffies; |
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| 199 | + timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * PQI_HZ) + jiffies; |
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206 | 200 | while (1) { |
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207 | 201 | msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS); |
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208 | 202 | doorbell = readl(®isters->sis_ctrl_to_host_doorbell); |
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.. | .. |
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316 | 310 | put_unaligned_le32(ctrl_info->max_io_slots, |
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317 | 311 | &base_struct->error_buffer_num_elements); |
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318 | 312 | |
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319 | | - bus_address = pci_map_single(ctrl_info->pci_dev, base_struct, |
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320 | | - sizeof(*base_struct), PCI_DMA_TODEVICE); |
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321 | | - if (pci_dma_mapping_error(ctrl_info->pci_dev, bus_address)) { |
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| 313 | + bus_address = dma_map_single(&ctrl_info->pci_dev->dev, base_struct, |
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| 314 | + sizeof(*base_struct), DMA_TO_DEVICE); |
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| 315 | + if (dma_mapping_error(&ctrl_info->pci_dev->dev, bus_address)) { |
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322 | 316 | rc = -ENOMEM; |
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323 | 317 | goto out; |
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324 | 318 | } |
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.. | .. |
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331 | 325 | rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS, |
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332 | 326 | ¶ms); |
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333 | 327 | |
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334 | | - pci_unmap_single(ctrl_info->pci_dev, bus_address, sizeof(*base_struct), |
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335 | | - PCI_DMA_TODEVICE); |
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336 | | - |
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| 328 | + dma_unmap_single(&ctrl_info->pci_dev->dev, bus_address, |
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| 329 | + sizeof(*base_struct), DMA_TO_DEVICE); |
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337 | 330 | out: |
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338 | 331 | kfree(base_struct_unaligned); |
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339 | 332 | |
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.. | .. |
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349 | 342 | u32 doorbell_register; |
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350 | 343 | unsigned long timeout; |
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351 | 344 | |
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352 | | - timeout = (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS * HZ) + jiffies; |
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| 345 | + timeout = (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS * PQI_HZ) + jiffies; |
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353 | 346 | |
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354 | 347 | while (1) { |
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355 | 348 | doorbell_register = |
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.. | .. |
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421 | 414 | return readl(&ctrl_info->registers->sis_driver_scratch); |
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422 | 415 | } |
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423 | 416 | |
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| 417 | +void sis_soft_reset(struct pqi_ctrl_info *ctrl_info) |
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| 418 | +{ |
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| 419 | + writel(SIS_SOFT_RESET, |
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| 420 | + &ctrl_info->registers->sis_host_to_ctrl_doorbell); |
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| 421 | +} |
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| 422 | + |
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424 | 423 | static void __attribute__((unused)) verify_structures(void) |
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425 | 424 | { |
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426 | 425 | BUILD_BUG_ON(offsetof(struct sis_base_struct, |
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