~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,8 +1,7 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* QLogic Fibre Channel HBA Driver
3	4	* Copyright (c) 2003-2014 QLogic Corporation
4		- *
5		- * See LICENSE.qla2xxx for copyright and licensing details.
6	5	*/
7	6	#ifndef __QLA_DEF_H
8	7	#define __QLA_DEF_H
..	..	@@ -34,7 +33,24 @@
34	33	#include <scsi/scsi_transport_fc.h>
35	34	#include <scsi/scsi_bsg_fc.h>
36	35
	36	+#include <uapi/scsi/fc/fc_els.h>
	37	+
	38	+/* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
	39	+typedef struct {
	40	+ uint8_t domain;
	41	+ uint8_t area;
	42	+ uint8_t al_pa;
	43	+} be_id_t;
	44	+
	45	+/* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
	46	+typedef struct {
	47	+ uint8_t al_pa;
	48	+ uint8_t area;
	49	+ uint8_t domain;
	50	+} le_id_t;
	51	+
37	52	#include "qla_bsg.h"
	53	+#include "qla_dsd.h"
38	54	#include "qla_nx.h"
39	55	#include "qla_nx2.h"
40	56	#include "qla_nvme.h"
..	..	@@ -104,21 +120,59 @@
104	120	#define LSD(x) ((uint32_t)((uint64_t)(x)))
105	121	#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
106	122
107		-#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) \| (uint32_t)(y)))
	123	+static inline uint32_t make_handle(uint16_t x, uint16_t y)
	124	+{
	125	+ return ((uint32_t)x << 16) \| y;
	126	+}
108	127
109	128	/*
110	129	* I/O register
111	130	*/
112	131
113		-#define RD_REG_BYTE(addr) readb(addr)
114		-#define RD_REG_WORD(addr) readw(addr)
115		-#define RD_REG_DWORD(addr) readl(addr)
116		-#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
117		-#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
118		-#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
119		-#define WRT_REG_BYTE(addr, data) writeb(data,addr)
120		-#define WRT_REG_WORD(addr, data) writew(data,addr)
121		-#define WRT_REG_DWORD(addr, data) writel(data,addr)
	132	+static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
	133	+{
	134	+ return readb(addr);
	135	+}
	136	+
	137	+static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
	138	+{
	139	+ return readw(addr);
	140	+}
	141	+
	142	+static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
	143	+{
	144	+ return readl(addr);
	145	+}
	146	+
	147	+static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
	148	+{
	149	+ return readb_relaxed(addr);
	150	+}
	151	+
	152	+static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
	153	+{
	154	+ return readw_relaxed(addr);
	155	+}
	156	+
	157	+static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
	158	+{
	159	+ return readl_relaxed(addr);
	160	+}
	161	+
	162	+static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
	163	+{
	164	+ return writeb(data, addr);
	165	+}
	166	+
	167	+static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
	168	+{
	169	+ return writew(data, addr);
	170	+}
	171	+
	172	+static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
	173	+{
	174	+ return writel(data, addr);
	175	+}
122	176
123	177	/*
124	178	* ISP83XX specific remote register addresses
..	..	@@ -206,7 +260,7 @@
206	260	* 133Mhz slot.
207	261	*/
208	262	#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
209		-#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
	263	+#define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
210	264
211	265	/*
212	266	* Fibre Channel device definitions.
..	..	@@ -302,7 +356,8 @@
302	356	uint32_t request_sense_length;
303	357	uint32_t fw_sense_length;
304	358	uint8_t *request_sense_ptr;
305		- void *ctx;
	359	+ struct ct6_dsd *ct6_ctx;
	360	+ struct crc_context *crc_ctx;
306	361	};
307	362
308	363	/*
..	..	@@ -314,6 +369,7 @@
314	369	#define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
315	370	#define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
316	371	#define SRB_WAKEUP_ON_COMP BIT_6
	372	+#define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
317	373
318	374	/* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
319	375	#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
..	..	@@ -340,6 +396,52 @@
340	396	} b;
341	397	} port_id_t;
342	398	#define INVALID_PORT_ID 0xFFFFFF
	399	+#define ISP_REG16_DISCONNECT 0xFFFF
	400	+
	401	+static inline le_id_t be_id_to_le(be_id_t id)
	402	+{
	403	+ le_id_t res;
	404	+
	405	+ res.domain = id.domain;
	406	+ res.area = id.area;
	407	+ res.al_pa = id.al_pa;
	408	+
	409	+ return res;
	410	+}
	411	+
	412	+static inline be_id_t le_id_to_be(le_id_t id)
	413	+{
	414	+ be_id_t res;
	415	+
	416	+ res.domain = id.domain;
	417	+ res.area = id.area;
	418	+ res.al_pa = id.al_pa;
	419	+
	420	+ return res;
	421	+}
	422	+
	423	+static inline port_id_t be_to_port_id(be_id_t id)
	424	+{
	425	+ port_id_t res;
	426	+
	427	+ res.b.domain = id.domain;
	428	+ res.b.area = id.area;
	429	+ res.b.al_pa = id.al_pa;
	430	+ res.b.rsvd_1 = 0;
	431	+
	432	+ return res;
	433	+}
	434	+
	435	+static inline be_id_t port_id_to_be_id(port_id_t port_id)
	436	+{
	437	+ be_id_t res;
	438	+
	439	+ res.domain = port_id.b.domain;
	440	+ res.area = port_id.b.area;
	441	+ res.al_pa = port_id.b.al_pa;
	442	+
	443	+ return res;
	444	+}
343	445
344	446	struct els_logo_payload {
345	447	uint8_t opcode;
..	..	@@ -352,7 +454,7 @@
352	454	struct els_plogi_payload {
353	455	uint8_t opcode;
354	456	uint8_t rsvd[3];
355		- uint8_t data[112];
	457	+ __be32 data[112 / 4];
356	458	};
357	459
358	460	struct ct_arg {
..	..	@@ -393,7 +495,7 @@
393	495	struct els_logo_payload *els_logo_pyld;
394	496	dma_addr_t els_logo_pyld_dma;
395	497	} els_logo;
396		- struct {
	498	+ struct els_plogi {
397	499	#define ELS_DCMD_PLOGI 0x3
398	500	uint32_t flags;
399	501	uint32_t els_cmd;
..	..	@@ -404,7 +506,7 @@
404	506	u32 rx_size;
405	507	dma_addr_t els_plogi_pyld_dma;
406	508	dma_addr_t els_resp_pyld_dma;
407		- uint32_t fw_status[3];
	509	+ __le32 fw_status[3];
408	510	__le16 comp_status;
409	511	__le16 len;
410	512	} els_plogi;
..	..	@@ -455,8 +557,8 @@
455	557	#define MAX_IOCB_MB_REG 28
456	558	#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
457	559	struct {
458		- __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
459		- __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
	560	+ u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
	561	+ u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
460	562	void out, in;
461	563	dma_addr_t out_dma, in_dma;
462	564	struct completion comp;
..	..	@@ -467,7 +569,7 @@
467	569	} nack;
468	570	struct {
469	571	__le16 comp_status;
470		- uint16_t rsp_pyld_len;
	572	+ __le16 rsp_pyld_len;
471	573	uint8_t aen_op;
472	574	void *desc;
473	575
..	..	@@ -519,6 +621,13 @@
519	621	enum {
520	622	TYPE_SRB,
521	623	TYPE_TGT_CMD,
	624	+ TYPE_TGT_TMCMD, /* task management */
	625	+};
	626	+
	627	+struct iocb_resource {
	628	+ u8 res_type;
	629	+ u8 pad;
	630	+ u16 iocb_cnt;
522	631	};
523	632
524	633	typedef struct srb {
..	..	@@ -528,34 +637,47 @@
528	637	*/
529	638	uint8_t cmd_type;
530	639	uint8_t pad[3];
531		- atomic_t ref_count;
532		- wait_queue_head_t nvme_ls_waitq;
	640	+ struct iocb_resource iores;
	641	+ struct kref cmd_kref; /* need to migrate ref_count over to this */
	642	+ void *priv;
533	643	struct fc_port *fcport;
534	644	struct scsi_qla_host *vha;
	645	+ unsigned int start_timer:1;
	646	+
535	647	uint32_t handle;
536	648	uint16_t flags;
537	649	uint16_t type;
538	650	const char *name;
539	651	int iocbs;
540	652	struct qla_qpair *qpair;
	653	+ struct srb *cmd_sp;
541	654	struct list_head elem;
542	655	u32 gen1; /* scratch */
543	656	u32 gen2; /* scratch */
544	657	int rc;
545	658	int retry_count;
546		- struct completion comp;
	659	+ struct completion *comp;
547	660	union {
548	661	struct srb_iocb iocb_cmd;
549	662	struct bsg_job *bsg_job;
550	663	struct srb_cmd scmd;
551	664	} u;
552		- void (done)(void , int);
553		- void (free)(void );
	665	+ /*
	666	+ * Report completion status @res and call sp_put(@sp). @res is
	667	+ * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a
	668	+ * QLA_* status value.
	669	+ */
	670	+ void (done)(struct srb sp, int res);
	671	+ /* Stop the timer and free @sp. Only used by the FCP code. */
	672	+ void (free)(struct srb sp);
	673	+ /*
	674	+ * Call nvme_private->fd->done() and free @sp. Only used by the NVMe
	675	+ * code.
	676	+ */
	677	+ void (put_fn)(struct kref kref);
554	678	} srb_t;
555	679
556	680	#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
557		-#define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
558		-#define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
559	681
560	682	#define GET_CMD_SENSE_LEN(sp) \
561	683	(sp->u.scmd.request_sense_length)
..	..	@@ -584,23 +706,23 @@
584	706	* ISP I/O Register Set structure definitions.
585	707	*/
586	708	struct device_reg_2xxx {
587		- uint16_t flash_address; /* Flash BIOS address */
588		- uint16_t flash_data; /* Flash BIOS data */
589		- uint16_t unused_1[1]; /* Gap */
590		- uint16_t ctrl_status; /* Control/Status */
	709	+ __le16 flash_address; /* Flash BIOS address */
	710	+ __le16 flash_data; /* Flash BIOS data */
	711	+ __le16 unused_1[1]; /* Gap */
	712	+ __le16 ctrl_status; /* Control/Status */
591	713	#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
592	714	#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
593	715	#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
594	716
595		- uint16_t ictrl; /* Interrupt control */
	717	+ __le16 ictrl; /* Interrupt control */
596	718	#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
597	719	#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
598	720
599		- uint16_t istatus; /* Interrupt status */
	721	+ __le16 istatus; /* Interrupt status */
600	722	#define ISR_RISC_INT BIT_3 /* RISC interrupt */
601	723
602		- uint16_t semaphore; /* Semaphore */
603		- uint16_t nvram; /* NVRAM register. */
	724	+ __le16 semaphore; /* Semaphore */
	725	+ __le16 nvram; /* NVRAM register. */
604	726	#define NVR_DESELECT 0
605	727	#define NVR_BUSY BIT_15
606	728	#define NVR_WRT_ENABLE BIT_14 /* Write enable */
..	..	@@ -614,80 +736,80 @@
614	736
615	737	union {
616	738	struct {
617		- uint16_t mailbox0;
618		- uint16_t mailbox1;
619		- uint16_t mailbox2;
620		- uint16_t mailbox3;
621		- uint16_t mailbox4;
622		- uint16_t mailbox5;
623		- uint16_t mailbox6;
624		- uint16_t mailbox7;
625		- uint16_t unused_2[59]; /* Gap */
	739	+ __le16 mailbox0;
	740	+ __le16 mailbox1;
	741	+ __le16 mailbox2;
	742	+ __le16 mailbox3;
	743	+ __le16 mailbox4;
	744	+ __le16 mailbox5;
	745	+ __le16 mailbox6;
	746	+ __le16 mailbox7;
	747	+ __le16 unused_2[59]; /* Gap */
626	748	} __attribute__((packed)) isp2100;
627	749	struct {
628	750	/* Request Queue */
629		- uint16_t req_q_in; /* In-Pointer */
630		- uint16_t req_q_out; /* Out-Pointer */
	751	+ __le16 req_q_in; /* In-Pointer */
	752	+ __le16 req_q_out; /* Out-Pointer */
631	753	/* Response Queue */
632		- uint16_t rsp_q_in; /* In-Pointer */
633		- uint16_t rsp_q_out; /* Out-Pointer */
	754	+ __le16 rsp_q_in; /* In-Pointer */
	755	+ __le16 rsp_q_out; /* Out-Pointer */
634	756
635	757	/* RISC to Host Status */
636		- uint32_t host_status;
	758	+ __le32 host_status;
637	759	#define HSR_RISC_INT BIT_15 /* RISC interrupt */
638	760	#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
639	761
640	762	/* Host to Host Semaphore */
641		- uint16_t host_semaphore;
642		- uint16_t unused_3[17]; /* Gap */
643		- uint16_t mailbox0;
644		- uint16_t mailbox1;
645		- uint16_t mailbox2;
646		- uint16_t mailbox3;
647		- uint16_t mailbox4;
648		- uint16_t mailbox5;
649		- uint16_t mailbox6;
650		- uint16_t mailbox7;
651		- uint16_t mailbox8;
652		- uint16_t mailbox9;
653		- uint16_t mailbox10;
654		- uint16_t mailbox11;
655		- uint16_t mailbox12;
656		- uint16_t mailbox13;
657		- uint16_t mailbox14;
658		- uint16_t mailbox15;
659		- uint16_t mailbox16;
660		- uint16_t mailbox17;
661		- uint16_t mailbox18;
662		- uint16_t mailbox19;
663		- uint16_t mailbox20;
664		- uint16_t mailbox21;
665		- uint16_t mailbox22;
666		- uint16_t mailbox23;
667		- uint16_t mailbox24;
668		- uint16_t mailbox25;
669		- uint16_t mailbox26;
670		- uint16_t mailbox27;
671		- uint16_t mailbox28;
672		- uint16_t mailbox29;
673		- uint16_t mailbox30;
674		- uint16_t mailbox31;
675		- uint16_t fb_cmd;
676		- uint16_t unused_4[10]; /* Gap */
	763	+ __le16 host_semaphore;
	764	+ __le16 unused_3[17]; /* Gap */
	765	+ __le16 mailbox0;
	766	+ __le16 mailbox1;
	767	+ __le16 mailbox2;
	768	+ __le16 mailbox3;
	769	+ __le16 mailbox4;
	770	+ __le16 mailbox5;
	771	+ __le16 mailbox6;
	772	+ __le16 mailbox7;
	773	+ __le16 mailbox8;
	774	+ __le16 mailbox9;
	775	+ __le16 mailbox10;
	776	+ __le16 mailbox11;
	777	+ __le16 mailbox12;
	778	+ __le16 mailbox13;
	779	+ __le16 mailbox14;
	780	+ __le16 mailbox15;
	781	+ __le16 mailbox16;
	782	+ __le16 mailbox17;
	783	+ __le16 mailbox18;
	784	+ __le16 mailbox19;
	785	+ __le16 mailbox20;
	786	+ __le16 mailbox21;
	787	+ __le16 mailbox22;
	788	+ __le16 mailbox23;
	789	+ __le16 mailbox24;
	790	+ __le16 mailbox25;
	791	+ __le16 mailbox26;
	792	+ __le16 mailbox27;
	793	+ __le16 mailbox28;
	794	+ __le16 mailbox29;
	795	+ __le16 mailbox30;
	796	+ __le16 mailbox31;
	797	+ __le16 fb_cmd;
	798	+ __le16 unused_4[10]; /* Gap */
677	799	} __attribute__((packed)) isp2300;
678	800	} u;
679	801
680		- uint16_t fpm_diag_config;
681		- uint16_t unused_5[0x4]; /* Gap */
682		- uint16_t risc_hw;
683		- uint16_t unused_5_1; /* Gap */
684		- uint16_t pcr; /* Processor Control Register. */
685		- uint16_t unused_6[0x5]; /* Gap */
686		- uint16_t mctr; /* Memory Configuration and Timing. */
687		- uint16_t unused_7[0x3]; /* Gap */
688		- uint16_t fb_cmd_2100; /* Unused on 23XX */
689		- uint16_t unused_8[0x3]; /* Gap */
690		- uint16_t hccr; /* Host command & control register. */
	802	+ __le16 fpm_diag_config;
	803	+ __le16 unused_5[0x4]; /* Gap */
	804	+ __le16 risc_hw;
	805	+ __le16 unused_5_1; /* Gap */
	806	+ __le16 pcr; /* Processor Control Register. */
	807	+ __le16 unused_6[0x5]; /* Gap */
	808	+ __le16 mctr; /* Memory Configuration and Timing. */
	809	+ __le16 unused_7[0x3]; /* Gap */
	810	+ __le16 fb_cmd_2100; /* Unused on 23XX */
	811	+ __le16 unused_8[0x3]; /* Gap */
	812	+ __le16 hccr; /* Host command & control register. */
691	813	#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
692	814	#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
693	815	/* HCCR commands */
..	..	@@ -700,9 +822,9 @@
700	822	#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
701	823	#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
702	824
703		- uint16_t unused_9[5]; /* Gap */
704		- uint16_t gpiod; /* GPIO Data register. */
705		- uint16_t gpioe; /* GPIO Enable register. */
	825	+ __le16 unused_9[5]; /* Gap */
	826	+ __le16 gpiod; /* GPIO Data register. */
	827	+ __le16 gpioe; /* GPIO Enable register. */
706	828	#define GPIO_LED_MASK 0x00C0
707	829	#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
708	830	#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
..	..	@@ -714,95 +836,95 @@
714	836
715	837	union {
716	838	struct {
717		- uint16_t unused_10[8]; /* Gap */
718		- uint16_t mailbox8;
719		- uint16_t mailbox9;
720		- uint16_t mailbox10;
721		- uint16_t mailbox11;
722		- uint16_t mailbox12;
723		- uint16_t mailbox13;
724		- uint16_t mailbox14;
725		- uint16_t mailbox15;
726		- uint16_t mailbox16;
727		- uint16_t mailbox17;
728		- uint16_t mailbox18;
729		- uint16_t mailbox19;
730		- uint16_t mailbox20;
731		- uint16_t mailbox21;
732		- uint16_t mailbox22;
733		- uint16_t mailbox23; /* Also probe reg. */
	839	+ __le16 unused_10[8]; /* Gap */
	840	+ __le16 mailbox8;
	841	+ __le16 mailbox9;
	842	+ __le16 mailbox10;
	843	+ __le16 mailbox11;
	844	+ __le16 mailbox12;
	845	+ __le16 mailbox13;
	846	+ __le16 mailbox14;
	847	+ __le16 mailbox15;
	848	+ __le16 mailbox16;
	849	+ __le16 mailbox17;
	850	+ __le16 mailbox18;
	851	+ __le16 mailbox19;
	852	+ __le16 mailbox20;
	853	+ __le16 mailbox21;
	854	+ __le16 mailbox22;
	855	+ __le16 mailbox23; /* Also probe reg. */
734	856	} __attribute__((packed)) isp2200;
735	857	} u_end;
736	858	};
737	859
738	860	struct device_reg_25xxmq {
739		- uint32_t req_q_in;
740		- uint32_t req_q_out;
741		- uint32_t rsp_q_in;
742		- uint32_t rsp_q_out;
743		- uint32_t atio_q_in;
744		- uint32_t atio_q_out;
	861	+ __le32 req_q_in;
	862	+ __le32 req_q_out;
	863	+ __le32 rsp_q_in;
	864	+ __le32 rsp_q_out;
	865	+ __le32 atio_q_in;
	866	+ __le32 atio_q_out;
745	867	};
746	868
747	869
748	870	struct device_reg_fx00 {
749		- uint32_t mailbox0; /* 00 */
750		- uint32_t mailbox1; /* 04 */
751		- uint32_t mailbox2; /* 08 */
752		- uint32_t mailbox3; /* 0C */
753		- uint32_t mailbox4; /* 10 */
754		- uint32_t mailbox5; /* 14 */
755		- uint32_t mailbox6; /* 18 */
756		- uint32_t mailbox7; /* 1C */
757		- uint32_t mailbox8; /* 20 */
758		- uint32_t mailbox9; /* 24 */
759		- uint32_t mailbox10; /* 28 */
760		- uint32_t mailbox11;
761		- uint32_t mailbox12;
762		- uint32_t mailbox13;
763		- uint32_t mailbox14;
764		- uint32_t mailbox15;
765		- uint32_t mailbox16;
766		- uint32_t mailbox17;
767		- uint32_t mailbox18;
768		- uint32_t mailbox19;
769		- uint32_t mailbox20;
770		- uint32_t mailbox21;
771		- uint32_t mailbox22;
772		- uint32_t mailbox23;
773		- uint32_t mailbox24;
774		- uint32_t mailbox25;
775		- uint32_t mailbox26;
776		- uint32_t mailbox27;
777		- uint32_t mailbox28;
778		- uint32_t mailbox29;
779		- uint32_t mailbox30;
780		- uint32_t mailbox31;
781		- uint32_t aenmailbox0;
782		- uint32_t aenmailbox1;
783		- uint32_t aenmailbox2;
784		- uint32_t aenmailbox3;
785		- uint32_t aenmailbox4;
786		- uint32_t aenmailbox5;
787		- uint32_t aenmailbox6;
788		- uint32_t aenmailbox7;
	871	+ __le32 mailbox0; /* 00 */
	872	+ __le32 mailbox1; /* 04 */
	873	+ __le32 mailbox2; /* 08 */
	874	+ __le32 mailbox3; /* 0C */
	875	+ __le32 mailbox4; /* 10 */
	876	+ __le32 mailbox5; /* 14 */
	877	+ __le32 mailbox6; /* 18 */
	878	+ __le32 mailbox7; /* 1C */
	879	+ __le32 mailbox8; /* 20 */
	880	+ __le32 mailbox9; /* 24 */
	881	+ __le32 mailbox10; /* 28 */
	882	+ __le32 mailbox11;
	883	+ __le32 mailbox12;
	884	+ __le32 mailbox13;
	885	+ __le32 mailbox14;
	886	+ __le32 mailbox15;
	887	+ __le32 mailbox16;
	888	+ __le32 mailbox17;
	889	+ __le32 mailbox18;
	890	+ __le32 mailbox19;
	891	+ __le32 mailbox20;
	892	+ __le32 mailbox21;
	893	+ __le32 mailbox22;
	894	+ __le32 mailbox23;
	895	+ __le32 mailbox24;
	896	+ __le32 mailbox25;
	897	+ __le32 mailbox26;
	898	+ __le32 mailbox27;
	899	+ __le32 mailbox28;
	900	+ __le32 mailbox29;
	901	+ __le32 mailbox30;
	902	+ __le32 mailbox31;
	903	+ __le32 aenmailbox0;
	904	+ __le32 aenmailbox1;
	905	+ __le32 aenmailbox2;
	906	+ __le32 aenmailbox3;
	907	+ __le32 aenmailbox4;
	908	+ __le32 aenmailbox5;
	909	+ __le32 aenmailbox6;
	910	+ __le32 aenmailbox7;
789	911	/* Request Queue. */
790		- uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
791		- uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
	912	+ __le32 req_q_in; /* A0 - Request Queue In-Pointer */
	913	+ __le32 req_q_out; /* A4 - Request Queue Out-Pointer */
792	914	/* Response Queue. */
793		- uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
794		- uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
	915	+ __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */
	916	+ __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */
795	917	/* Init values shadowed on FW Up Event */
796		- uint32_t initval0; /* B0 */
797		- uint32_t initval1; /* B4 */
798		- uint32_t initval2; /* B8 */
799		- uint32_t initval3; /* BC */
800		- uint32_t initval4; /* C0 */
801		- uint32_t initval5; /* C4 */
802		- uint32_t initval6; /* C8 */
803		- uint32_t initval7; /* CC */
804		- uint32_t fwheartbeat; /* D0 */
805		- uint32_t pseudoaen; /* D4 */
	918	+ __le32 initval0; /* B0 */
	919	+ __le32 initval1; /* B4 */
	920	+ __le32 initval2; /* B8 */
	921	+ __le32 initval3; /* BC */
	922	+ __le32 initval4; /* C0 */
	923	+ __le32 initval5; /* C4 */
	924	+ __le32 initval6; /* C8 */
	925	+ __le32 initval7; /* CC */
	926	+ __le32 fwheartbeat; /* D0 */
	927	+ __le32 pseudoaen; /* D4 */
806	928	};
807	929
808	930
..	..	@@ -842,18 +964,18 @@
842	964	&(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
843	965	&(reg)->u.isp2300.mailbox0 + (num))
844	966	#define RD_MAILBOX_REG(ha, reg, num) \
845		- RD_REG_WORD(MAILBOX_REG(ha, reg, num))
	967	+ rd_reg_word(MAILBOX_REG(ha, reg, num))
846	968	#define WRT_MAILBOX_REG(ha, reg, num, data) \
847		- WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
	969	+ wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
848	970
849	971	#define FB_CMD_REG(ha, reg) \
850	972	(IS_QLA2100(ha) \|\| IS_QLA2200(ha) ? \
851	973	&(reg)->fb_cmd_2100 : \
852	974	&(reg)->u.isp2300.fb_cmd)
853	975	#define RD_FB_CMD_REG(ha, reg) \
854		- RD_REG_WORD(FB_CMD_REG(ha, reg))
	976	+ rd_reg_word(FB_CMD_REG(ha, reg))
855	977	#define WRT_FB_CMD_REG(ha, reg, data) \
856		- WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
	978	+ wrt_reg_word(FB_CMD_REG(ha, reg), data)
857	979
858	980	typedef struct {
859	981	uint32_t out_mb; /* outbound from driver */
..	..	@@ -915,6 +1037,11 @@
915	1037	#define MBS_LINK_DOWN_ERROR 0x400B
916	1038	#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
917	1039
	1040	+static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
	1041	+{
	1042	+ return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
	1043	+}
	1044	+
918	1045	/*
919	1046	* ISP mailbox asynchronous event status codes
920	1047	*/
..	..	@@ -934,6 +1061,7 @@
934	1061	#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
935	1062	#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
936	1063	#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
	1064	+#define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */
937	1065	#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
938	1066	#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
939	1067	#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
..	..	@@ -965,6 +1093,7 @@
965	1093	#define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
966	1094	#define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
967	1095	#define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
	1096	+#define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */
968	1097	#define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
969	1098	#define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
970	1099	Notification */
..	..	@@ -1031,6 +1160,7 @@
1031	1160	#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1032	1161	#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1033	1162	#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
	1163	+#define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
1034	1164	#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1035	1165	#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1036	1166	#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
..	..	@@ -1049,6 +1179,7 @@
1049	1179	#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1050	1180	#define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1051	1181	#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
	1182	+#define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */
1052	1183	#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1053	1184	#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1054	1185	#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
..	..	@@ -1175,9 +1306,13 @@
1175	1306	#define MBX_1 BIT_1
1176	1307	#define MBX_0 BIT_0
1177	1308
	1309	+#define RNID_TYPE_ELS_CMD 0x5
1178	1310	#define RNID_TYPE_PORT_LOGIN 0x7
	1311	+#define RNID_BUFFER_CREDITS 0x8
1179	1312	#define RNID_TYPE_SET_VERSION 0x9
1180	1313	#define RNID_TYPE_ASIC_TEMP 0xC
	1314	+
	1315	+#define ELS_CMD_MAP_SIZE 32
1181	1316
1182	1317	/*
1183	1318	* Firmware state codes from get firmware state mailbox command
..	..	@@ -1201,6 +1336,10 @@
1201	1336	#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1202	1337	#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1203	1338	#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
	1339	+#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
	1340	+#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
	1341	+#define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
	1342	+#define QLA27XX_DEFAULT_IMAGE 0
1204	1343	#define QLA27XX_PRIMARY_IMAGE 1
1205	1344	#define QLA27XX_SECONDARY_IMAGE 2
1206	1345
..	..	@@ -1220,7 +1359,7 @@
1220	1359	uint8_t port_id[4];
1221	1360	uint8_t node_name[WWN_SIZE];
1222	1361	uint8_t port_name[WWN_SIZE];
1223		- uint16_t execution_throttle;
	1362	+ __le16 execution_throttle;
1224	1363	uint16_t execution_count;
1225	1364	uint8_t reset_count;
1226	1365	uint8_t reserved_2;
..	..	@@ -1306,9 +1445,9 @@
1306	1445	*/
1307	1446	uint8_t firmware_options[2];
1308	1447
1309		- uint16_t frame_payload_size;
1310		- uint16_t max_iocb_allocation;
1311		- uint16_t execution_throttle;
	1448	+ __le16 frame_payload_size;
	1449	+ __le16 max_iocb_allocation;
	1450	+ __le16 execution_throttle;
1312	1451	uint8_t retry_count;
1313	1452	uint8_t retry_delay; /* unused */
1314	1453	uint8_t port_name[WWN_SIZE]; /* Big endian. */
..	..	@@ -1317,17 +1456,17 @@
1317	1456	uint8_t login_timeout;
1318	1457	uint8_t node_name[WWN_SIZE]; /* Big endian. */
1319	1458
1320		- uint16_t request_q_outpointer;
1321		- uint16_t response_q_inpointer;
1322		- uint16_t request_q_length;
1323		- uint16_t response_q_length;
1324		- uint32_t request_q_address[2];
1325		- uint32_t response_q_address[2];
	1459	+ __le16 request_q_outpointer;
	1460	+ __le16 response_q_inpointer;
	1461	+ __le16 request_q_length;
	1462	+ __le16 response_q_length;
	1463	+ __le64 request_q_address __packed;
	1464	+ __le64 response_q_address __packed;
1326	1465
1327		- uint16_t lun_enables;
	1466	+ __le16 lun_enables;
1328	1467	uint8_t command_resource_count;
1329	1468	uint8_t immediate_notify_resource_count;
1330		- uint16_t timeout;
	1469	+ __le16 timeout;
1331	1470	uint8_t reserved_2[2];
1332	1471
1333	1472	/*
..	..	@@ -1378,6 +1517,25 @@
1378	1517	uint8_t reserved_3[26];
1379	1518	} init_cb_t;
1380	1519
	1520	+/* Special Features Control Block */
	1521	+struct init_sf_cb {
	1522	+ uint8_t format;
	1523	+ uint8_t reserved0;
	1524	+ /*
	1525	+ * BIT 15-14 = Reserved
	1526	+ * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled)
	1527	+ * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled)
	1528	+ * BIT 11-0 = Reserved
	1529	+ */
	1530	+ uint16_t flags;
	1531	+ uint8_t reserved1[32];
	1532	+ uint16_t discard_OHRB_timeout_value;
	1533	+ uint16_t remote_write_opt_queue_num;
	1534	+ uint8_t reserved2[40];
	1535	+ uint8_t scm_related_parameter[16];
	1536	+ uint8_t reserved3[32];
	1537	+};
	1538	+
1381	1539	/*
1382	1540	* Get Link Status mailbox command return buffer.
1383	1541	*/
..	..	@@ -1385,47 +1543,44 @@
1385	1543	#define GLSO_USE_DID BIT_3
1386	1544
1387	1545	struct link_statistics {
1388		- uint32_t link_fail_cnt;
1389		- uint32_t loss_sync_cnt;
1390		- uint32_t loss_sig_cnt;
1391		- uint32_t prim_seq_err_cnt;
1392		- uint32_t inval_xmit_word_cnt;
1393		- uint32_t inval_crc_cnt;
1394		- uint32_t lip_cnt;
1395		- uint32_t link_up_cnt;
1396		- uint32_t link_down_loop_init_tmo;
1397		- uint32_t link_down_los;
1398		- uint32_t link_down_loss_rcv_clk;
	1546	+ __le32 link_fail_cnt;
	1547	+ __le32 loss_sync_cnt;
	1548	+ __le32 loss_sig_cnt;
	1549	+ __le32 prim_seq_err_cnt;
	1550	+ __le32 inval_xmit_word_cnt;
	1551	+ __le32 inval_crc_cnt;
	1552	+ __le32 lip_cnt;
	1553	+ __le32 link_up_cnt;
	1554	+ __le32 link_down_loop_init_tmo;
	1555	+ __le32 link_down_los;
	1556	+ __le32 link_down_loss_rcv_clk;
1399	1557	uint32_t reserved0[5];
1400		- uint32_t port_cfg_chg;
	1558	+ __le32 port_cfg_chg;
1401	1559	uint32_t reserved1[11];
1402		- uint32_t rsp_q_full;
1403		- uint32_t atio_q_full;
1404		- uint32_t drop_ae;
1405		- uint32_t els_proto_err;
1406		- uint32_t reserved2;
1407		- uint32_t tx_frames;
1408		- uint32_t rx_frames;
1409		- uint32_t discarded_frames;
1410		- uint32_t dropped_frames;
	1560	+ __le32 rsp_q_full;
	1561	+ __le32 atio_q_full;
	1562	+ __le32 drop_ae;
	1563	+ __le32 els_proto_err;
	1564	+ __le32 reserved2;
	1565	+ __le32 tx_frames;
	1566	+ __le32 rx_frames;
	1567	+ __le32 discarded_frames;
	1568	+ __le32 dropped_frames;
1411	1569	uint32_t reserved3;
1412		- uint32_t nos_rcvd;
	1570	+ __le32 nos_rcvd;
1413	1571	uint32_t reserved4[4];
1414		- uint32_t tx_prjt;
1415		- uint32_t rcv_exfail;
1416		- uint32_t rcv_abts;
1417		- uint32_t seq_frm_miss;
1418		- uint32_t corr_err;
1419		- uint32_t mb_rqst;
1420		- uint32_t nport_full;
1421		- uint32_t eofa;
	1572	+ __le32 tx_prjt;
	1573	+ __le32 rcv_exfail;
	1574	+ __le32 rcv_abts;
	1575	+ __le32 seq_frm_miss;
	1576	+ __le32 corr_err;
	1577	+ __le32 mb_rqst;
	1578	+ __le32 nport_full;
	1579	+ __le32 eofa;
1422	1580	uint32_t reserved5;
1423		- uint32_t fpm_recv_word_cnt_lo;
1424		- uint32_t fpm_recv_word_cnt_hi;
1425		- uint32_t fpm_disc_word_cnt_lo;
1426		- uint32_t fpm_disc_word_cnt_hi;
1427		- uint32_t fpm_xmit_word_cnt_lo;
1428		- uint32_t fpm_xmit_word_cnt_hi;
	1581	+ __le64 fpm_recv_word_cnt;
	1582	+ __le64 fpm_disc_word_cnt;
	1583	+ __le64 fpm_xmit_word_cnt;
1429	1584	uint32_t reserved6[70];
1430	1585	};
1431	1586
..	..	@@ -1477,9 +1632,9 @@
1477	1632	*/
1478	1633	uint8_t firmware_options[2];
1479	1634
1480		- uint16_t frame_payload_size;
1481		- uint16_t max_iocb_allocation;
1482		- uint16_t execution_throttle;
	1635	+ __le16 frame_payload_size;
	1636	+ __le16 max_iocb_allocation;
	1637	+ __le16 execution_throttle;
1483	1638	uint8_t retry_count;
1484	1639	uint8_t retry_delay; /* unused */
1485	1640	uint8_t port_name[WWN_SIZE]; /* Big endian. */
..	..	@@ -1603,7 +1758,7 @@
1603	1758	uint8_t reset_delay;
1604	1759	uint8_t port_down_retry_count;
1605	1760	uint8_t boot_id_number;
1606		- uint16_t max_luns_per_target;
	1761	+ __le16 max_luns_per_target;
1607	1762	uint8_t fcode_boot_port_name[WWN_SIZE];
1608	1763	uint8_t alternate_port_name[WWN_SIZE];
1609	1764	uint8_t alternate_node_name[WWN_SIZE];
..	..	@@ -1709,7 +1864,7 @@
1709	1864	};
1710	1865
1711	1866	typedef union {
1712		- uint16_t extended;
	1867	+ __le16 extended;
1713	1868	struct {
1714	1869	uint8_t reserved;
1715	1870	uint8_t standard;
..	..	@@ -1735,24 +1890,22 @@
1735	1890	uint8_t entry_status; /* Entry Status. */
1736	1891	uint32_t handle; /* System handle. */
1737	1892	target_id_t target; /* SCSI ID */
1738		- uint16_t lun; /* SCSI LUN */
1739		- uint16_t control_flags; /* Control flags. */
	1893	+ __le16 lun; /* SCSI LUN */
	1894	+ __le16 control_flags; /* Control flags. */
1740	1895	#define CF_WRITE BIT_6
1741	1896	#define CF_READ BIT_5
1742	1897	#define CF_SIMPLE_TAG BIT_3
1743	1898	#define CF_ORDERED_TAG BIT_2
1744	1899	#define CF_HEAD_TAG BIT_1
1745	1900	uint16_t reserved_1;
1746		- uint16_t timeout; /* Command timeout. */
1747		- uint16_t dseg_count; /* Data segment count. */
	1901	+ __le16 timeout; /* Command timeout. */
	1902	+ __le16 dseg_count; /* Data segment count. */
1748	1903	uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1749		- uint32_t byte_count; /* Total byte count. */
1750		- uint32_t dseg_0_address; /* Data segment 0 address. */
1751		- uint32_t dseg_0_length; /* Data segment 0 length. */
1752		- uint32_t dseg_1_address; /* Data segment 1 address. */
1753		- uint32_t dseg_1_length; /* Data segment 1 length. */
1754		- uint32_t dseg_2_address; /* Data segment 2 address. */
1755		- uint32_t dseg_2_length; /* Data segment 2 length. */
	1904	+ __le32 byte_count; /* Total byte count. */
	1905	+ union {
	1906	+ struct dsd32 dsd32[3];
	1907	+ struct dsd64 dsd64[2];
	1908	+ };
1756	1909	} cmd_entry_t;
1757	1910
1758	1911	/*
..	..	@@ -1766,17 +1919,14 @@
1766	1919	uint8_t entry_status; /* Entry Status. */
1767	1920	uint32_t handle; /* System handle. */
1768	1921	target_id_t target; /* SCSI ID */
1769		- uint16_t lun; /* SCSI LUN */
1770		- uint16_t control_flags; /* Control flags. */
	1922	+ __le16 lun; /* SCSI LUN */
	1923	+ __le16 control_flags; /* Control flags. */
1771	1924	uint16_t reserved_1;
1772		- uint16_t timeout; /* Command timeout. */
1773		- uint16_t dseg_count; /* Data segment count. */
	1925	+ __le16 timeout; /* Command timeout. */
	1926	+ __le16 dseg_count; /* Data segment count. */
1774	1927	uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1775	1928	uint32_t byte_count; /* Total byte count. */
1776		- uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1777		- uint32_t dseg_0_length; /* Data segment 0 length. */
1778		- uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1779		- uint32_t dseg_1_length; /* Data segment 1 length. */
	1929	+ struct dsd64 dsd[2];
1780	1930	} cmd_a64_entry_t, request_t;
1781	1931
1782	1932	/*
..	..	@@ -1789,20 +1939,7 @@
1789	1939	uint8_t sys_define; /* System defined. */
1790	1940	uint8_t entry_status; /* Entry Status. */
1791	1941	uint32_t reserved;
1792		- uint32_t dseg_0_address; /* Data segment 0 address. */
1793		- uint32_t dseg_0_length; /* Data segment 0 length. */
1794		- uint32_t dseg_1_address; /* Data segment 1 address. */
1795		- uint32_t dseg_1_length; /* Data segment 1 length. */
1796		- uint32_t dseg_2_address; /* Data segment 2 address. */
1797		- uint32_t dseg_2_length; /* Data segment 2 length. */
1798		- uint32_t dseg_3_address; /* Data segment 3 address. */
1799		- uint32_t dseg_3_length; /* Data segment 3 length. */
1800		- uint32_t dseg_4_address; /* Data segment 4 address. */
1801		- uint32_t dseg_4_length; /* Data segment 4 length. */
1802		- uint32_t dseg_5_address; /* Data segment 5 address. */
1803		- uint32_t dseg_5_length; /* Data segment 5 length. */
1804		- uint32_t dseg_6_address; /* Data segment 6 address. */
1805		- uint32_t dseg_6_length; /* Data segment 6 length. */
	1942	+ struct dsd32 dsd[7];
1806	1943	} cont_entry_t;
1807	1944
1808	1945	/*
..	..	@@ -1814,16 +1951,7 @@
1814	1951	uint8_t entry_count; /* Entry count. */
1815	1952	uint8_t sys_define; /* System defined. */
1816	1953	uint8_t entry_status; /* Entry Status. */
1817		- uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1818		- uint32_t dseg_0_length; /* Data segment 0 length. */
1819		- uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1820		- uint32_t dseg_1_length; /* Data segment 1 length. */
1821		- uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1822		- uint32_t dseg_2_length; /* Data segment 2 length. */
1823		- uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1824		- uint32_t dseg_3_length; /* Data segment 3 length. */
1825		- uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1826		- uint32_t dseg_4_length; /* Data segment 4 length. */
	1954	+ struct dsd64 dsd[5];
1827	1955	} cont_a64_entry_t;
1828	1956
1829	1957	#define PO_MODE_DIF_INSERT 0
..	..	@@ -1857,7 +1985,7 @@
1857	1985	__le16 guard_seed; /* Initial Guard Seed */
1858	1986	__le16 prot_opts; /* Requested Data Protection Mode */
1859	1987	__le16 blk_size; /* Data size in bytes */
1860		- uint16_t runt_blk_guard; /* Guard value for runt block (tape
	1988	+ __le16 runt_blk_guard; /* Guard value for runt block (tape
1861	1989	* only) */
1862	1990	__le32 byte_count; /* Total byte count/ total data
1863	1991	* transfer count */
..	..	@@ -1867,8 +1995,7 @@
1867	1995	uint16_t reserved_2;
1868	1996	uint16_t reserved_3;
1869	1997	uint32_t reserved_4;
1870		- uint32_t data_address[2];
1871		- uint32_t data_length;
	1998	+ struct dsd64 data_dsd[1];
1872	1999	uint32_t reserved_5[2];
1873	2000	uint32_t reserved_6;
1874	2001	} nobundling;
..	..	@@ -1878,11 +2005,8 @@
1878	2005	uint16_t reserved_1;
1879	2006	__le16 dseg_count; /* Data segment count */
1880	2007	uint32_t reserved_2;
1881		- uint32_t data_address[2];
1882		- uint32_t data_length;
1883		- uint32_t dif_address[2];
1884		- uint32_t dif_length; /* Data segment 0
1885		- * length */
	2008	+ struct dsd64 data_dsd[1];
	2009	+ struct dsd64 dif_dsd;
1886	2010	} bundling;
1887	2011	} u;
1888	2012
..	..	@@ -1891,6 +2015,13 @@
1891	2015	/* List of DMA context transfers */
1892	2016	struct list_head dsd_list;
1893	2017
	2018	+ /* List of DIF Bundling context DMA address */
	2019	+ struct list_head ldif_dsd_list;
	2020	+ u8 no_ldif_dsd;
	2021	+
	2022	+ struct list_head ldif_dma_hndl_list;
	2023	+ u32 dif_bundl_len;
	2024	+ u8 no_dif_bundl;
1894	2025	/* This structure should not exceed 512 bytes */
1895	2026	};
1896	2027
..	..	@@ -1907,13 +2038,13 @@
1907	2038	uint8_t sys_define; /* System defined. */
1908	2039	uint8_t entry_status; /* Entry Status. */
1909	2040	uint32_t handle; /* System handle. */
1910		- uint16_t scsi_status; /* SCSI status. */
1911		- uint16_t comp_status; /* Completion status. */
1912		- uint16_t state_flags; /* State flags. */
1913		- uint16_t status_flags; /* Status flags. */
1914		- uint16_t rsp_info_len; /* Response Info Length. */
1915		- uint16_t req_sense_length; /* Request sense data length. */
1916		- uint32_t residual_length; /* Residual transfer length. */
	2041	+ __le16 scsi_status; /* SCSI status. */
	2042	+ __le16 comp_status; /* Completion status. */
	2043	+ __le16 state_flags; /* State flags. */
	2044	+ __le16 status_flags; /* Status flags. */
	2045	+ __le16 rsp_info_len; /* Response Info Length. */
	2046	+ __le16 req_sense_length; /* Request sense data length. */
	2047	+ __le32 residual_length; /* Residual transfer length. */
1917	2048	uint8_t rsp_info[8]; /* FCP response information. */
1918	2049	uint8_t req_sense_data[32]; /* Request sense data. */
1919	2050	} sts_entry_t;
..	..	@@ -2045,8 +2176,8 @@
2045	2176	/* clear port changed, */
2046	2177	/* use sequence number. */
2047	2178	uint8_t reserved_1;
2048		- uint16_t sequence_number; /* Sequence number of event */
2049		- uint16_t lun; /* SCSI LUN */
	2179	+ __le16 sequence_number; /* Sequence number of event */
	2180	+ __le16 lun; /* SCSI LUN */
2050	2181	uint8_t reserved_2[48];
2051	2182	} mrk_entry_t;
2052	2183
..	..	@@ -2061,25 +2192,25 @@
2061	2192	uint8_t entry_status; /* Entry Status. */
2062	2193	uint32_t handle1; /* System handle. */
2063	2194	target_id_t loop_id;
2064		- uint16_t status;
2065		- uint16_t control_flags; /* Control flags. */
	2195	+ __le16 status;
	2196	+ __le16 control_flags; /* Control flags. */
2066	2197	uint16_t reserved2;
2067		- uint16_t timeout;
2068		- uint16_t cmd_dsd_count;
2069		- uint16_t total_dsd_count;
	2198	+ __le16 timeout;
	2199	+ __le16 cmd_dsd_count;
	2200	+ __le16 total_dsd_count;
2070	2201	uint8_t type;
2071	2202	uint8_t r_ctl;
2072		- uint16_t rx_id;
	2203	+ __le16 rx_id;
2073	2204	uint16_t reserved3;
2074	2205	uint32_t handle2;
2075		- uint32_t rsp_bytecount;
2076		- uint32_t req_bytecount;
2077		- uint32_t dseg_req_address[2]; /* Data segment 0 address. */
2078		- uint32_t dseg_req_length; /* Data segment 0 length. */
2079		- uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
2080		- uint32_t dseg_rsp_length; /* Data segment 1 length. */
	2206	+ __le32 rsp_bytecount;
	2207	+ __le32 req_bytecount;
	2208	+ struct dsd64 req_dsd;
	2209	+ struct dsd64 rsp_dsd;
2081	2210	} ms_iocb_entry_t;
2082	2211
	2212	+#define SCM_EDC_ACC_RECEIVED BIT_6
	2213	+#define SCM_RDF_ACC_RECEIVED BIT_7
2083	2214
2084	2215	/*
2085	2216	* ISP queue - Mailbox Command entry structure definition.
..	..	@@ -2103,20 +2234,20 @@
2103	2234	uint32_t handle;
2104	2235	target_id_t loop_id;
2105	2236
2106		- uint16_t status;
2107		- uint16_t state_flags;
2108		- uint16_t status_flags;
	2237	+ __le16 status;
	2238	+ __le16 state_flags;
	2239	+ __le16 status_flags;
2109	2240
2110	2241	uint32_t sys_define2[2];
2111	2242
2112		- uint16_t mb0;
2113		- uint16_t mb1;
2114		- uint16_t mb2;
2115		- uint16_t mb3;
2116		- uint16_t mb6;
2117		- uint16_t mb7;
2118		- uint16_t mb9;
2119		- uint16_t mb10;
	2243	+ __le16 mb0;
	2244	+ __le16 mb1;
	2245	+ __le16 mb2;
	2246	+ __le16 mb3;
	2247	+ __le16 mb6;
	2248	+ __le16 mb7;
	2249	+ __le16 mb9;
	2250	+ __le16 mb10;
2120	2251	uint32_t reserved_2[2];
2121	2252	uint8_t node_name[WWN_SIZE];
2122	2253	uint8_t port_name[WWN_SIZE];
..	..	@@ -2138,52 +2269,52 @@
2138	2269	uint8_t entry_status; /* Entry Status. */
2139	2270	union {
2140	2271	struct {
2141		- uint32_t sys_define_2; /* System defined. */
	2272	+ __le32 sys_define_2; /* System defined. */
2142	2273	target_id_t target;
2143		- uint16_t lun;
	2274	+ __le16 lun;
2144	2275	uint8_t target_id;
2145	2276	uint8_t reserved_1;
2146		- uint16_t status_modifier;
2147		- uint16_t status;
2148		- uint16_t task_flags;
2149		- uint16_t seq_id;
2150		- uint16_t srr_rx_id;
2151		- uint32_t srr_rel_offs;
2152		- uint16_t srr_ui;
	2277	+ __le16 status_modifier;
	2278	+ __le16 status;
	2279	+ __le16 task_flags;
	2280	+ __le16 seq_id;
	2281	+ __le16 srr_rx_id;
	2282	+ __le32 srr_rel_offs;
	2283	+ __le16 srr_ui;
2153	2284	#define SRR_IU_DATA_IN 0x1
2154	2285	#define SRR_IU_DATA_OUT 0x5
2155	2286	#define SRR_IU_STATUS 0x7
2156		- uint16_t srr_ox_id;
	2287	+ __le16 srr_ox_id;
2157	2288	uint8_t reserved_2[28];
2158	2289	} isp2x;
2159	2290	struct {
2160	2291	uint32_t reserved;
2161		- uint16_t nport_handle;
	2292	+ __le16 nport_handle;
2162	2293	uint16_t reserved_2;
2163		- uint16_t flags;
	2294	+ __le16 flags;
2164	2295	#define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2165	2296	#define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2166		- uint16_t srr_rx_id;
2167		- uint16_t status;
	2297	+ __le16 srr_rx_id;
	2298	+ __le16 status;
2168	2299	uint8_t status_subcode;
2169	2300	uint8_t fw_handle;
2170		- uint32_t exchange_address;
2171		- uint32_t srr_rel_offs;
2172		- uint16_t srr_ui;
2173		- uint16_t srr_ox_id;
	2301	+ __le32 exchange_address;
	2302	+ __le32 srr_rel_offs;
	2303	+ __le16 srr_ui;
	2304	+ __le16 srr_ox_id;
2174	2305	union {
2175	2306	struct {
2176	2307	uint8_t node_name[8];
2177	2308	} plogi; /* PLOGI/ADISC/PDISC */
2178	2309	struct {
2179	2310	/* PRLI word 3 bit 0-15 */
2180		- uint16_t wd3_lo;
	2311	+ __le16 wd3_lo;
2181	2312	uint8_t resv0[6];
2182	2313	} prli;
2183	2314	struct {
2184	2315	uint8_t port_id[3];
2185	2316	uint8_t resv1;
2186		- uint16_t nport_handle;
	2317	+ __le16 nport_handle;
2187	2318	uint16_t resv2;
2188	2319	} req_els;
2189	2320	} u;
..	..	@@ -2196,7 +2327,7 @@
2196	2327	} isp24;
2197	2328	} u;
2198	2329	uint16_t reserved_7;
2199		- uint16_t ox_id;
	2330	+ __le16 ox_id;
2200	2331	} __packed;
2201	2332	#endif
2202	2333
..	..	@@ -2218,7 +2349,7 @@
2218	2349	uint8_t fabric_port_name[WWN_SIZE];
2219	2350	uint16_t fp_speed;
2220	2351	uint8_t fc4_type;
2221		- uint8_t fc4f_nvme; /* nvme fc4 feature bits */
	2352	+ uint8_t fc4_features;
2222	2353	} sw_info_t;
2223	2354
2224	2355	/* FCP-4 types */
..	..	@@ -2249,7 +2380,10 @@
2249	2380	FCT_BROADCAST,
2250	2381	FCT_INITIATOR,
2251	2382	FCT_TARGET,
2252		- FCT_NVME
	2383	+ FCT_NVME_INITIATOR = 0x10,
	2384	+ FCT_NVME_TARGET = 0x20,
	2385	+ FCT_NVME_DISCOVERY = 0x40,
	2386	+ FCT_NVME = 0xf0,
2253	2387	} fc_port_type_t;
2254	2388
2255	2389	enum qla_sess_deletion {
..	..	@@ -2280,7 +2414,6 @@
2280	2414	enum discovery_state {
2281	2415	DSC_DELETED,
2282	2416	DSC_GNN_ID,
2283		- DSC_GID_PN,
2284	2417	DSC_GNL,
2285	2418	DSC_LOGIN_PEND,
2286	2419	DSC_LOGIN_FAILED,
..	..	@@ -2302,23 +2435,6 @@
2302	2435	DSC_LS_LOGO_PEND,
2303	2436	};
2304	2437
2305		-enum fcport_mgt_event {
2306		- FCME_RELOGIN = 1,
2307		- FCME_RSCN,
2308		- FCME_GIDPN_DONE,
2309		- FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */
2310		- FCME_PRLI_DONE,
2311		- FCME_GNL_DONE,
2312		- FCME_GPSC_DONE,
2313		- FCME_GPDB_DONE,
2314		- FCME_GPNID_DONE,
2315		- FCME_GFFID_DONE,
2316		- FCME_ADISC_DONE,
2317		- FCME_GNNID_DONE,
2318		- FCME_GFPNID_DONE,
2319		- FCME_ELS_PLOGI_DONE,
2320		-};
2321		-
2322	2438	enum rscn_addr_format {
2323	2439	RSCN_PORT_ADDR,
2324	2440	RSCN_AREA_ADDR,
..	..	@@ -2333,12 +2449,6 @@
2333	2449	struct list_head list;
2334	2450	struct scsi_qla_host *vha;
2335	2451
2336		- uint8_t node_name[WWN_SIZE];
2337		- uint8_t port_name[WWN_SIZE];
2338		- port_id_t d_id;
2339		- uint16_t loop_id;
2340		- uint16_t old_loop_id;
2341		-
2342	2452	unsigned int conf_compl_supported:1;
2343	2453	unsigned int deleted:2;
2344	2454	unsigned int free_pending:1;
..	..	@@ -2352,15 +2462,28 @@
2352	2462	unsigned int query:1;
2353	2463	unsigned int id_changed:1;
2354	2464	unsigned int scan_needed:1;
	2465	+ unsigned int n2n_flag:1;
	2466	+ unsigned int explicit_logout:1;
	2467	+ unsigned int prli_pend_timer:1;
	2468	+ uint8_t nvme_flag;
2355	2469
2356		- struct work_struct nvme_del_work;
	2470	+ uint8_t node_name[WWN_SIZE];
	2471	+ uint8_t port_name[WWN_SIZE];
	2472	+ port_id_t d_id;
	2473	+ uint16_t loop_id;
	2474	+ uint16_t old_loop_id;
	2475	+
2357	2476	struct completion nvme_del_done;
2358	2477	uint32_t nvme_prli_service_param;
	2478	+#define NVME_PRLI_SP_PI_CTRL BIT_9
	2479	+#define NVME_PRLI_SP_SLER BIT_8
2359	2480	#define NVME_PRLI_SP_CONF BIT_7
2360	2481	#define NVME_PRLI_SP_INITIATOR BIT_5
2361	2482	#define NVME_PRLI_SP_TARGET BIT_4
2362	2483	#define NVME_PRLI_SP_DISCOVERY BIT_3
2363		- uint8_t nvme_flag;
	2484	+#define NVME_PRLI_SP_FIRST_BURST BIT_0
	2485	+
	2486	+ uint32_t nvme_first_burst_size;
2364	2487	#define NVME_FLAG_REGISTERED 4
2365	2488	#define NVME_FLAG_DELETING 2
2366	2489	#define NVME_FLAG_RESETTING 1
..	..	@@ -2377,6 +2500,7 @@
2377	2500	struct work_struct free_work;
2378	2501	struct work_struct reg_work;
2379	2502	uint64_t jiffies_at_registration;
	2503	+ unsigned long prli_expired;
2380	2504	struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2381	2505
2382	2506	uint16_t tgt_id;
..	..	@@ -2399,9 +2523,8 @@
2399	2523	u32 supported_classes;
2400	2524
2401	2525	uint8_t fc4_type;
2402		- uint8_t fc4f_nvme;
	2526	+ uint8_t fc4_features;
2403	2527	uint8_t scan_state;
2404		- uint8_t n2n_flag;
2405	2528
2406	2529	unsigned long last_queue_full;
2407	2530	unsigned long last_ramp_up;
..	..	@@ -2414,6 +2537,7 @@
2414	2537	struct qla_tgt_sess *tgt_session;
2415	2538	struct ct_sns_desc ct_desc;
2416	2539	enum discovery_state disc_state;
	2540	+ atomic_t shadow_disc_state;
2417	2541	enum discovery_state next_disc_state;
2418	2542	enum login_state fw_login_state;
2419	2543	unsigned long dm_login_expire;
..	..	@@ -2429,13 +2553,19 @@
2429	2553	u8 last_login_state;
2430	2554	u16 n2n_link_reset_cnt;
2431	2555	u16 n2n_chip_reset;
	2556	+
	2557	+ struct dentry *dfs_rport_dir;
2432	2558	} fc_port_t;
	2559	+
	2560	+enum {
	2561	+ FC4_PRIORITY_NVME = 1,
	2562	+ FC4_PRIORITY_FCP = 2,
	2563	+};
2433	2564
2434	2565	#define QLA_FCPORT_SCAN 1
2435	2566	#define QLA_FCPORT_FOUND 2
2436	2567
2437	2568	struct event_arg {
2438		- enum fcport_mgt_event event;
2439	2569	fc_port_t *fcport;
2440	2570	srb_t *sp;
2441	2571	port_id_t id;
..	..	@@ -2454,12 +2584,19 @@
2454	2584	#define FCS_DEVICE_LOST 3
2455	2585	#define FCS_ONLINE 4
2456	2586
2457		-static const char * const port_state_str[] = {
2458		- "Unknown",
2459		- "UNCONFIGURED",
2460		- "DEAD",
2461		- "LOST",
2462		- "ONLINE"
	2587	+extern const char *const port_state_str[5];
	2588	+
	2589	+static const char * const port_dstate_str[] = {
	2590	+ "DELETED",
	2591	+ "GNN_ID",
	2592	+ "GNL",
	2593	+ "LOGIN_PEND",
	2594	+ "LOGIN_FAILED",
	2595	+ "GPDB",
	2596	+ "UPD_FCPORT",
	2597	+ "LOGIN_COMPLETE",
	2598	+ "ADISC",
	2599	+ "DELETE_PEND"
2463	2600	};
2464	2601
2465	2602	/*
..	..	@@ -2560,10 +2697,11 @@
2560	2697	#define GFF_ID_RSP_SIZE (16 + 128)
2561	2698
2562	2699	/*
2563		- * HBA attribute types.
	2700	+ * FDMI HBA attribute types.
2564	2701	*/
2565		-#define FDMI_HBA_ATTR_COUNT 9
2566		-#define FDMIV2_HBA_ATTR_COUNT 17
	2702	+#define FDMI1_HBA_ATTR_COUNT 9
	2703	+#define FDMI2_HBA_ATTR_COUNT 17
	2704	+
2567	2705	#define FDMI_HBA_NODE_NAME 0x1
2568	2706	#define FDMI_HBA_MANUFACTURER 0x2
2569	2707	#define FDMI_HBA_SERIAL_NUMBER 0x3
..	..	@@ -2575,16 +2713,17 @@
2575	2713	#define FDMI_HBA_FIRMWARE_VERSION 0x9
2576	2714	#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2577	2715	#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
	2716	+
2578	2717	#define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2579		-#define FDMI_HBA_VENDOR_ID 0xd
	2718	+#define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
2580	2719	#define FDMI_HBA_NUM_PORTS 0xe
2581	2720	#define FDMI_HBA_FABRIC_NAME 0xf
2582	2721	#define FDMI_HBA_BOOT_BIOS_NAME 0x10
2583		-#define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
	2722	+#define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
2584	2723
2585	2724	struct ct_fdmi_hba_attr {
2586		- uint16_t type;
2587		- uint16_t len;
	2725	+ __be16 type;
	2726	+ __be16 len;
2588	2727	union {
2589	2728	uint8_t node_name[WWN_SIZE];
2590	2729	uint8_t manufacturer[64];
..	..	@@ -2596,55 +2735,41 @@
2596	2735	uint8_t orom_version[16];
2597	2736	uint8_t fw_version[32];
2598	2737	uint8_t os_version[128];
2599		- uint32_t max_ct_len;
2600		- } a;
2601		-};
	2738	+ __be32 max_ct_len;
2602	2739
2603		-struct ct_fdmi_hba_attributes {
2604		- uint32_t count;
2605		- struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2606		-};
2607		-
2608		-struct ct_fdmiv2_hba_attr {
2609		- uint16_t type;
2610		- uint16_t len;
2611		- union {
2612		- uint8_t node_name[WWN_SIZE];
2613		- uint8_t manufacturer[64];
2614		- uint8_t serial_num[32];
2615		- uint8_t model[16+1];
2616		- uint8_t model_desc[80];
2617		- uint8_t hw_version[16];
2618		- uint8_t driver_version[32];
2619		- uint8_t orom_version[16];
2620		- uint8_t fw_version[32];
2621		- uint8_t os_version[128];
2622		- uint32_t max_ct_len;
2623	2740	uint8_t sym_name[256];
2624		- uint32_t vendor_id;
2625		- uint32_t num_ports;
	2741	+ __be32 vendor_specific_info;
	2742	+ __be32 num_ports;
2626	2743	uint8_t fabric_name[WWN_SIZE];
2627	2744	uint8_t bios_name[32];
2628	2745	uint8_t vendor_identifier[8];
2629	2746	} a;
2630	2747	};
2631	2748
2632		-struct ct_fdmiv2_hba_attributes {
2633		- uint32_t count;
2634		- struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
	2749	+struct ct_fdmi1_hba_attributes {
	2750	+ __be32 count;
	2751	+ struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
	2752	+};
	2753	+
	2754	+struct ct_fdmi2_hba_attributes {
	2755	+ __be32 count;
	2756	+ struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
2635	2757	};
2636	2758
2637	2759	/*
2638		- * Port attribute types.
	2760	+ * FDMI Port attribute types.
2639	2761	*/
2640		-#define FDMI_PORT_ATTR_COUNT 6
2641		-#define FDMIV2_PORT_ATTR_COUNT 16
	2762	+#define FDMI1_PORT_ATTR_COUNT 6
	2763	+#define FDMI2_PORT_ATTR_COUNT 16
	2764	+#define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
	2765	+
2642	2766	#define FDMI_PORT_FC4_TYPES 0x1
2643	2767	#define FDMI_PORT_SUPPORT_SPEED 0x2
2644	2768	#define FDMI_PORT_CURRENT_SPEED 0x3
2645	2769	#define FDMI_PORT_MAX_FRAME_SIZE 0x4
2646	2770	#define FDMI_PORT_OS_DEVICE_NAME 0x5
2647	2771	#define FDMI_PORT_HOST_NAME 0x6
	2772	+
2648	2773	#define FDMI_PORT_NODE_NAME 0x7
2649	2774	#define FDMI_PORT_NAME 0x8
2650	2775	#define FDMI_PORT_SYM_NAME 0x9
..	..	@@ -2654,7 +2779,15 @@
2654	2779	#define FDMI_PORT_FC4_TYPE 0xd
2655	2780	#define FDMI_PORT_STATE 0x101
2656	2781	#define FDMI_PORT_COUNT 0x102
2657		-#define FDMI_PORT_ID 0x103
	2782	+#define FDMI_PORT_IDENTIFIER 0x103
	2783	+
	2784	+#define FDMI_SMARTSAN_SERVICE 0xF100
	2785	+#define FDMI_SMARTSAN_GUID 0xF101
	2786	+#define FDMI_SMARTSAN_VERSION 0xF102
	2787	+#define FDMI_SMARTSAN_PROD_NAME 0xF103
	2788	+#define FDMI_SMARTSAN_PORT_INFO 0xF104
	2789	+#define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
	2790	+#define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
2658	2791
2659	2792	#define FDMI_PORT_SPEED_1GB 0x1
2660	2793	#define FDMI_PORT_SPEED_2GB 0x2
..	..	@@ -2663,60 +2796,69 @@
2663	2796	#define FDMI_PORT_SPEED_8GB 0x10
2664	2797	#define FDMI_PORT_SPEED_16GB 0x20
2665	2798	#define FDMI_PORT_SPEED_32GB 0x40
	2799	+#define FDMI_PORT_SPEED_20GB 0x80
	2800	+#define FDMI_PORT_SPEED_40GB 0x100
	2801	+#define FDMI_PORT_SPEED_128GB 0x200
	2802	+#define FDMI_PORT_SPEED_64GB 0x400
	2803	+#define FDMI_PORT_SPEED_256GB 0x800
2666	2804	#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2667	2805
2668	2806	#define FC_CLASS_2 0x04
2669	2807	#define FC_CLASS_3 0x08
2670	2808	#define FC_CLASS_2_3 0x0C
2671	2809
2672		-struct ct_fdmiv2_port_attr {
2673		- uint16_t type;
2674		- uint16_t len;
	2810	+struct ct_fdmi_port_attr {
	2811	+ __be16 type;
	2812	+ __be16 len;
2675	2813	union {
2676	2814	uint8_t fc4_types[32];
2677		- uint32_t sup_speed;
2678		- uint32_t cur_speed;
2679		- uint32_t max_frame_size;
	2815	+ __be32 sup_speed;
	2816	+ __be32 cur_speed;
	2817	+ __be32 max_frame_size;
2680	2818	uint8_t os_dev_name[32];
2681	2819	uint8_t host_name[256];
	2820	+
2682	2821	uint8_t node_name[WWN_SIZE];
2683	2822	uint8_t port_name[WWN_SIZE];
2684	2823	uint8_t port_sym_name[128];
2685		- uint32_t port_type;
2686		- uint32_t port_supported_cos;
	2824	+ __be32 port_type;
	2825	+ __be32 port_supported_cos;
2687	2826	uint8_t fabric_name[WWN_SIZE];
2688	2827	uint8_t port_fc4_type[32];
2689		- uint32_t port_state;
2690		- uint32_t num_ports;
2691		- uint32_t port_id;
	2828	+ __be32 port_state;
	2829	+ __be32 num_ports;
	2830	+ __be32 port_id;
	2831	+
	2832	+ uint8_t smartsan_service[24];
	2833	+ uint8_t smartsan_guid[16];
	2834	+ uint8_t smartsan_version[24];
	2835	+ uint8_t smartsan_prod_name[16];
	2836	+ __be32 smartsan_port_info;
	2837	+ __be32 smartsan_qos_support;
	2838	+ __be32 smartsan_security_support;
2692	2839	} a;
2693	2840	};
2694	2841
2695		-/*
2696		- * Port Attribute Block.
2697		- */
2698		-struct ct_fdmiv2_port_attributes {
2699		- uint32_t count;
2700		- struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
	2842	+struct ct_fdmi1_port_attributes {
	2843	+ __be32 count;
	2844	+ struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
2701	2845	};
2702	2846
2703		-struct ct_fdmi_port_attr {
2704		- uint16_t type;
2705		- uint16_t len;
2706		- union {
2707		- uint8_t fc4_types[32];
2708		- uint32_t sup_speed;
2709		- uint32_t cur_speed;
2710		- uint32_t max_frame_size;
2711		- uint8_t os_dev_name[32];
2712		- uint8_t host_name[256];
2713		- } a;
	2847	+struct ct_fdmi2_port_attributes {
	2848	+ __be32 count;
	2849	+ struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2714	2850	};
2715	2851
2716		-struct ct_fdmi_port_attributes {
2717		- uint32_t count;
2718		- struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2719		-};
	2852	+#define FDMI_ATTR_TYPELEN(obj) \
	2853	+ (sizeof((obj)->type) + sizeof((obj)->len))
	2854	+
	2855	+#define FDMI_ATTR_ALIGNMENT(len) \
	2856	+ (4 - ((len) & 3))
	2857	+
	2858	+/* FDMI register call options */
	2859	+#define CALLOPT_FDMI1 0
	2860	+#define CALLOPT_FDMI2 1
	2861	+#define CALLOPT_FDMI2_SMARTSAN 2
2720	2862
2721	2863	/* FDMI definitions. */
2722	2864	#define GRHL_CMD 0x100
..	..	@@ -2728,10 +2870,13 @@
2728	2870	#define RHBA_RSP_SIZE 16
2729	2871
2730	2872	#define RHAT_CMD 0x201
	2873	+
2731	2874	#define RPRT_CMD 0x210
	2875	+#define RPRT_RSP_SIZE 24
2732	2876
2733	2877	#define RPA_CMD 0x211
2734	2878	#define RPA_RSP_SIZE 16
	2879	+#define SMARTSAN_RPA_RSP_SIZE 24
2735	2880
2736	2881	#define DHBA_CMD 0x300
2737	2882	#define DHBA_REQ_SIZE (16 + 8)
..	..	@@ -2754,8 +2899,8 @@
2754	2899	/* CT command request */
2755	2900	struct ct_sns_req {
2756	2901	struct ct_cmd_hdr header;
2757		- uint16_t command;
2758		- uint16_t max_rsp_size;
	2902	+ __be16 command;
	2903	+ __be16 max_rsp_size;
2759	2904	uint8_t fragment_id;
2760	2905	uint8_t reserved[3];
2761	2906
..	..	@@ -2763,7 +2908,7 @@
2763	2908	/* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2764	2909	struct {
2765	2910	uint8_t reserved;
2766		- uint8_t port_id[3];
	2911	+ be_id_t port_id;
2767	2912	} port_id;
2768	2913
2769	2914	struct {
..	..	@@ -2782,13 +2927,13 @@
2782	2927
2783	2928	struct {
2784	2929	uint8_t reserved;
2785		- uint8_t port_id[3];
	2930	+ be_id_t port_id;
2786	2931	uint8_t fc4_types[32];
2787	2932	} rft_id;
2788	2933
2789	2934	struct {
2790	2935	uint8_t reserved;
2791		- uint8_t port_id[3];
	2936	+ be_id_t port_id;
2792	2937	uint16_t reserved2;
2793	2938	uint8_t fc4_feature;
2794	2939	uint8_t fc4_type;
..	..	@@ -2796,7 +2941,7 @@
2796	2941
2797	2942	struct {
2798	2943	uint8_t reserved;
2799		- uint8_t port_id[3];
	2944	+ be_id_t port_id;
2800	2945	uint8_t node_name[8];
2801	2946	} rnn_id;
2802	2947
..	..	@@ -2812,32 +2957,26 @@
2812	2957
2813	2958	struct {
2814	2959	uint8_t hba_identifier[8];
2815		- uint32_t entry_count;
	2960	+ __be32 entry_count;
2816	2961	uint8_t port_name[8];
2817		- struct ct_fdmi_hba_attributes attrs;
	2962	+ struct ct_fdmi2_hba_attributes attrs;
2818	2963	} rhba;
2819	2964
2820	2965	struct {
2821	2966	uint8_t hba_identifier[8];
2822		- uint32_t entry_count;
2823		- uint8_t port_name[8];
2824		- struct ct_fdmiv2_hba_attributes attrs;
2825		- } rhba2;
2826		-
2827		- struct {
2828		- uint8_t hba_identifier[8];
2829		- struct ct_fdmi_hba_attributes attrs;
	2967	+ struct ct_fdmi1_hba_attributes attrs;
2830	2968	} rhat;
2831	2969
2832	2970	struct {
2833	2971	uint8_t port_name[8];
2834		- struct ct_fdmi_port_attributes attrs;
	2972	+ struct ct_fdmi2_port_attributes attrs;
2835	2973	} rpa;
2836	2974
2837	2975	struct {
	2976	+ uint8_t hba_identifier[8];
2838	2977	uint8_t port_name[8];
2839		- struct ct_fdmiv2_port_attributes attrs;
2840		- } rpa2;
	2978	+ struct ct_fdmi2_port_attributes attrs;
	2979	+ } rprt;
2841	2980
2842	2981	struct {
2843	2982	uint8_t port_name[8];
..	..	@@ -2873,7 +3012,7 @@
2873	3012	/* CT command response header */
2874	3013	struct ct_rsp_hdr {
2875	3014	struct ct_cmd_hdr header;
2876		- uint16_t response;
	3015	+ __be16 response;
2877	3016	uint16_t residual;
2878	3017	uint8_t fragment_id;
2879	3018	uint8_t reason_code;
..	..	@@ -2883,7 +3022,7 @@
2883	3022
2884	3023	struct ct_sns_gid_pt_data {
2885	3024	uint8_t control_byte;
2886		- uint8_t port_id[3];
	3025	+ be_id_t port_id;
2887	3026	};
2888	3027
2889	3028	/* It's the same for both GPN_FT and GNN_FT */
..	..	@@ -2913,7 +3052,7 @@
2913	3052	union {
2914	3053	struct {
2915	3054	uint8_t port_type;
2916		- uint8_t port_id[3];
	3055	+ be_id_t port_id;
2917	3056	uint8_t port_name[8];
2918	3057	uint8_t sym_port_name_len;
2919	3058	uint8_t sym_port_name[255];
..	..	@@ -2951,7 +3090,7 @@
2951	3090	struct {
2952	3091	uint32_t entry_count;
2953	3092	uint8_t port_name[8];
2954		- struct ct_fdmi_hba_attributes attrs;
	3093	+ struct ct_fdmi1_hba_attributes attrs;
2955	3094	} ghat;
2956	3095
2957	3096	struct {
..	..	@@ -2959,8 +3098,8 @@
2959	3098	} gfpn_id;
2960	3099
2961	3100	struct {
2962		- uint16_t speeds;
2963		- uint16_t speed;
	3101	+ __be16 speeds;
	3102	+ __be16 speed;
2964	3103	} gpsc;
2965	3104
2966	3105	#define GFF_FCP_SCSI_OFFSET 7
..	..	@@ -2997,6 +3136,7 @@
2997	3136	enum fc4type_t {
2998	3137	FS_FC4TYPE_FCP = BIT_0,
2999	3138	FS_FC4TYPE_NVME = BIT_1,
	3139	+ FS_FCP_IS_N2N = BIT_7,
3000	3140	};
3001	3141
3002	3142	struct fab_scan_rp {
..	..	@@ -3049,13 +3189,13 @@
3049	3189	struct sns_cmd_pkt {
3050	3190	union {
3051	3191	struct {
3052		- uint16_t buffer_length;
3053		- uint16_t reserved_1;
3054		- uint32_t buffer_address[2];
3055		- uint16_t subcommand_length;
3056		- uint16_t reserved_2;
3057		- uint16_t subcommand;
3058		- uint16_t size;
	3192	+ __le16 buffer_length;
	3193	+ __le16 reserved_1;
	3194	+ __le64 buffer_address __packed;
	3195	+ __le16 subcommand_length;
	3196	+ __le16 reserved_2;
	3197	+ __le16 subcommand;
	3198	+ __le16 size;
3059	3199	uint32_t reserved_3;
3060	3200	uint8_t param[36];
3061	3201	} cmd;
..	..	@@ -3081,7 +3221,7 @@
3081	3221	uint8_t area;
3082	3222	uint8_t domain;
3083	3223	uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3084		- uint16_t loop_id; /* ISP23XX -- 6 bytes. */
	3224	+ __le16 loop_id; /* ISP23XX -- 6 bytes. */
3085	3225	uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3086	3226	};
3087	3227
..	..	@@ -3121,15 +3261,15 @@
3121	3261	struct isp_operations {
3122	3262
3123	3263	int (pci_config) (struct scsi_qla_host );
3124		- void (reset_chip) (struct scsi_qla_host );
	3264	+ int (reset_chip)(struct scsi_qla_host );
3125	3265	int (chip_diag) (struct scsi_qla_host );
3126	3266	void (config_rings) (struct scsi_qla_host );
3127		- void (reset_adapter) (struct scsi_qla_host );
	3267	+ int (reset_adapter)(struct scsi_qla_host );
3128	3268	int (nvram_config) (struct scsi_qla_host );
3129	3269	void (update_fw_options) (struct scsi_qla_host );
3130	3270	int (load_risc) (struct scsi_qla_host , uint32_t *);
3131	3271
3132		- char * (pci_info_str) (struct scsi_qla_host , char *);
	3272	+ char * (pci_info_str)(struct scsi_qla_host , char *, size_t);
3133	3273	char * (fw_version_str)(struct scsi_qla_host , char *, size_t);
3134	3274
3135	3275	irq_handler_t intr_handler;
..	..	@@ -3150,27 +3290,28 @@
3150	3290	void (prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3151	3291	uint32_t);
3152	3292
3153		- uint8_t (read_nvram) (struct scsi_qla_host , uint8_t ,
	3293	+ uint8_t (read_nvram)(struct scsi_qla_host , void ,
3154	3294	uint32_t, uint32_t);
3155		- int (write_nvram) (struct scsi_qla_host , uint8_t *, uint32_t,
	3295	+ int (write_nvram)(struct scsi_qla_host , void *, uint32_t,
3156	3296	uint32_t);
3157	3297
3158		- void (fw_dump) (struct scsi_qla_host , int);
	3298	+ void (fw_dump)(struct scsi_qla_host vha);
	3299	+ void (mpi_fw_dump)(struct scsi_qla_host , int);
3159	3300
3160	3301	int (beacon_on) (struct scsi_qla_host );
3161	3302	int (beacon_off) (struct scsi_qla_host );
3162	3303	void (beacon_blink) (struct scsi_qla_host );
3163	3304
3164		- uint8_t * (read_optrom) (struct scsi_qla_host , uint8_t *,
	3305	+ void (read_optrom)(struct scsi_qla_host , void ,
3165	3306	uint32_t, uint32_t);
3166		- int (write_optrom) (struct scsi_qla_host , uint8_t *, uint32_t,
	3307	+ int (write_optrom)(struct scsi_qla_host , void *, uint32_t,
3167	3308	uint32_t);
3168	3309
3169	3310	int (get_flash_version) (struct scsi_qla_host , void *);
3170	3311	int (start_scsi) (srb_t );
3171	3312	int (start_scsi_mq) (srb_t );
3172	3313	int (abort_isp) (struct scsi_qla_host );
3173		- int (iospace_config)(struct qla_hw_data);
	3314	+ int (iospace_config)(struct qla_hw_data );
3174	3315	int (initialize_adapter)(struct scsi_qla_host );
3175	3316	};
3176	3317
..	..	@@ -3184,6 +3325,7 @@
3184	3325	#define QLA_MSIX_RSP_Q 0x01
3185	3326	#define QLA_ATIO_VECTOR 0x02
3186	3327	#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
	3328	+#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
3187	3329
3188	3330	#define QLA_MIDX_DEFAULT 0
3189	3331	#define QLA_MIDX_RSP_Q 1
..	..	@@ -3213,12 +3355,9 @@
3213	3355	QLA_EVT_IDC_ACK,
3214	3356	QLA_EVT_ASYNC_LOGIN,
3215	3357	QLA_EVT_ASYNC_LOGOUT,
3216		- QLA_EVT_ASYNC_LOGOUT_DONE,
3217	3358	QLA_EVT_ASYNC_ADISC,
3218		- QLA_EVT_ASYNC_ADISC_DONE,
3219	3359	QLA_EVT_UEVENT,
3220	3360	QLA_EVT_AENFX,
3221		- QLA_EVT_GIDPN,
3222	3361	QLA_EVT_GPNID,
3223	3362	QLA_EVT_UNMAP,
3224	3363	QLA_EVT_NEW_SESS,
..	..	@@ -3361,7 +3500,8 @@
3361	3500	#define QLA_MQ_SIZE 32
3362	3501	#define QLA_MAX_QUEUES 256
3363	3502	#define ISP_QUE_REG(ha, id) \
3364		- ((ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) ? \
	3503	+ ((ha->mqenable \|\| IS_QLA83XX(ha) \|\| \
	3504	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) ? \
3365	3505	((void __iomem )ha->mqiobase + (QLA_QUE_PAGE id)) :\
3366	3506	((void __iomem *)ha->iobase))
3367	3507	#define QLA_REQ_QUE_ID(tag) \
..	..	@@ -3383,6 +3523,14 @@
3383	3523	uint64_t num_term_xchg_sent;
3384	3524	};
3385	3525
	3526	+struct qla_counters {
	3527	+ uint64_t input_bytes;
	3528	+ uint64_t input_requests;
	3529	+ uint64_t output_bytes;
	3530	+ uint64_t output_requests;
	3531	+
	3532	+};
	3533	+
3386	3534	struct qla_qpair;
3387	3535
3388	3536	/* Response queue data structure */
..	..	@@ -3390,8 +3538,8 @@
3390	3538	dma_addr_t dma;
3391	3539	response_t *ring;
3392	3540	response_t *ring_ptr;
3393		- uint32_t __iomem rsp_q_in; / FWI2-capable only. */
3394		- uint32_t __iomem *rsp_q_out;
	3541	+ __le32 __iomem rsp_q_in; / FWI2-capable only. */
	3542	+ __le32 __iomem *rsp_q_out;
3395	3543	uint16_t ring_index;
3396	3544	uint16_t out_ptr;
3397	3545	uint16_t in_ptr; / queue shadow in index */
..	..	@@ -3417,8 +3565,8 @@
3417	3565	dma_addr_t dma;
3418	3566	request_t *ring;
3419	3567	request_t *ring_ptr;
3420		- uint32_t __iomem req_q_in; / FWI2-capable only. */
3421		- uint32_t __iomem *req_q_out;
	3568	+ __le32 __iomem req_q_in; / FWI2-capable only. */
	3569	+ __le32 __iomem *req_q_out;
3422	3570	uint16_t ring_index;
3423	3571	uint16_t in_ptr;
3424	3572	uint16_t out_ptr; / queue shadow out index */
..	..	@@ -3440,6 +3588,15 @@
3440	3588	uint16_t length_fx00;
3441	3589	uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3442	3590	};
	3591	+
	3592	+struct qla_fw_resources {
	3593	+ u16 iocbs_total;
	3594	+ u16 iocbs_limit;
	3595	+ u16 iocbs_qp_limit;
	3596	+ u16 iocbs_used;
	3597	+};
	3598	+
	3599	+#define QLA_IOCB_PCT_LIMIT 95
3443	3600
3444	3601	/Queue pair data structure /
3445	3602	struct qla_qpair {
..	..	@@ -3467,6 +3624,7 @@
3467	3624	uint32_t enable_class_2:1;
3468	3625	uint32_t enable_explicit_conf:1;
3469	3626	uint32_t use_shadow_reg:1;
	3627	+ uint32_t rcv_intr:1;
3470	3628
3471	3629	uint16_t id; /* qp number used with FW */
3472	3630	uint16_t vp_idx; /* vport ID */
..	..	@@ -3482,10 +3640,17 @@
3482	3640	struct qla_msix_entry msix; / point to &ha->msix_entries[x] */
3483	3641	struct qla_hw_data *hw;
3484	3642	struct work_struct q_work;
	3643	+ struct qla_counters counters;
	3644	+
3485	3645	struct list_head qp_list_elem; /* vha->qp_list */
3486	3646	struct list_head hints_list;
3487		- uint16_t cpuid;
	3647	+
	3648	+ uint16_t retry_term_cnt;
	3649	+ __le32 retry_term_exchg_addr;
	3650	+ uint64_t retry_term_jiff;
3488	3651	struct qla_tgt_counters tgt_counters;
	3652	+ uint16_t cpuid;
	3653	+ struct qla_fw_resources fwres ____cacheline_aligned;
3489	3654	};
3490	3655
3491	3656	/* Place holder for FW buffer parameters */
..	..	@@ -3494,6 +3659,134 @@
3494	3659	dma_addr_t fw_dma;
3495	3660	uint32_t len;
3496	3661	};
	3662	+
	3663	+struct rdp_req_payload {
	3664	+ uint32_t els_request;
	3665	+ uint32_t desc_list_len;
	3666	+
	3667	+ /* NPIV descriptor */
	3668	+ struct {
	3669	+ uint32_t desc_tag;
	3670	+ uint32_t desc_len;
	3671	+ uint8_t reserved;
	3672	+ uint8_t nport_id[3];
	3673	+ } npiv_desc;
	3674	+};
	3675	+
	3676	+struct rdp_rsp_payload {
	3677	+ struct {
	3678	+ __be32 cmd;
	3679	+ __be32 len;
	3680	+ } hdr;
	3681	+
	3682	+ /* LS Request Info descriptor */
	3683	+ struct {
	3684	+ __be32 desc_tag;
	3685	+ __be32 desc_len;
	3686	+ __be32 req_payload_word_0;
	3687	+ } ls_req_info_desc;
	3688	+
	3689	+ /* LS Request Info descriptor */
	3690	+ struct {
	3691	+ __be32 desc_tag;
	3692	+ __be32 desc_len;
	3693	+ __be32 req_payload_word_0;
	3694	+ } ls_req_info_desc2;
	3695	+
	3696	+ /* SFP diagnostic param descriptor */
	3697	+ struct {
	3698	+ __be32 desc_tag;
	3699	+ __be32 desc_len;
	3700	+ __be16 temperature;
	3701	+ __be16 vcc;
	3702	+ __be16 tx_bias;
	3703	+ __be16 tx_power;
	3704	+ __be16 rx_power;
	3705	+ __be16 sfp_flags;
	3706	+ } sfp_diag_desc;
	3707	+
	3708	+ /* Port Speed Descriptor */
	3709	+ struct {
	3710	+ __be32 desc_tag;
	3711	+ __be32 desc_len;
	3712	+ __be16 speed_capab;
	3713	+ __be16 operating_speed;
	3714	+ } port_speed_desc;
	3715	+
	3716	+ /* Link Error Status Descriptor */
	3717	+ struct {
	3718	+ __be32 desc_tag;
	3719	+ __be32 desc_len;
	3720	+ __be32 link_fail_cnt;
	3721	+ __be32 loss_sync_cnt;
	3722	+ __be32 loss_sig_cnt;
	3723	+ __be32 prim_seq_err_cnt;
	3724	+ __be32 inval_xmit_word_cnt;
	3725	+ __be32 inval_crc_cnt;
	3726	+ uint8_t pn_port_phy_type;
	3727	+ uint8_t reserved[3];
	3728	+ } ls_err_desc;
	3729	+
	3730	+ /* Port name description with diag param */
	3731	+ struct {
	3732	+ __be32 desc_tag;
	3733	+ __be32 desc_len;
	3734	+ uint8_t WWNN[WWN_SIZE];
	3735	+ uint8_t WWPN[WWN_SIZE];
	3736	+ } port_name_diag_desc;
	3737	+
	3738	+ /* Port Name desc for Direct attached Fx_Port or Nx_Port */
	3739	+ struct {
	3740	+ __be32 desc_tag;
	3741	+ __be32 desc_len;
	3742	+ uint8_t WWNN[WWN_SIZE];
	3743	+ uint8_t WWPN[WWN_SIZE];
	3744	+ } port_name_direct_desc;
	3745	+
	3746	+ /* Buffer Credit descriptor */
	3747	+ struct {
	3748	+ __be32 desc_tag;
	3749	+ __be32 desc_len;
	3750	+ __be32 fcport_b2b;
	3751	+ __be32 attached_fcport_b2b;
	3752	+ __be32 fcport_rtt;
	3753	+ } buffer_credit_desc;
	3754	+
	3755	+ /* Optical Element Data Descriptor */
	3756	+ struct {
	3757	+ __be32 desc_tag;
	3758	+ __be32 desc_len;
	3759	+ __be16 high_alarm;
	3760	+ __be16 low_alarm;
	3761	+ __be16 high_warn;
	3762	+ __be16 low_warn;
	3763	+ __be32 element_flags;
	3764	+ } optical_elmt_desc[5];
	3765	+
	3766	+ /* Optical Product Data Descriptor */
	3767	+ struct {
	3768	+ __be32 desc_tag;
	3769	+ __be32 desc_len;
	3770	+ uint8_t vendor_name[16];
	3771	+ uint8_t part_number[16];
	3772	+ uint8_t serial_number[16];
	3773	+ uint8_t revision[4];
	3774	+ uint8_t date[8];
	3775	+ } optical_prod_desc;
	3776	+};
	3777	+
	3778	+#define RDP_DESC_LEN(obj) \
	3779	+ (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
	3780	+
	3781	+#define RDP_PORT_SPEED_1GB BIT_15
	3782	+#define RDP_PORT_SPEED_2GB BIT_14
	3783	+#define RDP_PORT_SPEED_4GB BIT_13
	3784	+#define RDP_PORT_SPEED_10GB BIT_12
	3785	+#define RDP_PORT_SPEED_8GB BIT_11
	3786	+#define RDP_PORT_SPEED_16GB BIT_10
	3787	+#define RDP_PORT_SPEED_32GB BIT_9
	3788	+#define RDP_PORT_SPEED_64GB BIT_8
	3789	+#define RDP_PORT_SPEED_UNKNOWN BIT_0
3497	3790
3498	3791	struct scsi_qlt_host {
3499	3792	void *target_lport_ptr;
..	..	@@ -3511,17 +3804,17 @@
3511	3804	struct atio atio_ring_ptr; / Current address. */
3512	3805	uint16_t atio_ring_index; /* Current index. */
3513	3806	uint16_t atio_q_length;
3514		- uint32_t __iomem *atio_q_in;
3515		- uint32_t __iomem *atio_q_out;
	3807	+ __le32 __iomem *atio_q_in;
	3808	+ __le32 __iomem *atio_q_out;
3516	3809
3517	3810	struct qla_tgt_func_tmpl *tgt_ops;
3518	3811	struct qla_tgt_vp_map *tgt_vp_map;
3519	3812
3520	3813	int saved_set;
3521		- uint16_t saved_exchange_count;
3522		- uint32_t saved_firmware_options_1;
3523		- uint32_t saved_firmware_options_2;
3524		- uint32_t saved_firmware_options_3;
	3814	+ __le16 saved_exchange_count;
	3815	+ __le32 saved_firmware_options_1;
	3816	+ __le32 saved_firmware_options_2;
	3817	+ __le32 saved_firmware_options_3;
3525	3818	uint8_t saved_firmware_options[2];
3526	3819	uint8_t saved_add_firmware_options[2];
3527	3820
..	..	@@ -3551,6 +3844,18 @@
3551	3844
3552	3845	#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3553	3846
	3847	+struct qla_hw_data_stat {
	3848	+ u32 num_fw_dump;
	3849	+ u32 num_mpi_reset;
	3850	+};
	3851	+
	3852	+/* refer to pcie_do_recovery reference */
	3853	+typedef enum {
	3854	+ QLA_PCI_RESUME,
	3855	+ QLA_PCI_ERR_DETECTED,
	3856	+ QLA_PCI_MMIO_ENABLED,
	3857	+ QLA_PCI_SLOT_RESET,
	3858	+} pci_error_state_t;
3554	3859	/*
3555	3860	* Qlogic host adapter specific data structure.
3556	3861	*/
..	..	@@ -3559,6 +3864,7 @@
3559	3864	/* SRB cache. */
3560	3865	#define SRB_MIN_REQ 128
3561	3866	mempool_t *srb_mempool;
	3867	+ u8 port_name[WWN_SIZE];
3562	3868
3563	3869	volatile struct {
3564	3870	uint32_t mbox_int :1;
..	..	@@ -3606,15 +3912,24 @@
3606	3912	uint32_t fw_started:1;
3607	3913	uint32_t fw_init_done:1;
3608	3914
3609		- uint32_t detected_lr_sfp:1;
3610		- uint32_t using_lr_setting:1;
	3915	+ uint32_t lr_detected:1;
	3916	+
3611	3917	uint32_t rida_fmt2:1;
3612	3918	uint32_t purge_mbox:1;
3613	3919	uint32_t n2n_bigger:1;
	3920	+ uint32_t secure_adapter:1;
	3921	+ uint32_t secure_fw:1;
	3922	+ /* Supported by Adapter */
	3923	+ uint32_t scm_supported_a:1;
	3924	+ /* Supported by Firmware */
	3925	+ uint32_t scm_supported_f:1;
	3926	+ /* Enabled in Driver */
	3927	+ uint32_t scm_enabled:1;
	3928	+ uint32_t plogi_template_valid:1;
3614	3929	} flags;
3615	3930
3616	3931	uint16_t max_exchg;
3617		- uint16_t long_range_distance; /* 32G & above */
	3932	+ uint16_t lr_distance; /* 32G & above */
3618	3933	#define LR_DISTANCE_5K 1
3619	3934	#define LR_DISTANCE_10K 0
3620	3935
..	..	@@ -3688,12 +4003,15 @@
3688	4003	#define PORT_SPEED_UNKNOWN 0xFFFF
3689	4004	#define PORT_SPEED_1GB 0x00
3690	4005	#define PORT_SPEED_2GB 0x01
	4006	+#define PORT_SPEED_AUTO 0x02
3691	4007	#define PORT_SPEED_4GB 0x03
3692	4008	#define PORT_SPEED_8GB 0x04
3693	4009	#define PORT_SPEED_16GB 0x05
3694	4010	#define PORT_SPEED_32GB 0x06
	4011	+#define PORT_SPEED_64GB 0x07
3695	4012	#define PORT_SPEED_10GB 0x13
3696	4013	uint16_t link_data_rate; /* F/W operating speed */
	4014	+ uint16_t set_data_rate; /* Set by user */
3697	4015
3698	4016	uint8_t current_topology;
3699	4017	uint8_t prev_topology;
..	..	@@ -3717,6 +4035,11 @@
3717	4035	#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3718	4036	#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3719	4037	#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
	4038	+#define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
	4039	+#define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
	4040	+#define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
	4041	+#define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
	4042	+#define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
3720	4043
3721	4044	uint32_t isp_type;
3722	4045	#define DT_ISP2100 BIT_0
..	..	@@ -3741,7 +4064,12 @@
3741	4064	#define DT_ISP2071 BIT_19
3742	4065	#define DT_ISP2271 BIT_20
3743	4066	#define DT_ISP2261 BIT_21
3744		-#define DT_ISP_LAST (DT_ISP2261 << 1)
	4067	+#define DT_ISP2061 BIT_22
	4068	+#define DT_ISP2081 BIT_23
	4069	+#define DT_ISP2089 BIT_24
	4070	+#define DT_ISP2281 BIT_25
	4071	+#define DT_ISP2289 BIT_26
	4072	+#define DT_ISP_LAST (DT_ISP2289 << 1)
3745	4073
3746	4074	uint32_t device_type;
3747	4075	#define DT_T10_PI BIT_25
..	..	@@ -3776,6 +4104,8 @@
3776	4104	#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3777	4105	#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3778	4106	#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
	4107	+#define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
	4108	+#define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
3779	4109
3780	4110	#define IS_QLA23XX(ha) (IS_QLA2300(ha) \|\| IS_QLA2312(ha) \|\| IS_QLA2322(ha) \|\| \
3781	4111	IS_QLA6312(ha) \|\| IS_QLA6322(ha))
..	..	@@ -3785,6 +4115,7 @@
3785	4115	#define IS_QLA83XX(ha) (IS_QLA2031(ha) \|\| IS_QLA8031(ha))
3786	4116	#define IS_QLA84XX(ha) (IS_QLA8432(ha))
3787	4117	#define IS_QLA27XX(ha) (IS_QLA2071(ha) \|\| IS_QLA2271(ha) \|\| IS_QLA2261(ha))
	4118	+#define IS_QLA28XX(ha) (IS_QLA2081(ha) \|\| IS_QLA2281(ha))
3788	4119	#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) \|\| IS_QLA54XX(ha) \|\| \
3789	4120	IS_QLA84XX(ha))
3790	4121	#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) \|\| IS_QLA82XX(ha) \|\| \
..	..	@@ -3793,14 +4124,15 @@
3793	4124	#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) \|\| IS_QLA84XX(ha) \|\| \
3794	4125	IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\| \
3795	4126	IS_QLA82XX(ha) \|\| IS_QLA83XX(ha) \|\| \
3796		- IS_QLA8044(ha) \|\| IS_QLA27XX(ha))
	4127	+ IS_QLA8044(ha) \|\| IS_QLA27XX(ha) \|\| \
	4128	+ IS_QLA28XX(ha))
3797	4129	#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| \
3798		- IS_QLA27XX(ha))
	4130	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
3799	4131	#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3800	4132	#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| \
3801		- IS_QLA27XX(ha))
	4133	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
3802	4134	#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| \
3803		- IS_QLA27XX(ha))
	4135	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
3804	4136	#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) \|\| IS_FWI2_CAPABLE(ha))
3805	4137
3806	4138	#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
..	..	@@ -3810,29 +4142,39 @@
3810	4142	#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3811	4143	#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3812	4144	#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3813		-#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable \|\| IS_QLA83XX(ha) \|\| \
3814		- IS_QLA27XX(ha))
3815		-#define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) \|\| IS_QLA2031(ha)))
	4145	+#define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| \
	4146	+ IS_QLA28XX(ha))
	4147	+#define IS_BIDI_CAPABLE(ha) \
	4148	+ (IS_QLA25XX(ha) \|\| IS_QLA2031(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
3816	4149	/* Bit 21 of fw_attributes decides the MCTP capabilities */
3817	4150	#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3818	4151	((ha)->fw_attributes_ext[0] & BIT_0))
3819	4152	#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
3820	4153	#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
3821	4154	#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3822		-#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4155	+#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| \
	4156	+ IS_QLA28XX(ha))
3823	4157	#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3824	4158	(((ha)->fw_attributes_h << 16 \| (ha)->fw_attributes) & BIT_22))
3825		-#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4159	+#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| \
	4160	+ IS_QLA28XX(ha))
3826	4161	#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3827		-#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3828		-#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
3829		-#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4162	+#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	4163	+#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| \
	4164	+ IS_QLA28XX(ha))
	4165	+#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| \
	4166	+ IS_QLA28XX(ha))
3830	4167	#define IS_EXCHG_OFFLD_CAPABLE(ha) \
3831		- (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4168	+ (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
3832	4169	#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3833		- (IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4170	+ (IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| \
	4171	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
3834	4172	#define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\|\
3835		- IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4173	+ IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	4174	+
	4175	+#define IS_ZIO_THRESHOLD_CAPABLE(ha) \
	4176	+ ((IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) &&\
	4177	+ (ha->zio_mode == QLA_ZIO_MODE_6))
3836	4178
3837	4179	/* HBA serial number */
3838	4180	uint8_t serial0;
..	..	@@ -3841,7 +4183,7 @@
3841	4183
3842	4184	/* NVRAM configuration data */
3843	4185	#define MAX_NVRAM_SIZE 4096
3844		-#define VPD_OFFSET MAX_NVRAM_SIZE / 2
	4186	+#define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
3845	4187	uint16_t nvram_size;
3846	4188	uint16_t nvram_base;
3847	4189	void *nvram;
..	..	@@ -3858,7 +4200,6 @@
3858	4200	uint8_t aen_mbx_count;
3859	4201	atomic_t num_pend_mbx_stage1;
3860	4202	atomic_t num_pend_mbx_stage2;
3861		- atomic_t num_pend_mbx_stage3;
3862	4203	uint16_t frame_payload_size;
3863	4204
3864	4205	uint32_t login_retry_count;
..	..	@@ -3873,8 +4214,13 @@
3873	4214
3874	4215	#define SFP_DEV_SIZE 512
3875	4216	#define SFP_BLOCK_SIZE 64
	4217	+#define SFP_RTDI_LEN SFP_BLOCK_SIZE
	4218	+
3876	4219	void *sfp_data;
3877	4220	dma_addr_t sfp_data_dma;
	4221	+
	4222	+ struct qla_flt_header *flt;
	4223	+ dma_addr_t flt_dma;
3878	4224
3879	4225	#define XGMAC_DATA_SIZE 4096
3880	4226	void *xgmac_data;
..	..	@@ -3900,6 +4246,13 @@
3900	4246	int init_cb_size;
3901	4247	dma_addr_t ex_init_cb_dma;
3902	4248	struct ex_init_cb_81xx *ex_init_cb;
	4249	+ dma_addr_t sf_init_cb_dma;
	4250	+ struct init_sf_cb *sf_init_cb;
	4251	+
	4252	+ void *scm_fpin_els_buff;
	4253	+ uint64_t scm_fpin_els_buff_size;
	4254	+ bool scm_fpin_valid;
	4255	+ bool scm_fpin_payload_size;
3903	4256
3904	4257	void *async_pd;
3905	4258	dma_addr_t async_pd_dma;
..	..	@@ -3909,7 +4262,7 @@
3909	4262	/* Extended Logins */
3910	4263	void *exlogin_buf;
3911	4264	dma_addr_t exlogin_buf_dma;
3912		- int exlogin_size;
	4265	+ uint32_t exlogin_size;
3913	4266
3914	4267	#define ENABLE_EXCHANGE_OFFLD BIT_2
3915	4268
..	..	@@ -3920,7 +4273,8 @@
3920	4273	int exchoffld_count;
3921	4274
3922	4275	/* n2n */
3923		- struct els_plogi_payload plogi_els_payld;
	4276	+ struct fc_els_flogi plogi_els_payld;
	4277	+#define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
3924	4278
3925	4279	void *swl;
3926	4280
..	..	@@ -3958,6 +4312,17 @@
3958	4312	uint16_t fw_subminor_version;
3959	4313	uint16_t fw_attributes;
3960	4314	uint16_t fw_attributes_h;
	4315	+#define FW_ATTR_H_NVME_FBURST BIT_1
	4316	+#define FW_ATTR_H_NVME BIT_10
	4317	+#define FW_ATTR_H_NVME_UPDATED BIT_14
	4318	+
	4319	+ /* About firmware SCM support */
	4320	+#define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
	4321	+ /* Brocade fabric attached */
	4322	+#define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
	4323	+ /* Cisco fabric attached */
	4324	+#define FW_ATTR_EXT0_SCM_CISCO 0x00002000
	4325	+#define FW_ATTR_EXT0_NVME2 BIT_13
3961	4326	uint16_t fw_attributes_ext[2];
3962	4327	uint32_t fw_memory_size;
3963	4328	uint32_t fw_transfer_size;
..	..	@@ -3981,20 +4346,24 @@
3981	4346
3982	4347	uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3983	4348	uint8_t fw_seriallink_options[4];
3984		- uint16_t fw_seriallink_options24[4];
	4349	+ __le16 fw_seriallink_options24[4];
3985	4350
	4351	+ uint8_t serdes_version[3];
3986	4352	uint8_t mpi_version[3];
3987	4353	uint32_t mpi_capabilities;
3988	4354	uint8_t phy_version[3];
3989	4355	uint8_t pep_version[3];
3990	4356
3991	4357	/* Firmware dump template */
3992		- void *fw_dump_template;
3993		- uint32_t fw_dump_template_len;
3994		- /* Firmware dump information. */
	4358	+ struct fwdt {
	4359	+ void *template;
	4360	+ ulong length;
	4361	+ ulong dump_size;
	4362	+ } fwdt[2];
3995	4363	struct qla2xxx_fw_dump *fw_dump;
3996	4364	uint32_t fw_dump_len;
3997		- int fw_dumped;
	4365	+ u32 fw_dump_alloc_len;
	4366	+ bool fw_dumped;
3998	4367	unsigned long fw_dump_cap_flags;
3999	4368	#define RISC_PAUSE_CMPL 0
4000	4369	#define DMA_SHUTDOWN_CMPL 1
..	..	@@ -4005,6 +4374,10 @@
4005	4374	#define ISP_MBX_RDY 6
4006	4375	#define ISP_SOFT_RESET_CMPL 7
4007	4376	int fw_dump_reading;
	4377	+ void *mpi_fw_dump;
	4378	+ u32 mpi_fw_dump_len;
	4379	+ unsigned int mpi_fw_dump_reading:1;
	4380	+ unsigned int mpi_fw_dumped:1;
4008	4381	int prev_minidump_failed;
4009	4382	dma_addr_t eft_dma;
4010	4383	void *eft;
..	..	@@ -4033,7 +4406,6 @@
4033	4406	uint16_t product_id[4];
4034	4407
4035	4408	uint8_t model_number[16+1];
4036		-#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
4037	4409	char model_desc[80];
4038	4410	uint8_t adapter_id[16+1];
4039	4411
..	..	@@ -4073,22 +4445,28 @@
4073	4445	uint32_t fdt_protect_sec_cmd;
4074	4446	uint32_t fdt_wrt_sts_reg_cmd;
4075	4447
4076		- uint32_t flt_region_flt;
4077		- uint32_t flt_region_fdt;
4078		- uint32_t flt_region_boot;
4079		- uint32_t flt_region_boot_sec;
4080		- uint32_t flt_region_fw;
4081		- uint32_t flt_region_fw_sec;
4082		- uint32_t flt_region_vpd_nvram;
4083		- uint32_t flt_region_vpd;
4084		- uint32_t flt_region_vpd_sec;
4085		- uint32_t flt_region_nvram;
4086		- uint32_t flt_region_npiv_conf;
4087		- uint32_t flt_region_gold_fw;
4088		- uint32_t flt_region_fcp_prio;
4089		- uint32_t flt_region_bootload;
4090		- uint32_t flt_region_img_status_pri;
4091		- uint32_t flt_region_img_status_sec;
	4448	+ struct {
	4449	+ uint32_t flt_region_flt;
	4450	+ uint32_t flt_region_fdt;
	4451	+ uint32_t flt_region_boot;
	4452	+ uint32_t flt_region_boot_sec;
	4453	+ uint32_t flt_region_fw;
	4454	+ uint32_t flt_region_fw_sec;
	4455	+ uint32_t flt_region_vpd_nvram;
	4456	+ uint32_t flt_region_vpd_nvram_sec;
	4457	+ uint32_t flt_region_vpd;
	4458	+ uint32_t flt_region_vpd_sec;
	4459	+ uint32_t flt_region_nvram;
	4460	+ uint32_t flt_region_nvram_sec;
	4461	+ uint32_t flt_region_npiv_conf;
	4462	+ uint32_t flt_region_gold_fw;
	4463	+ uint32_t flt_region_fcp_prio;
	4464	+ uint32_t flt_region_bootload;
	4465	+ uint32_t flt_region_img_status_pri;
	4466	+ uint32_t flt_region_img_status_sec;
	4467	+ uint32_t flt_region_aux_img_status_pri;
	4468	+ uint32_t flt_region_aux_img_status_sec;
	4469	+ };
4092	4470	uint8_t active_image;
4093	4471
4094	4472	/* Needed for BEACON */
..	..	@@ -4151,7 +4529,7 @@
4151	4529	#define NUM_DSD_CHAIN 4096
4152	4530
4153	4531	uint8_t fw_type;
4154		- __le32 file_prd_off; /* File firmware product offset */
	4532	+ uint32_t file_prd_off; /* File firmware product offset */
4155	4533
4156	4534	uint32_t md_template_size;
4157	4535	void *md_tmplt_hdr;
..	..	@@ -4181,11 +4559,51 @@
4181	4559	struct qlt_hw_data tgt;
4182	4560	int allow_cna_fw_dump;
4183	4561	uint32_t fw_ability_mask;
4184		- uint16_t min_link_speed;
4185		- uint16_t max_speed_sup;
	4562	+ uint16_t min_supported_speed;
	4563	+ uint16_t max_supported_speed;
	4564	+
	4565	+ /* DMA pool for the DIF bundling buffers */
	4566	+ struct dma_pool *dif_bundl_pool;
	4567	+ #define DIF_BUNDLING_DMA_POOL_SIZE 1024
	4568	+ struct {
	4569	+ struct {
	4570	+ struct list_head head;
	4571	+ uint count;
	4572	+ } good;
	4573	+ struct {
	4574	+ struct list_head head;
	4575	+ uint count;
	4576	+ } unusable;
	4577	+ } pool;
	4578	+
	4579	+ unsigned long long dif_bundle_crossed_pages;
	4580	+ unsigned long long dif_bundle_reads;
	4581	+ unsigned long long dif_bundle_writes;
	4582	+ unsigned long long dif_bundle_kallocs;
	4583	+ unsigned long long dif_bundle_dma_allocs;
4186	4584
4187	4585	atomic_t nvme_active_aen_cnt;
4188	4586	uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
	4587	+
	4588	+ uint8_t fc4_type_priority;
	4589	+
	4590	+ atomic_t zio_threshold;
	4591	+ uint16_t last_zio_threshold;
	4592	+
	4593	+#define DEFAULT_ZIO_THRESHOLD 5
	4594	+
	4595	+ struct qla_hw_data_stat stat;
	4596	+ pci_error_state_t pci_error_state;
	4597	+};
	4598	+
	4599	+struct active_regions {
	4600	+ uint8_t global;
	4601	+ struct {
	4602	+ uint8_t board_config;
	4603	+ uint8_t vpd_nvram;
	4604	+ uint8_t npiv_config_0_1;
	4605	+ uint8_t npiv_config_2_3;
	4606	+ } aux;
4189	4607	};
4190	4608
4191	4609	#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
..	..	@@ -4193,6 +4611,35 @@
4193	4611	#define FW_ABILITY_MAX_SPEED_32G 0x1
4194	4612	#define FW_ABILITY_MAX_SPEED(ha) \
4195	4613	(ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
	4614	+
	4615	+#define QLA_GET_DATA_RATE 0
	4616	+#define QLA_SET_DATA_RATE_NOLR 1
	4617	+#define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
	4618	+
	4619	+#define QLA_DEFAULT_PAYLOAD_SIZE 64
	4620	+/*
	4621	+ * This item might be allocated with a size > sizeof(struct purex_item).
	4622	+ * The "size" variable gives the size of the payload (which
	4623	+ * is variable) starting at "iocb".
	4624	+ */
	4625	+struct purex_item {
	4626	+ struct list_head list;
	4627	+ struct scsi_qla_host *vha;
	4628	+ void (process_item)(struct scsi_qla_host vha,
	4629	+ struct purex_item *pkt);
	4630	+ atomic_t in_use;
	4631	+ uint16_t size;
	4632	+ struct {
	4633	+ uint8_t iocb[64];
	4634	+ } iocb;
	4635	+};
	4636	+
	4637	+#define SCM_FLAG_RDF_REJECT 0x00
	4638	+#define SCM_FLAG_RDF_COMPLETED 0x01
	4639	+
	4640	+#define QLA_CON_PRIMITIVE_RECEIVED 0x1
	4641	+#define QLA_CONGESTION_ARB_WARNING 0x1
	4642	+#define QLA_CONGESTION_ARB_ALARM 0X2
4196	4643
4197	4644	/*
4198	4645	* Qlogic scsi host structure
..	..	@@ -4225,6 +4672,8 @@
4225	4672	uint32_t qpairs_req_created:1;
4226	4673	uint32_t qpairs_rsp_created:1;
4227	4674	uint32_t nvme_enabled:1;
	4675	+ uint32_t nvme_first_burst:1;
	4676	+ uint32_t nvme2_enabled:1;
4228	4677	} flags;
4229	4678
4230	4679	atomic_t loop_state;
..	..	@@ -4265,10 +4714,15 @@
4265	4714	#define FX00_CRITEMP_RECOVERY 25
4266	4715	#define FX00_HOST_INFO_RESEND 26
4267	4716	#define QPAIR_ONLINE_CHECK_NEEDED 27
4268		-#define SET_ZIO_THRESHOLD_NEEDED 28
	4717	+#define DO_EEH_RECOVERY 28
4269	4718	#define DETECT_SFP_CHANGE 29
4270	4719	#define N2N_LOGIN_NEEDED 30
4271	4720	#define IOCB_WORK_ACTIVE 31
	4721	+#define SET_ZIO_THRESHOLD_NEEDED 32
	4722	+#define ISP_ABORT_TO_ROM 33
	4723	+#define VPORT_DELETE 34
	4724	+
	4725	+#define PROCESS_PUREX_IOCB 63
4272	4726
4273	4727	unsigned long pci_flags;
4274	4728	#define PFLG_DISCONNECTED 0 /* PCI device removed */
..	..	@@ -4307,10 +4761,10 @@
4307	4761	uint8_t node_name[WWN_SIZE];
4308	4762	uint8_t port_name[WWN_SIZE];
4309	4763	uint8_t fabric_node_name[WWN_SIZE];
	4764	+ uint8_t fabric_port_name[WWN_SIZE];
4310	4765
4311	4766	struct nvme_fc_local_port *nvme_local_port;
4312	4767	struct completion nvme_del_done;
4313		- struct list_head nvme_rport_list;
4314	4768
4315	4769	uint16_t fcoe_vlan_id;
4316	4770	uint16_t fcoe_fcf_idx;
..	..	@@ -4371,28 +4825,54 @@
4371	4825	atomic_t vref_count;
4372	4826	struct qla8044_reset_template reset_tmplt;
4373	4827	uint16_t bbcr;
	4828	+
	4829	+ uint16_t u_ql2xexchoffld;
	4830	+ uint16_t u_ql2xiniexchg;
	4831	+ uint16_t qlini_mode;
	4832	+ uint16_t ql2xexchoffld;
	4833	+ uint16_t ql2xiniexchg;
	4834	+
	4835	+ struct dentry *dfs_rport_root;
	4836	+
	4837	+ struct purex_list {
	4838	+ struct list_head head;
	4839	+ spinlock_t lock;
	4840	+ } purex_list;
	4841	+ struct purex_item default_item;
	4842	+
4374	4843	struct name_list_extended gnl;
4375	4844	/* Count of active session/fcport */
4376	4845	int fcport_count;
4377	4846	wait_queue_head_t fcport_waitQ;
4378	4847	wait_queue_head_t vref_waitq;
4379		- uint8_t min_link_speed_feat;
	4848	+ uint8_t min_supported_speed;
4380	4849	uint8_t n2n_node_name[WWN_SIZE];
4381	4850	uint8_t n2n_port_name[WWN_SIZE];
4382	4851	uint16_t n2n_id;
	4852	+ __le16 dport_data[4];
4383	4853	struct list_head gpnid_list;
4384	4854	struct fab_scan scan;
	4855	+ uint8_t scm_fabric_connection_flags;
	4856	+
	4857	+ unsigned int irq_offset;
4385	4858	} scsi_qla_host_t;
4386	4859
4387	4860	struct qla27xx_image_status {
4388	4861	uint8_t image_status_mask;
4389		- uint16_t generation_number;
4390		- uint8_t reserved[3];
4391		- uint8_t ver_minor;
	4862	+ __le16 generation;
4392	4863	uint8_t ver_major;
4393		- uint32_t checksum;
4394		- uint32_t signature;
	4864	+ uint8_t ver_minor;
	4865	+ uint8_t bitmap; /* 28xx only */
	4866	+ uint8_t reserved[2];
	4867	+ __le32 checksum;
	4868	+ __le32 signature;
4395	4869	} __packed;
	4870	+
	4871	+/* 28xx aux image status bimap values */
	4872	+#define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
	4873	+#define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
	4874	+#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
	4875	+#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4396	4876
4397	4877	#define SET_VP_IDX 1
4398	4878	#define SET_AL_PA 2
..	..	@@ -4439,6 +4919,24 @@
4439	4919	_ha->queue_pair_map[i]->fw_started = 0; \
4440	4920	} \
4441	4921	}
	4922	+
	4923	+
	4924	+#define SFUB_CHECKSUM_SIZE 4
	4925	+
	4926	+struct secure_flash_update_block {
	4927	+ uint32_t block_info;
	4928	+ uint32_t signature_lo;
	4929	+ uint32_t signature_hi;
	4930	+ uint32_t signature_upper[0x3e];
	4931	+};
	4932	+
	4933	+struct secure_flash_update_block_pk {
	4934	+ uint32_t block_info;
	4935	+ uint32_t signature_lo;
	4936	+ uint32_t signature_hi;
	4937	+ uint32_t signature_upper[0x3e];
	4938	+ uint32_t public_key[0x41];
	4939	+};
4442	4940
4443	4941	/*
4444	4942	* Macros to help code, maintain, etc.
..	..	@@ -4527,6 +5025,7 @@
4527	5025	#define QLA_SUSPENDED 0x106
4528	5026	#define QLA_BUSY 0x107
4529	5027	#define QLA_ALREADY_REGISTERED 0x109
	5028	+#define QLA_OS_TIMER_EXPIRED 0x10a
4530	5029
4531	5030	#define NVRAM_DELAY() udelay(10)
4532	5031
..	..	@@ -4540,6 +5039,7 @@
4540	5039	#define OPTROM_SIZE_81XX 0x400000
4541	5040	#define OPTROM_SIZE_82XX 0x800000
4542	5041	#define OPTROM_SIZE_83XX 0x1000000
	5042	+#define OPTROM_SIZE_28XX 0x2000000
4543	5043
4544	5044	#define OPTROM_BURST_SIZE 0x1000
4545	5045	#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
..	..	@@ -4633,13 +5133,19 @@
4633	5133	u8 resv2[128];
4634	5134	};
4635	5135
4636		-#define AUTO_DETECT_SFP_SUPPORT(_vha)\
4637		- (ql2xautodetectsfp && !_vha->vp_idx && \
4638		- (IS_QLA25XX(_vha->hw) \|\| IS_QLA81XX(_vha->hw) \|\|\
4639		- IS_QLA83XX(_vha->hw) \|\| IS_QLA27XX(_vha->hw)))
	5136	+/* BPM -- Buffer Plus Management support. */
	5137	+#define IS_BPM_CAPABLE(ha) \
	5138	+ (IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| \
	5139	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	5140	+#define IS_BPM_RANGE_CAPABLE(ha) \
	5141	+ (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	5142	+#define IS_BPM_ENABLED(vha) \
	5143	+ (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
	5144	+
	5145	+#define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
4640	5146
4641	5147	#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4642		- (IS_QLA27XX(_ha) \|\| IS_QLA83XX(_ha)))
	5148	+ (IS_QLA27XX(_ha) \|\| IS_QLA28XX(_ha) \|\| IS_QLA83XX(_ha)))
4643	5149
4644	5150	#define SAVE_TOPO(_ha) { \
4645	5151	if (_ha->current_topology) \
..	..	@@ -4651,8 +5157,34 @@
4651	5157	ha->current_topology == ISP_CFG_N \|\| \
4652	5158	!ha->current_topology)
4653	5159
	5160	+#define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */
	5161	+
	5162	+#define NVME_TYPE(fcport) \
	5163	+ (fcport->fc4_type & FS_FC4TYPE_NVME) \
	5164	+
	5165	+#define FCP_TYPE(fcport) \
	5166	+ (fcport->fc4_type & FS_FC4TYPE_FCP) \
	5167	+
	5168	+#define NVME_ONLY_TARGET(fcport) \
	5169	+ (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
	5170	+
	5171	+#define NVME_FCP_TARGET(fcport) \
	5172	+ (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
	5173	+
	5174	+#define NVME_TARGET(ha, fcport) \
	5175	+ ((NVME_FCP_TARGET(fcport) && \
	5176	+ (ha->fc4_type_priority == FC4_PRIORITY_NVME)) \|\| \
	5177	+ NVME_ONLY_TARGET(fcport)) \
	5178	+
	5179	+#define PRLI_PHASE(_cls) \
	5180	+ ((_cls == DSC_LS_PRLI_PEND) \|\| (_cls == DSC_LS_PRLI_COMP))
	5181	+
4654	5182	#include "qla_target.h"
4655	5183	#include "qla_gbl.h"
4656	5184	#include "qla_dbg.h"
4657	5185	#include "qla_inline.h"
	5186	+
	5187	+#define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND \|\| \
	5188	+ _fcport->disc_state == DSC_DELETED)
	5189	+
4658	5190	#endif