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2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
....@@ -1,12 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2015 Linaro Ltd.
34  * Copyright (c) 2015 Hisilicon Limited.
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
105  */
116 
127 #include "hisi_sas.h"
....@@ -406,8 +401,6 @@
406401 	TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */
407402 };
408403 
409
-#define HISI_SAS_COMMAND_ENTRIES_V1_HW 8192
410
-
411404 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
412405 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
413406 #define HISI_SAS_FATAL_INT_NR (2)
....@@ -421,13 +414,6 @@
421414 	void __iomem *regs = hisi_hba->regs + off;
422415 
423416 	return readl(regs);
424
-}
425
-
426
-static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
427
-{
428
-	void __iomem *regs = hisi_hba->regs + off;
429
-
430
-	return readl_relaxed(regs);
431417 }
432418 
433419 static void hisi_sas_write32(struct hisi_hba *hisi_hba,
....@@ -510,6 +496,7 @@
510496 	struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
511497 	struct asd_sas_port *sas_port = device->port;
512498 	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
499
+	u64 sas_addr;
513500 
514501 	memset(itct, 0, sizeof(*itct));
515502 
....@@ -534,8 +521,8 @@
534521 	itct->qw0 = cpu_to_le64(qw0);
535522 
536523 	/* qw1 */
537
-	memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
538
-	itct->sas_addr = __swab64(itct->sas_addr);
524
+	memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
525
+	itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
539526 
540527 	/* qw2 */
541528 	itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
....@@ -544,8 +531,8 @@
544531 				(0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF));
545532 }
546533 
547
-static void clear_itct_v1_hw(struct hisi_hba *hisi_hba,
548
-			      struct hisi_sas_device *sas_dev)
534
+static int clear_itct_v1_hw(struct hisi_hba *hisi_hba,
535
+			    struct hisi_sas_device *sas_dev)
549536 {
550537 	u64 dev_id = sas_dev->device_id;
551538 	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
....@@ -561,9 +548,11 @@
561548 	reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
562549 	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
563550 
564
-	qw0 = cpu_to_le64(itct->qw0);
551
+	qw0 = le64_to_cpu(itct->qw0);
565552 	qw0 &= ~ITCT_HDR_VALID_MSK;
566553 	itct->qw0 = cpu_to_le64(qw0);
554
+
555
+	return 0;
567556 }
568557 
569558 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
....@@ -763,7 +752,7 @@
763752 
764753 	rc = reset_hw_v1_hw(hisi_hba);
765754 	if (rc) {
766
-		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
755
+		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
767756 		return rc;
768757 	}
769758 
....@@ -797,16 +786,11 @@
797786 	enable_phy_v1_hw(hisi_hba, phy_no);
798787 }
799788 
800
-static void stop_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
801
-{
802
-	disable_phy_v1_hw(hisi_hba, phy_no);
803
-}
804
-
805789 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
806790 {
807
-	stop_phy_v1_hw(hisi_hba, phy_no);
791
+	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
808792 	msleep(100);
809
-	start_phy_v1_hw(hisi_hba, phy_no);
793
+	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
810794 }
811795 
812796 static void start_phys_v1_hw(struct timer_list *t)
....@@ -816,7 +800,7 @@
816800 
817801 	for (i = 0; i < hisi_hba->n_phy; i++) {
818802 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
819
-		start_phy_v1_hw(hisi_hba, i);
803
+		hisi_sas_phy_enable(hisi_hba, i, 1);
820804 	}
821805 }
822806 
....@@ -873,30 +857,6 @@
873857 			bitmap |= 1 << i;
874858 
875859 	return bitmap;
876
-}
877
-
878
-/*
879
- * The callpath to this function and upto writing the write
880
- * queue pointer should be safe from interruption.
881
- */
882
-static int
883
-get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
884
-{
885
-	struct device *dev = hisi_hba->dev;
886
-	int queue = dq->id;
887
-	u32 r, w;
888
-
889
-	w = dq->wr_point;
890
-	r = hisi_sas_read32_relaxed(hisi_hba,
891
-				DLVRY_Q_0_RD_PTR + (queue * 0x14));
892
-	if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
893
-		dev_warn(dev, "could not find free slot\n");
894
-		return -EAGAIN;
895
-	}
896
-
897
-	dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
898
-
899
-	return w;
900860 }
901861 
902862 /* DQ lock must be taken here */
....@@ -1100,7 +1060,7 @@
11001060 	case SAS_PROTOCOL_SSP:
11011061 	{
11021062 		int error = -1;
1103
-		u32 dma_err_type = cpu_to_le32(err_record->dma_err_type);
1063
+		u32 dma_err_type = le32_to_cpu(err_record->dma_err_type);
11041064 		u32 dma_tx_err_type = ((dma_err_type &
11051065 					ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
11061066 					ERR_HDR_DMA_TX_ERR_TYPE_OFF;
....@@ -1108,9 +1068,9 @@
11081068 					ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
11091069 					ERR_HDR_DMA_RX_ERR_TYPE_OFF;
11101070 		u32 trans_tx_fail_type =
1111
-				cpu_to_le32(err_record->trans_tx_fail_type);
1071
+				le32_to_cpu(err_record->trans_tx_fail_type);
11121072 		u32 trans_rx_fail_type =
1113
-				cpu_to_le32(err_record->trans_rx_fail_type);
1073
+				le32_to_cpu(err_record->trans_rx_fail_type);
11141074 
11151075 		if (dma_tx_err_type) {
11161076 			/* dma tx err */
....@@ -1192,21 +1152,21 @@
11921152 		}
11931153 		default:
11941154 		{
1195
-			ts->stat = SAM_STAT_CHECK_CONDITION;
1155
+			ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
11961156 			break;
11971157 		}
11981158 		}
11991159 	}
12001160 		break;
12011161 	case SAS_PROTOCOL_SMP:
1202
-		ts->stat = SAM_STAT_CHECK_CONDITION;
1162
+		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
12031163 		break;
12041164 
12051165 	case SAS_PROTOCOL_SATA:
12061166 	case SAS_PROTOCOL_STP:
12071167 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
12081168 	{
1209
-		dev_err(dev, "slot err: SATA/STP not supported");
1169
+		dev_err(dev, "slot err: SATA/STP not supported\n");
12101170 	}
12111171 		break;
12121172 	default:
....@@ -1215,15 +1175,14 @@
12151175 
12161176 }
12171177 
1218
-static int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
1219
-			       struct hisi_sas_slot *slot)
1178
+static void slot_complete_v1_hw(struct hisi_hba *hisi_hba,
1179
+				struct hisi_sas_slot *slot)
12201180 {
12211181 	struct sas_task *task = slot->task;
12221182 	struct hisi_sas_device *sas_dev;
12231183 	struct device *dev = hisi_hba->dev;
12241184 	struct task_status_struct *ts;
12251185 	struct domain_device *device;
1226
-	enum exec_status sts;
12271186 	struct hisi_sas_complete_v1_hdr *complete_queue =
12281187 			hisi_hba->complete_hdr[slot->cmplt_queue];
12291188 	struct hisi_sas_complete_v1_hdr *complete_hdr;
....@@ -1234,7 +1193,7 @@
12341193 	cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
12351194 
12361195 	if (unlikely(!task || !task->lldd_task || !task->dev))
1237
-		return -EINVAL;
1196
+		return;
12381197 
12391198 	ts = &task->task_status;
12401199 	device = task->dev;
....@@ -1259,35 +1218,35 @@
12591218 		u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO);
12601219 
12611220 		if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK)
1262
-			dev_err(dev, "slot complete: [%d:%d] has dq IPTT err",
1221
+			dev_err(dev, "slot complete: [%d:%d] has dq IPTT err\n",
12631222 				slot->cmplt_queue, slot->cmplt_queue_slot);
12641223 
12651224 		if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK)
1266
-			dev_err(dev, "slot complete: [%d:%d] has dq type err",
1225
+			dev_err(dev, "slot complete: [%d:%d] has dq type err\n",
12671226 				slot->cmplt_queue, slot->cmplt_queue_slot);
12681227 
12691228 		if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK)
1270
-			dev_err(dev, "slot complete: [%d:%d] has dq force phy err",
1229
+			dev_err(dev, "slot complete: [%d:%d] has dq force phy err\n",
12711230 				slot->cmplt_queue, slot->cmplt_queue_slot);
12721231 
12731232 		if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK)
1274
-			dev_err(dev, "slot complete: [%d:%d] has dq phy id err",
1233
+			dev_err(dev, "slot complete: [%d:%d] has dq phy id err\n",
12751234 				slot->cmplt_queue, slot->cmplt_queue_slot);
12761235 
12771236 		if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK)
1278
-			dev_err(dev, "slot complete: [%d:%d] has dq abort flag err",
1237
+			dev_err(dev, "slot complete: [%d:%d] has dq abort flag err\n",
12791238 				slot->cmplt_queue, slot->cmplt_queue_slot);
12801239 
12811240 		if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK)
1282
-			dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err",
1241
+			dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err\n",
12831242 				slot->cmplt_queue, slot->cmplt_queue_slot);
12841243 
12851244 		if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK)
1286
-			dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err",
1245
+			dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err\n",
12871246 				slot->cmplt_queue, slot->cmplt_queue_slot);
12881247 
12891248 		if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK)
1290
-			dev_err(dev, "slot complete: [%d:%d] has dq order frame len err",
1249
+			dev_err(dev, "slot complete: [%d:%d] has dq order frame len err\n",
12911250 				slot->cmplt_queue, slot->cmplt_queue_slot);
12921251 
12931252 		ts->stat = SAS_OPEN_REJECT;
....@@ -1299,8 +1258,10 @@
12991258 		!(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
13001259 
13011260 		slot_err_v1_hw(hisi_hba, task, slot);
1302
-		if (unlikely(slot->abort))
1303
-			return ts->stat;
1261
+		if (unlikely(slot->abort)) {
1262
+			sas_task_abort(task);
1263
+			return;
1264
+		}
13041265 		goto out;
13051266 	}
13061267 
....@@ -1317,31 +1278,27 @@
13171278 	}
13181279 	case SAS_PROTOCOL_SMP:
13191280 	{
1320
-		void *to;
13211281 		struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1282
+		void *to = page_address(sg_page(sg_resp));
13221283 
1323
-		ts->stat = SAM_STAT_GOOD;
1324
-		to = kmap_atomic(sg_page(sg_resp));
1284
+		ts->stat = SAS_SAM_STAT_GOOD;
13251285 
1326
-		dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1327
-			     DMA_FROM_DEVICE);
13281286 		dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
13291287 			     DMA_TO_DEVICE);
13301288 		memcpy(to + sg_resp->offset,
13311289 		       hisi_sas_status_buf_addr_mem(slot) +
13321290 		       sizeof(struct hisi_sas_err_record),
1333
-		       sg_dma_len(sg_resp));
1334
-		kunmap_atomic(to);
1291
+		       sg_resp->length);
13351292 		break;
13361293 	}
13371294 	case SAS_PROTOCOL_SATA:
13381295 	case SAS_PROTOCOL_STP:
13391296 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1340
-		dev_err(dev, "slot complete: SATA/STP not supported");
1297
+		dev_err(dev, "slot complete: SATA/STP not supported\n");
13411298 		break;
13421299 
13431300 	default:
1344
-		ts->stat = SAM_STAT_CHECK_CONDITION;
1301
+		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
13451302 		break;
13461303 	}
13471304 
....@@ -1353,12 +1310,9 @@
13531310 
13541311 out:
13551312 	hisi_sas_slot_task_free(hisi_hba, task, slot);
1356
-	sts = ts->stat;
13571313 
13581314 	if (task->task_done)
13591315 		task->task_done(task);
1360
-
1361
-	return sts;
13621316 }
13631317 
13641318 /* Interrupts */
....@@ -1454,7 +1408,6 @@
14541408 	struct hisi_sas_phy *phy = p;
14551409 	struct hisi_hba *hisi_hba = phy->hisi_hba;
14561410 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1457
-	struct sas_ha_struct *sha = &hisi_hba->sha;
14581411 	struct device *dev = hisi_hba->dev;
14591412 	int phy_no = sas_phy->id;
14601413 	u32 irq_value;
....@@ -1463,14 +1416,14 @@
14631416 	irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
14641417 
14651418 	if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
1466
-		dev_err(dev, "bcast: irq_value = %x not set enable bit",
1419
+		dev_err(dev, "bcast: irq_value = %x not set enable bit\n",
14671420 			irq_value);
14681421 		res = IRQ_NONE;
14691422 		goto end;
14701423 	}
14711424 
14721425 	if (!test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1473
-		sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1426
+		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
14741427 
14751428 end:
14761429 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
....@@ -1543,11 +1496,9 @@
15431496 	struct hisi_sas_complete_v1_hdr *complete_queue =
15441497 			(struct hisi_sas_complete_v1_hdr *)
15451498 			hisi_hba->complete_hdr[queue];
1546
-	u32 irq_value, rd_point = cq->rd_point, wr_point;
1499
+	u32 rd_point = cq->rd_point, wr_point;
15471500 
15481501 	spin_lock(&hisi_hba->lock);
1549
-	irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1550
-
15511502 	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
15521503 	wr_point = hisi_sas_read32(hisi_hba,
15531504 			COMPL_Q_0_WR_PTR + (0x14 * queue));
....@@ -1558,7 +1509,7 @@
15581509 		u32 cmplt_hdr_data;
15591510 
15601511 		complete_hdr = &complete_queue[rd_point];
1561
-		cmplt_hdr_data = cpu_to_le32(complete_hdr->data);
1512
+		cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
15621513 		idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
15631514 		      CMPLT_HDR_IPTT_OFF;
15641515 		slot = &hisi_hba->slot_info[idx];
....@@ -1693,20 +1644,18 @@
16931644 		idx = i * HISI_SAS_PHY_INT_NR;
16941645 		for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) {
16951646 			irq = platform_get_irq(pdev, idx);
1696
-			if (!irq) {
1697
-				dev_err(dev,
1698
-					"irq init: fail map phy interrupt %d\n",
1647
+			if (irq < 0) {
1648
+				dev_err(dev, "irq init: fail map phy interrupt %d\n",
16991649 					idx);
1700
-				return -ENOENT;
1650
+				return irq;
17011651 			}
17021652 
17031653 			rc = devm_request_irq(dev, irq, phy_interrupts[j], 0,
17041654 					      DRV_NAME " phy", phy);
17051655 			if (rc) {
1706
-				dev_err(dev, "irq init: could not request "
1707
-					"phy interrupt %d, rc=%d\n",
1656
+				dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n",
17081657 					irq, rc);
1709
-				return -ENOENT;
1658
+				return rc;
17101659 			}
17111660 		}
17121661 	}
....@@ -1714,10 +1663,10 @@
17141663 	idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR;
17151664 	for (i = 0; i < hisi_hba->queue_count; i++, idx++) {
17161665 		irq = platform_get_irq(pdev, idx);
1717
-		if (!irq) {
1666
+		if (irq < 0) {
17181667 			dev_err(dev, "irq init: could not map cq interrupt %d\n",
17191668 				idx);
1720
-			return -ENOENT;
1669
+			return irq;
17211670 		}
17221671 
17231672 		rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0,
....@@ -1725,28 +1674,29 @@
17251674 		if (rc) {
17261675 			dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
17271676 				irq, rc);
1728
-			return -ENOENT;
1677
+			return rc;
17291678 		}
17301679 	}
17311680 
17321681 	idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count;
17331682 	for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) {
17341683 		irq = platform_get_irq(pdev, idx);
1735
-		if (!irq) {
1684
+		if (irq < 0) {
17361685 			dev_err(dev, "irq init: could not map fatal interrupt %d\n",
17371686 				idx);
1738
-			return -ENOENT;
1687
+			return irq;
17391688 		}
17401689 
17411690 		rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
17421691 				      DRV_NAME " fatal", hisi_hba);
17431692 		if (rc) {
1744
-			dev_err(dev,
1745
-				"irq init: could not request fatal interrupt %d, rc=%d\n",
1693
+			dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n",
17461694 				irq, rc);
1747
-			return -ENOENT;
1695
+			return rc;
17481696 		}
17491697 	}
1698
+
1699
+	hisi_hba->cq_nvecs = hisi_hba->queue_count;
17501700 
17511701 	return 0;
17521702 }
....@@ -1797,27 +1747,36 @@
17971747 	return 0;
17981748 }
17991749 
1750
+static struct device_attribute *host_attrs_v1_hw[] = {
1751
+	&dev_attr_phy_event_threshold,
1752
+	NULL
1753
+};
1754
+
18001755 static struct scsi_host_template sht_v1_hw = {
18011756 	.name			= DRV_NAME,
1757
+	.proc_name		= DRV_NAME,
18021758 	.module			= THIS_MODULE,
18031759 	.queuecommand		= sas_queuecommand,
1760
+	.dma_need_drain		= ata_scsi_dma_need_drain,
18041761 	.target_alloc		= sas_target_alloc,
18051762 	.slave_configure	= hisi_sas_slave_configure,
18061763 	.scan_finished		= hisi_sas_scan_finished,
18071764 	.scan_start		= hisi_sas_scan_start,
18081765 	.change_queue_depth	= sas_change_queue_depth,
18091766 	.bios_param		= sas_bios_param,
1810
-	.can_queue		= 1,
18111767 	.this_id		= -1,
1812
-	.sg_tablesize		= SG_ALL,
1768
+	.sg_tablesize		= HISI_SAS_SGE_PAGE_CNT,
18131769 	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
1814
-	.use_clustering		= ENABLE_CLUSTERING,
18151770 	.eh_device_reset_handler = sas_eh_device_reset_handler,
18161771 	.eh_target_reset_handler = sas_eh_target_reset_handler,
18171772 	.slave_alloc		= sas_slave_alloc,
18181773 	.target_destroy		= sas_target_destroy,
18191774 	.ioctl			= sas_ioctl,
1820
-	.shost_attrs		= host_attrs,
1775
+#ifdef CONFIG_COMPAT
1776
+	.compat_ioctl		= sas_ioctl,
1777
+#endif
1778
+	.shost_attrs		= host_attrs_v1_hw,
1779
+	.host_reset             = hisi_sas_host_reset,
18211780 };
18221781 
18231782 static const struct hisi_sas_hw hisi_sas_v1_hw = {
....@@ -1827,9 +1786,7 @@
18271786 	.clear_itct = clear_itct_v1_hw,
18281787 	.prep_smp = prep_smp_v1_hw,
18291788 	.prep_ssp = prep_ssp_v1_hw,
1830
-	.get_free_slot = get_free_slot_v1_hw,
18311789 	.start_delivery = start_delivery_v1_hw,
1832
-	.slot_complete = slot_complete_v1_hw,
18331790 	.phys_init = phys_init_v1_hw,
18341791 	.phy_start = start_phy_v1_hw,
18351792 	.phy_disable = disable_phy_v1_hw,
....@@ -1837,7 +1794,6 @@
18371794 	.phy_set_linkrate = phy_set_linkrate_v1_hw,
18381795 	.phy_get_max_linkrate = phy_get_max_linkrate_v1_hw,
18391796 	.get_wideport_bitmap = get_wideport_bitmap_v1_hw,
1840
-	.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V1_HW,
18411797 	.complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),
18421798 	.sht = &sht_v1_hw,
18431799 };