forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/platform/x86/intel_pmc_core.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
12 /*
23  * Intel Core SoC Power Management Controller Header File
34  *
....@@ -6,20 +7,12 @@
67  *
78  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
89  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
9
- *
10
- * This program is free software; you can redistribute it and/or modify it
11
- * under the terms and conditions of the GNU General Public License,
12
- * version 2, as published by the Free Software Foundation.
13
- *
14
- * This program is distributed in the hope it will be useful, but WITHOUT
15
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
- * more details.
18
- *
1910  */
2011 
2112 #ifndef PMC_CORE_H
2213 #define PMC_CORE_H
14
+
15
+#include <linux/bits.h>
2316 
2417 #define PMC_BASE_ADDR_DEFAULT			0xFE000000
2518 
....@@ -32,11 +25,12 @@
3225 #define SPT_PMC_MTPMC_OFFSET			0x20
3326 #define SPT_PMC_MFPMC_OFFSET			0x38
3427 #define SPT_PMC_LTR_IGNORE_OFFSET		0x30C
28
+#define SPT_PMC_VRIC1_OFFSET			0x31c
3529 #define SPT_PMC_MPHY_CORE_STS_0			0x1143
3630 #define SPT_PMC_MPHY_CORE_STS_1			0x1142
3731 #define SPT_PMC_MPHY_COM_STS_0			0x1155
3832 #define SPT_PMC_MMIO_REG_LEN			0x1000
39
-#define SPT_PMC_SLP_S0_RES_COUNTER_STEP		0x64
33
+#define SPT_PMC_SLP_S0_RES_COUNTER_STEP		0x68
4034 #define PMC_BASE_ADDR_MASK			~(SPT_PMC_MMIO_REG_LEN - 1)
4135 #define MTPMC_MASK				0xffff0000
4236 #define PPFEAR_MAX_NUM_ENTRIES			12
....@@ -44,7 +38,27 @@
4438 #define SPT_PMC_READ_DISABLE_BIT		0x16
4539 #define SPT_PMC_MSG_FULL_STS_BIT		0x18
4640 #define NUM_RETRIES				100
47
-#define NUM_IP_IGN_ALLOWED			17
41
+#define SPT_NUM_IP_IGN_ALLOWED			17
42
+
43
+#define SPT_PMC_LTR_CUR_PLT			0x350
44
+#define SPT_PMC_LTR_CUR_ASLT			0x354
45
+#define SPT_PMC_LTR_SPA				0x360
46
+#define SPT_PMC_LTR_SPB				0x364
47
+#define SPT_PMC_LTR_SATA			0x368
48
+#define SPT_PMC_LTR_GBE				0x36C
49
+#define SPT_PMC_LTR_XHCI			0x370
50
+#define SPT_PMC_LTR_RESERVED			0x374
51
+#define SPT_PMC_LTR_ME				0x378
52
+#define SPT_PMC_LTR_EVA				0x37C
53
+#define SPT_PMC_LTR_SPC				0x380
54
+#define SPT_PMC_LTR_AZ				0x384
55
+#define SPT_PMC_LTR_LPSS			0x38C
56
+#define SPT_PMC_LTR_CAM				0x390
57
+#define SPT_PMC_LTR_SPD				0x394
58
+#define SPT_PMC_LTR_SPE				0x398
59
+#define SPT_PMC_LTR_ESPI			0x39C
60
+#define SPT_PMC_LTR_SCC				0x3A0
61
+#define SPT_PMC_LTR_ISH				0x3A4
4862 
4963 /* Sunrise Point: PGD PFET Enable Ack Status Registers */
5064 enum ppfear_regs {
....@@ -123,18 +137,80 @@
123137 #define SPT_PMC_BIT_MPHY_CMN_LANE2		BIT(2)
124138 #define SPT_PMC_BIT_MPHY_CMN_LANE3		BIT(3)
125139 
126
-/* Cannonlake Power Management Controller register offsets */
127
-#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET      0x193C
128
-#define CNP_PMC_LTR_IGNORE_OFFSET              0x1B0C
129
-#define CNP_PMC_PM_CFG_OFFSET                  0x1818
130
-#define CNP_PMC_SLPS0_DBG_OFFSET		0x10B4
131
-/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
132
-#define CNP_PMC_HOST_PPFEAR0A                  0x1D90
140
+#define SPT_PMC_VRIC1_SLPS0LVEN			BIT(13)
141
+#define SPT_PMC_VRIC1_XTALSDQDIS		BIT(22)
133142 
134
-#define CNP_PMC_MMIO_REG_LEN                   0x2000
135
-#define CNP_PPFEAR_NUM_ENTRIES                 8
136
-#define CNP_PMC_READ_DISABLE_BIT               22
143
+/* Cannonlake Power Management Controller register offsets */
144
+#define CNP_PMC_SLPS0_DBG_OFFSET		0x10B4
145
+#define CNP_PMC_PM_CFG_OFFSET			0x1818
146
+#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET	0x193C
147
+#define CNP_PMC_LTR_IGNORE_OFFSET		0x1B0C
148
+/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
149
+#define CNP_PMC_HOST_PPFEAR0A			0x1D90
150
+
137151 #define CNP_PMC_LATCH_SLPS0_EVENTS		BIT(31)
152
+
153
+#define CNP_PMC_MMIO_REG_LEN			0x2000
154
+#define CNP_PPFEAR_NUM_ENTRIES			8
155
+#define CNP_PMC_READ_DISABLE_BIT		22
156
+#define CNP_NUM_IP_IGN_ALLOWED			19
157
+#define CNP_PMC_LTR_CUR_PLT			0x1B50
158
+#define CNP_PMC_LTR_CUR_ASLT			0x1B54
159
+#define CNP_PMC_LTR_SPA				0x1B60
160
+#define CNP_PMC_LTR_SPB				0x1B64
161
+#define CNP_PMC_LTR_SATA			0x1B68
162
+#define CNP_PMC_LTR_GBE				0x1B6C
163
+#define CNP_PMC_LTR_XHCI			0x1B70
164
+#define CNP_PMC_LTR_RESERVED			0x1B74
165
+#define CNP_PMC_LTR_ME				0x1B78
166
+#define CNP_PMC_LTR_EVA				0x1B7C
167
+#define CNP_PMC_LTR_SPC				0x1B80
168
+#define CNP_PMC_LTR_AZ				0x1B84
169
+#define CNP_PMC_LTR_LPSS			0x1B8C
170
+#define CNP_PMC_LTR_CAM				0x1B90
171
+#define CNP_PMC_LTR_SPD				0x1B94
172
+#define CNP_PMC_LTR_SPE				0x1B98
173
+#define CNP_PMC_LTR_ESPI			0x1B9C
174
+#define CNP_PMC_LTR_SCC				0x1BA0
175
+#define CNP_PMC_LTR_ISH				0x1BA4
176
+#define CNP_PMC_LTR_CNV				0x1BF0
177
+#define CNP_PMC_LTR_EMMC			0x1BF4
178
+#define CNP_PMC_LTR_UFSX2			0x1BF8
179
+
180
+#define LTR_DECODED_VAL				GENMASK(9, 0)
181
+#define LTR_DECODED_SCALE			GENMASK(12, 10)
182
+#define LTR_REQ_SNOOP				BIT(15)
183
+#define LTR_REQ_NONSNOOP			BIT(31)
184
+
185
+#define ICL_PPFEAR_NUM_ENTRIES			9
186
+#define ICL_NUM_IP_IGN_ALLOWED			20
187
+#define ICL_PMC_LTR_WIGIG			0x1BFC
188
+#define ICL_PMC_SLP_S0_RES_COUNTER_STEP		0x64
189
+
190
+#define TGL_NUM_IP_IGN_ALLOWED			22
191
+#define TGL_PMC_SLP_S0_RES_COUNTER_STEP		0x7A
192
+
193
+/*
194
+ * Tigerlake Power Management Controller register offsets
195
+ */
196
+#define TGL_LPM_EN_OFFSET			0x1C78
197
+#define TGL_LPM_RESIDENCY_OFFSET		0x1C80
198
+
199
+/* Tigerlake Low Power Mode debug registers */
200
+#define TGL_LPM_STATUS_OFFSET			0x1C3C
201
+#define TGL_LPM_LIVE_STATUS_OFFSET		0x1C5C
202
+
203
+const char *tgl_lpm_modes[] = {
204
+	"S0i2.0",
205
+	"S0i2.1",
206
+	"S0i2.2",
207
+	"S0i3.0",
208
+	"S0i3.1",
209
+	"S0i3.2",
210
+	"S0i3.3",
211
+	"S0i3.4",
212
+	NULL
213
+};
138214 
139215 struct pmc_bit_map {
140216 	const char *name;
....@@ -148,6 +224,7 @@
148224  * @mphy_sts:		Maps name of MPHY lane to MPHY status lane status bit
149225  * @pll_sts:		Maps name of PLL to corresponding bit status
150226  * @slps0_dbg_maps:	Array of SLP_S0_DBG* registers containing debug info
227
+ * @ltr_show_sts:	Maps PCH IP Names to their MMIO register offsets
151228  * @slp_s0_offset:	PWRMBASE offset to read SLP_S0 residency
152229  * @ltr_ignore_offset:	PWRMBASE offset to read/write LTR ignore bit
153230  * @regmap_length:	Length of memory to map from PWRMBASE address to access
....@@ -162,11 +239,15 @@
162239  * captures them to have a common implementation.
163240  */
164241 struct pmc_reg_map {
165
-	const struct pmc_bit_map *pfear_sts;
242
+	const struct pmc_bit_map **pfear_sts;
166243 	const struct pmc_bit_map *mphy_sts;
167244 	const struct pmc_bit_map *pll_sts;
168245 	const struct pmc_bit_map **slps0_dbg_maps;
246
+	const struct pmc_bit_map *ltr_show_sts;
247
+	const struct pmc_bit_map *msr_sts;
248
+	const struct pmc_bit_map **lpm_sts;
169249 	const u32 slp_s0_offset;
250
+	const int slp_s0_res_counter_step;
170251 	const u32 ltr_ignore_offset;
171252 	const int regmap_length;
172253 	const u32 ppfear0_offset;
....@@ -174,6 +255,14 @@
174255 	const u32 pm_cfg_offset;
175256 	const int pm_read_disable_bit;
176257 	const u32 slps0_dbg_offset;
258
+	const u32 ltr_ignore_max;
259
+	const u32 pm_vric1_offset;
260
+	/* Low Power Mode registers */
261
+	const char **lpm_modes;
262
+	const u32 lpm_en_offset;
263
+	const u32 lpm_residency_offset;
264
+	const u32 lpm_status_offset;
265
+	const u32 lpm_live_status_offset;
177266 };
178267 
179268 /**
....@@ -186,6 +275,9 @@
186275  * @pmc_xram_read_bit:	flag to indicate whether PMC XRAM shadow registers
187276  *			used to read MPHY PG and PLL status are available
188277  * @mutex_lock:		mutex to complete one transcation
278
+ * @check_counters:	On resume, check if counters are getting incremented
279
+ * @pc10_counter:	PC10 residency counter
280
+ * @s0ix_counter:	S0ix residency (step adjusted)
189281  *
190282  * pmc_dev contains info about power management controller device.
191283  */
....@@ -193,11 +285,13 @@
193285 	u32 base_addr;
194286 	void __iomem *regbase;
195287 	const struct pmc_reg_map *map;
196
-#if IS_ENABLED(CONFIG_DEBUG_FS)
197288 	struct dentry *dbgfs_dir;
198
-#endif /* CONFIG_DEBUG_FS */
199289 	int pmc_xram_read_bit;
200290 	struct mutex lock; /* generic mutex lock for PMC Core */
291
+
292
+	bool check_counters; /* Check for counter increments on resume */
293
+	u64 pc10_counter;
294
+	u64 s0ix_counter;
201295 };
202296 
203297 #endif /* PMC_CORE_H */