forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920
kernel/drivers/phy/st/phy-miphy28lp.c
....@@ -1,18 +1,15 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright (C) 2014 STMicroelectronics
34 *
45 * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
56 *
67 * Author: Alexandre Torgue <alexandre.torgue@st.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2, as
10
- * published by the Free Software Foundation.
11
- *
128 */
139
1410 #include <linux/platform_device.h>
1511 #include <linux/io.h>
12
+#include <linux/iopoll.h>
1613 #include <linux/kernel.h>
1714 #include <linux/module.h>
1815 #include <linux/of.h>
....@@ -488,19 +485,11 @@
488485
489486 static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy)
490487 {
491
- unsigned long finish = jiffies + 5 * HZ;
492488 u8 val;
493489
494490 /* Waiting for Compensation to complete */
495
- do {
496
- val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);
497
-
498
- if (time_after_eq(jiffies, finish))
499
- return -EBUSY;
500
- cpu_relax();
501
- } while (!(val & COMP_DONE));
502
-
503
- return 0;
491
+ return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_COMP_FSM_6,
492
+ val, val & COMP_DONE, 1, 5 * USEC_PER_SEC);
504493 }
505494
506495
....@@ -809,7 +798,6 @@
809798
810799 static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
811800 {
812
- unsigned long finish = jiffies + 5 * HZ;
813801 u8 mask = HFC_PLL | HFC_RDY;
814802 u8 val;
815803
....@@ -820,21 +808,14 @@
820808 if (miphy_phy->type == PHY_TYPE_SATA)
821809 mask |= PHY_RDY;
822810
823
- do {
824
- val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
825
- if ((val & mask) != mask)
826
- cpu_relax();
827
- else
828
- return 0;
829
- } while (!time_after_eq(jiffies, finish));
830
-
831
- return -EBUSY;
811
+ return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_STATUS_1,
812
+ val, (val & mask) == mask, 1,
813
+ 5 * USEC_PER_SEC);
832814 }
833815
834816 static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
835817 {
836818 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
837
- unsigned long finish = jiffies + 5 * HZ;
838819 u32 val;
839820
840821 if (!miphy_phy->osc_rdy)
....@@ -843,17 +824,10 @@
843824 if (!miphy_phy->syscfg_reg[SYSCFG_STATUS])
844825 return -EINVAL;
845826
846
- do {
847
- regmap_read(miphy_dev->regmap,
848
- miphy_phy->syscfg_reg[SYSCFG_STATUS], &val);
849
-
850
- if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY)
851
- cpu_relax();
852
- else
853
- return 0;
854
- } while (!time_after_eq(jiffies, finish));
855
-
856
- return -EBUSY;
827
+ return regmap_read_poll_timeout(miphy_dev->regmap,
828
+ miphy_phy->syscfg_reg[SYSCFG_STATUS],
829
+ val, val & MIPHY_OSC_RDY, 1,
830
+ 5 * USEC_PER_SEC);
857831 }
858832
859833 static int miphy28lp_get_resource_byname(struct device_node *child,