add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/net/wireless/marvell/mwifiex/pcie.h
..
..
@@ -3,10 +3,10 @@
3
3
  * @brief This file contains definitions for PCI-E interface.
4
4
  * driver.
5
5
  *
6
- * Copyright (C) 2011-2014, Marvell International Ltd.
6
+ * Copyright 2011-2020 NXP
7
7
  *
8
- * This software file (the "File") is distributed by Marvell International
9
- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8
+ * This software file (the "File") is distributed by NXP
9
+ * under the terms of the GNU General Public License Version 2, June 1991
10
10
  * (the "License").  You may use, redistribute and/or modify this File in
11
11
  * accordance with the terms and conditions of the License, a copy of which
12
12
  * is available by writing to the Free Software Foundation, Inc.,
..
..
@@ -158,127 +158,6 @@
158
158
 	u8 msix_support;
159
159
 };
160
160
 
161
-static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
162
-	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
163
-	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
164
-	.cmd_size = PCIE_SCRATCH_2_REG,
165
-	.fw_status = PCIE_SCRATCH_3_REG,
166
-	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
167
-	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
168
-	.tx_rdptr = PCIE_SCRATCH_6_REG,
169
-	.tx_wrptr = PCIE_SCRATCH_7_REG,
170
-	.rx_rdptr = PCIE_SCRATCH_8_REG,
171
-	.rx_wrptr = PCIE_SCRATCH_9_REG,
172
-	.evt_rdptr = PCIE_SCRATCH_10_REG,
173
-	.evt_wrptr = PCIE_SCRATCH_11_REG,
174
-	.drv_rdy = PCIE_SCRATCH_12_REG,
175
-	.tx_start_ptr = 0,
176
-	.tx_mask = MWIFIEX_TXBD_MASK,
177
-	.tx_wrap_mask = 0,
178
-	.rx_mask = MWIFIEX_RXBD_MASK,
179
-	.rx_wrap_mask = 0,
180
-	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
181
-	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
182
-	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
183
-	.ring_flag_sop = 0,
184
-	.ring_flag_eop = 0,
185
-	.ring_flag_xs_sop = 0,
186
-	.ring_flag_xs_eop = 0,
187
-	.ring_tx_start_ptr = 0,
188
-	.pfu_enabled = 0,
189
-	.sleep_cookie = 1,
190
-	.msix_support = 0,
191
-};
192
-
193
-static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
194
-	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
195
-	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
196
-	.cmd_size = PCIE_SCRATCH_2_REG,
197
-	.fw_status = PCIE_SCRATCH_3_REG,
198
-	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
199
-	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
200
-	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
201
-	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
202
-	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
203
-	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
204
-	.evt_rdptr = PCIE_SCRATCH_10_REG,
205
-	.evt_wrptr = PCIE_SCRATCH_11_REG,
206
-	.drv_rdy = PCIE_SCRATCH_12_REG,
207
-	.tx_start_ptr = 16,
208
-	.tx_mask = 0x03FF0000,
209
-	.tx_wrap_mask = 0x07FF0000,
210
-	.rx_mask = 0x000003FF,
211
-	.rx_wrap_mask = 0x000007FF,
212
-	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
213
-	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
214
-	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
215
-	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
216
-	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
217
-	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
218
-	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
219
-	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
220
-	.pfu_enabled = 1,
221
-	.sleep_cookie = 0,
222
-	.fw_dump_ctrl = PCIE_SCRATCH_13_REG,
223
-	.fw_dump_start = PCIE_SCRATCH_14_REG,
224
-	.fw_dump_end = 0xcff,
225
-	.fw_dump_host_ready = 0xee,
226
-	.fw_dump_read_done = 0xfe,
227
-	.msix_support = 0,
228
-};
229
-
230
-static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
231
-	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
232
-	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
233
-	.cmd_size = PCIE_SCRATCH_2_REG,
234
-	.fw_status = PCIE_SCRATCH_3_REG,
235
-	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
236
-	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
237
-	.tx_rdptr = 0xC1A4,
238
-	.tx_wrptr = 0xC174,
239
-	.rx_rdptr = 0xC174,
240
-	.rx_wrptr = 0xC1A4,
241
-	.evt_rdptr = PCIE_SCRATCH_10_REG,
242
-	.evt_wrptr = PCIE_SCRATCH_11_REG,
243
-	.drv_rdy = PCIE_SCRATCH_12_REG,
244
-	.tx_start_ptr = 16,
245
-	.tx_mask = 0x0FFF0000,
246
-	.tx_wrap_mask = 0x1FFF0000,
247
-	.rx_mask = 0x00000FFF,
248
-	.rx_wrap_mask = 0x00001FFF,
249
-	.tx_rollover_ind = BIT(28),
250
-	.rx_rollover_ind = BIT(12),
251
-	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
252
-	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
253
-	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
254
-	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
255
-	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
256
-	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
257
-	.pfu_enabled = 1,
258
-	.sleep_cookie = 0,
259
-	.fw_dump_ctrl = PCIE_SCRATCH_13_REG,
260
-	.fw_dump_start = PCIE_SCRATCH_14_REG,
261
-	.fw_dump_end = 0xcff,
262
-	.fw_dump_host_ready = 0xcc,
263
-	.fw_dump_read_done = 0xdd,
264
-	.msix_support = 0,
265
-};
266
-
267
-static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
268
-	{"ITCM", NULL, 0, 0xF0},
269
-	{"DTCM", NULL, 0, 0xF1},
270
-	{"SQRAM", NULL, 0, 0xF2},
271
-	{"IRAM", NULL, 0, 0xF3},
272
-	{"APU", NULL, 0, 0xF4},
273
-	{"CIU", NULL, 0, 0xF5},
274
-	{"ICU", NULL, 0, 0xF6},
275
-	{"MAC", NULL, 0, 0xF7},
276
-};
277
-
278
-static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
279
-	{"DUMP", NULL, 0, 0xDD},
280
-};
281
-
282
161
 struct mwifiex_pcie_device {
283
162
 	const struct mwifiex_pcie_card_reg *reg;
284
163
 	u16 blksz_fw_dl;
..
..
@@ -287,34 +166,6 @@
287
166
 	struct memory_type_mapping *mem_type_mapping_tbl;
288
167
 	u8 num_mem_types;
289
168
 	bool can_ext_scan;
290
-};
291
-
292
-static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
293
-	.reg            = &mwifiex_reg_8766,
294
-	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
295
-	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
296
-	.can_dump_fw = false,
297
-	.can_ext_scan = true,
298
-};
299
-
300
-static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
301
-	.reg            = &mwifiex_reg_8897,
302
-	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
303
-	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
304
-	.can_dump_fw = true,
305
-	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
306
-	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
307
-	.can_ext_scan = true,
308
-};
309
-
310
-static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
311
-	.reg            = &mwifiex_reg_8997,
312
-	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
313
-	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
314
-	.can_dump_fw = true,
315
-	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
316
-	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
317
-	.can_ext_scan = true,
318
169
 };
319
170
 
320
171
 struct mwifiex_evt_buf_desc {