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145 | 145 | |
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146 | 146 | enum { |
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147 | 147 | SH_ETH_REG_GIGABIT, |
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148 | | - SH_ETH_REG_FAST_RZ, |
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149 | 148 | SH_ETH_REG_FAST_RCAR, |
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150 | 149 | SH_ETH_REG_FAST_SH4, |
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151 | 150 | SH_ETH_REG_FAST_SH3_SH2 |
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.. | .. |
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490 | 489 | unsigned apr:1; /* EtherC has APR */ |
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491 | 490 | unsigned mpr:1; /* EtherC has MPR */ |
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492 | 491 | unsigned tpauser:1; /* EtherC has TPAUSER */ |
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| 492 | + unsigned gecmr:1; /* EtherC has GECMR */ |
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493 | 493 | unsigned bculr:1; /* EtherC has BCULR */ |
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494 | 494 | unsigned tsu:1; /* EtherC has TSU */ |
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495 | 495 | unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */ |
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.. | .. |
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499 | 499 | unsigned no_ade:1; /* E-DMAC DOES NOT have ADE bit in EESR */ |
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500 | 500 | unsigned no_xdfar:1; /* E-DMAC DOES NOT have RDFAR/TDFAR */ |
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501 | 501 | unsigned xdfar_rw:1; /* E-DMAC has writeable RDFAR/TDFAR */ |
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502 | | - unsigned hw_checksum:1; /* E-DMAC has CSMR */ |
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| 502 | + unsigned csmr:1; /* E-DMAC has CSMR */ |
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| 503 | + unsigned rx_csum:1; /* EtherC has ECMR.RCSC */ |
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503 | 504 | unsigned select_mii:1; /* EtherC has RMII_MII (MII select register) */ |
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504 | 505 | unsigned rmiimode:1; /* EtherC has RMIIMODE register */ |
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505 | 506 | unsigned rtrate:1; /* EtherC has RTRATE register */ |
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