~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,11 +1,5 @@
1		-/* This program is free software; you can redistribute it and/or modify
2		- * it under the terms of the GNU General Public License as published by
3		- * the Free Software Foundation; version 2 of the License
4		- *
5		- * This program is distributed in the hope that it will be useful,
6		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
7		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8		- * GNU General Public License for more details.
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
9	3	*
10	4	* Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11	5	* Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
..	..	@@ -15,7 +9,12 @@
15	9	#ifndef MTK_ETH_H
16	10	#define MTK_ETH_H
17	11
	12	+#include <linux/dma-mapping.h>
	13	+#include <linux/netdevice.h>
	14	+#include <linux/of_net.h>
	15	+#include <linux/u64_stats_sync.h>
18	16	#include <linux/refcount.h>
	17	+#include <linux/phylink.h>
19	18
20	19	#define MTK_QDMA_PAGE_SIZE 2048
21	20	#define MTK_MAX_RX_LENGTH 1536
..	..	@@ -41,7 +40,8 @@
41	40	NETIF_F_SG \| NETIF_F_TSO \| \
42	41	NETIF_F_TSO6 \| \
43	42	NETIF_F_IPV6_CSUM)
44		-#define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
	43	+#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG \| NETIF_F_RXCSUM)
	44	+#define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
45	45
46	46	#define MTK_MAX_RX_RING_NUM 4
47	47	#define MTK_HW_LRO_DMA_SIZE 8
..	..	@@ -84,6 +84,8 @@
84	84	#define MTK_GDMA_ICS_EN BIT(22)
85	85	#define MTK_GDMA_TCS_EN BIT(21)
86	86	#define MTK_GDMA_UCS_EN BIT(20)
	87	+#define MTK_GDMA_TO_PDMA 0x0
	88	+#define MTK_GDMA_DROP_ALL 0x7777
87	89
88	90	/* Unicast Filter MAC Address Register - Low */
89	91	#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
..	..	@@ -120,6 +122,7 @@
120	122	/* PDMA Global Configuration Register */
121	123	#define MTK_PDMA_GLO_CFG 0xa04
122	124	#define MTK_MULTI_EN BIT(10)
	125	+#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
123	126
124	127	/* PDMA Reset Index Register */
125	128	#define MTK_PDMA_RST_IDX 0xa08
..	..	@@ -214,7 +217,7 @@
214	217	#define FC_THRES_MIN 0x4444
215	218
216	219	/* QDMA Interrupt Status Register */
217		-#define MTK_QMTK_INT_STATUS 0x1A18
	220	+#define MTK_QDMA_INT_STATUS 0x1A18
218	221	#define MTK_RX_DONE_DLY BIT(30)
219	222	#define MTK_RX_DONE_INT3 BIT(19)
220	223	#define MTK_RX_DONE_INT2 BIT(18)
..	..	@@ -263,8 +266,21 @@
263	266	/* QDMA FQ Free Page Buffer Length Register */
264	267	#define MTK_QDMA_FQ_BLEN 0x1B2C
265	268
266		-/* GMA1 Received Good Byte Count Register */
267		-#define MTK_GDM1_TX_GBCNT 0x2400
	269	+/* GMA1 counter / statics register */
	270	+#define MTK_GDM1_RX_GBCNT_L 0x2400
	271	+#define MTK_GDM1_RX_GBCNT_H 0x2404
	272	+#define MTK_GDM1_RX_GPCNT 0x2408
	273	+#define MTK_GDM1_RX_OERCNT 0x2410
	274	+#define MTK_GDM1_RX_FERCNT 0x2414
	275	+#define MTK_GDM1_RX_SERCNT 0x2418
	276	+#define MTK_GDM1_RX_LENCNT 0x241c
	277	+#define MTK_GDM1_RX_CERCNT 0x2420
	278	+#define MTK_GDM1_RX_FCCNT 0x2424
	279	+#define MTK_GDM1_TX_SKIPCNT 0x2428
	280	+#define MTK_GDM1_TX_COLCNT 0x242c
	281	+#define MTK_GDM1_TX_GBCNT_L 0x2430
	282	+#define MTK_GDM1_TX_GBCNT_H 0x2434
	283	+#define MTK_GDM1_TX_GPCNT 0x2438
268	284	#define MTK_STAT_OFFSET 0x40
269	285
270	286	/* QDMA descriptor txd4 */
..	..	@@ -278,11 +294,18 @@
278	294	#define TX_DMA_OWNER_CPU BIT(31)
279	295	#define TX_DMA_LS0 BIT(30)
280	296	#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
	297	+#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
281	298	#define TX_DMA_SWC BIT(14)
282	299	#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
283	300
	301	+/* PDMA on MT7628 */
	302	+#define TX_DMA_DONE BIT(31)
	303	+#define TX_DMA_LS1 BIT(14)
	304	+#define TX_DMA_DESP2_DEF (TX_DMA_LS0 \| TX_DMA_DONE)
	305	+
284	306	/* QDMA descriptor rxd2 */
285	307	#define RX_DMA_DONE BIT(31)
	308	+#define RX_DMA_LSO BIT(30)
286	309	#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
287	310	#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
288	311	#define RX_DMA_VTAG BIT(15)
..	..	@@ -292,6 +315,7 @@
292	315
293	316	/* QDMA descriptor rxd4 */
294	317	#define RX_DMA_L4_VALID BIT(24)
	318	+#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
295	319	#define RX_DMA_FPORT_SHIFT 19
296	320	#define RX_DMA_FPORT_MASK 0x7
297	321
..	..	@@ -315,6 +339,7 @@
315	339	#define MAC_MCR_FORCE_MODE BIT(15)
316	340	#define MAC_MCR_TX_EN BIT(14)
317	341	#define MAC_MCR_RX_EN BIT(13)
	342	+#define MAC_MCR_RX_FIFO_CLR_DIS BIT(12)
318	343	#define MAC_MCR_BACKOFF_EN BIT(9)
319	344	#define MAC_MCR_BACKPR_EN BIT(8)
320	345	#define MAC_MCR_FORCE_RX_FC BIT(5)
..	..	@@ -323,21 +348,31 @@
323	348	#define MAC_MCR_SPEED_100 BIT(2)
324	349	#define MAC_MCR_FORCE_DPX BIT(1)
325	350	#define MAC_MCR_FORCE_LINK BIT(0)
326		-#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 \| MAC_MCR_IPG_CFG \| \
327		- MAC_MCR_FORCE_MODE \| MAC_MCR_TX_EN \| \
328		- MAC_MCR_RX_EN \| MAC_MCR_BACKOFF_EN \| \
329		- MAC_MCR_BACKPR_EN \| MAC_MCR_FORCE_RX_FC \| \
330		- MAC_MCR_FORCE_TX_FC \| MAC_MCR_SPEED_1000 \| \
331		- MAC_MCR_FORCE_DPX \| MAC_MCR_FORCE_LINK)
	351	+#define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
	352	+
	353	+/* Mac status registers */
	354	+#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
	355	+#define MAC_MSR_EEE1G BIT(7)
	356	+#define MAC_MSR_EEE100M BIT(6)
	357	+#define MAC_MSR_RX_FC BIT(5)
	358	+#define MAC_MSR_TX_FC BIT(4)
	359	+#define MAC_MSR_SPEED_1000 BIT(3)
	360	+#define MAC_MSR_SPEED_100 BIT(2)
	361	+#define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 \| MAC_MSR_SPEED_100)
	362	+#define MAC_MSR_DPX BIT(1)
	363	+#define MAC_MSR_LINK BIT(0)
332	364
333	365	/* TRGMII RXC control register */
334	366	#define TRGMII_RCK_CTRL 0x10300
335	367	#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
336	368	#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
337	369	#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
	370	+#define RXC_RST BIT(31)
338	371	#define RXC_DQSISEL BIT(30)
339	372	#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL \| RXCTL_DMWTLAT(2) \| DQSI1(16))
340	373	#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
	374	+
	375	+#define NUM_TRGMII_CTRL 5
341	376
342	377	/* TRGMII RXC control register */
343	378	#define TRGMII_TCK_CTRL 0x10340
..	..	@@ -345,6 +380,11 @@
345	380	#define TXC_INV BIT(30)
346	381	#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
347	382	#define TCK_CTRL_RGMII_10_100 (TXC_INV \| TXCTL_DMWTLAT(2))
	383	+
	384	+/* TRGMII TX Drive Strength */
	385	+#define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
	386	+#define TD_DM_DRVP(x) ((x) & 0xf)
	387	+#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
348	388
349	389	/* TRGMII Interface mode register */
350	390	#define INTF_MODE 0x10390
..	..	@@ -364,18 +404,29 @@
364	404	#define ETHSYS_CHIPID4_7 0x4
365	405	#define MT7623_ETH 7623
366	406	#define MT7622_ETH 7622
	407	+#define MT7621_ETH 7621
	408	+
	409	+/* ethernet system control register */
	410	+#define ETHSYS_SYSCFG 0x10
	411	+#define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
367	412
368	413	/* ethernet subsystem config register */
369	414	#define ETHSYS_SYSCFG0 0x14
370	415	#define SYSCFG0_GE_MASK 0x3
371	416	#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
372		-#define SYSCFG0_SGMII_MASK (3 << 8)
373		-#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & GENMASK(9, 8))
374		-#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & GENMASK(9, 8))
	417	+#define SYSCFG0_SGMII_MASK GENMASK(9, 8)
	418	+#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
	419	+#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
	420	+#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
	421	+#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
	422	+
375	423
376	424	/* ethernet subsystem clock register */
377	425	#define ETHSYS_CLKCFG0 0x2c
378	426	#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
	427	+#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) \| BIT(6))
	428	+#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
	429	+#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
379	430
380	431	/* ethernet reset control register */
381	432	#define ETHSYS_RSTCTRL 0x34
..	..	@@ -386,18 +437,67 @@
386	437	/* Register to auto-negotiation restart */
387	438	#define SGMSYS_PCS_CONTROL_1 0x0
388	439	#define SGMII_AN_RESTART BIT(9)
	440	+#define SGMII_ISOLATE BIT(10)
	441	+#define SGMII_AN_ENABLE BIT(12)
	442	+#define SGMII_LINK_STATYS BIT(18)
	443	+#define SGMII_AN_ABILITY BIT(19)
	444	+#define SGMII_AN_COMPLETE BIT(21)
	445	+#define SGMII_PCS_FAULT BIT(23)
	446	+#define SGMII_AN_EXPANSION_CLR BIT(30)
389	447
390	448	/* Register to programmable link timer, the unit in 2 * 8ns */
391	449	#define SGMSYS_PCS_LINK_TIMER 0x18
392	450	#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
393	451
394	452	/* Register to control remote fault */
395		-#define SGMSYS_SGMII_MODE 0x20
396		-#define SGMII_REMOTE_FAULT_DIS BIT(8)
	453	+#define SGMSYS_SGMII_MODE 0x20
	454	+#define SGMII_IF_MODE_BIT0 BIT(0)
	455	+#define SGMII_SPEED_DUPLEX_AN BIT(1)
	456	+#define SGMII_SPEED_10 0x0
	457	+#define SGMII_SPEED_100 BIT(2)
	458	+#define SGMII_SPEED_1000 BIT(3)
	459	+#define SGMII_DUPLEX_FULL BIT(4)
	460	+#define SGMII_IF_MODE_BIT5 BIT(5)
	461	+#define SGMII_REMOTE_FAULT_DIS BIT(8)
	462	+#define SGMII_CODE_SYNC_SET_VAL BIT(9)
	463	+#define SGMII_CODE_SYNC_SET_EN BIT(10)
	464	+#define SGMII_SEND_AN_ERROR_EN BIT(11)
	465	+#define SGMII_IF_MODE_MASK GENMASK(5, 1)
	466	+
	467	+/* Register to set SGMII speed, ANA RG_ Control Signals III*/
	468	+#define SGMSYS_ANA_RG_CS3 0x2028
	469	+#define RG_PHY_SPEED_MASK (BIT(2) \| BIT(3))
	470	+#define RG_PHY_SPEED_1_25G 0x0
	471	+#define RG_PHY_SPEED_3_125G BIT(2)
397	472
398	473	/* Register to power up QPHY */
399	474	#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
400	475	#define SGMII_PHYA_PWD BIT(4)
	476	+
	477	+/* Infrasys subsystem config registers */
	478	+#define INFRA_MISC2 0x70c
	479	+#define CO_QPHY_SEL BIT(0)
	480	+#define GEPHY_MAC_SEL BIT(1)
	481	+
	482	+/* MT7628/88 specific stuff */
	483	+#define MT7628_PDMA_OFFSET 0x0800
	484	+#define MT7628_SDM_OFFSET 0x0c00
	485	+
	486	+#define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
	487	+#define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
	488	+#define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
	489	+#define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
	490	+#define MT7628_PST_DTX_IDX0 BIT(0)
	491	+
	492	+#define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
	493	+#define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
	494	+
	495	+/* Counter / stat register */
	496	+#define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100)
	497	+#define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104)
	498	+#define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108)
	499	+#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
	500	+#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
401	501
402	502	struct mtk_rx_dma {
403	503	unsigned int rxd1;
..	..	@@ -463,15 +563,21 @@
463	563	*/
464	564	enum mtk_clks_map {
465	565	MTK_CLK_ETHIF,
	566	+ MTK_CLK_SGMIITOP,
466	567	MTK_CLK_ESW,
467	568	MTK_CLK_GP0,
468	569	MTK_CLK_GP1,
469	570	MTK_CLK_GP2,
	571	+ MTK_CLK_FE,
470	572	MTK_CLK_TRGPLL,
471	573	MTK_CLK_SGMII_TX_250M,
472	574	MTK_CLK_SGMII_RX_250M,
473	575	MTK_CLK_SGMII_CDR_REF,
474	576	MTK_CLK_SGMII_CDR_FB,
	577	+ MTK_CLK_SGMII2_TX_250M,
	578	+ MTK_CLK_SGMII2_RX_250M,
	579	+ MTK_CLK_SGMII2_CDR_REF,
	580	+ MTK_CLK_SGMII2_CDR_FB,
475	581	MTK_CLK_SGMII_CK,
476	582	MTK_CLK_ETH2PLL,
477	583	MTK_CLK_MAX
..	..	@@ -489,6 +595,22 @@
489	595	BIT(MTK_CLK_SGMII_CDR_FB) \| \
490	596	BIT(MTK_CLK_SGMII_CK) \| \
491	597	BIT(MTK_CLK_ETH2PLL))
	598	+#define MT7621_CLKS_BITMAP (0)
	599	+#define MT7628_CLKS_BITMAP (0)
	600	+#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) \| BIT(MTK_CLK_ESW) \| \
	601	+ BIT(MTK_CLK_GP0) \| BIT(MTK_CLK_GP1) \| \
	602	+ BIT(MTK_CLK_GP2) \| BIT(MTK_CLK_FE) \| \
	603	+ BIT(MTK_CLK_SGMII_TX_250M) \| \
	604	+ BIT(MTK_CLK_SGMII_RX_250M) \| \
	605	+ BIT(MTK_CLK_SGMII_CDR_REF) \| \
	606	+ BIT(MTK_CLK_SGMII_CDR_FB) \| \
	607	+ BIT(MTK_CLK_SGMII2_TX_250M) \| \
	608	+ BIT(MTK_CLK_SGMII2_RX_250M) \| \
	609	+ BIT(MTK_CLK_SGMII2_CDR_REF) \| \
	610	+ BIT(MTK_CLK_SGMII2_CDR_FB) \| \
	611	+ BIT(MTK_CLK_SGMII_CK) \| \
	612	+ BIT(MTK_CLK_ETH2PLL) \| BIT(MTK_CLK_SGMIITOP))
	613	+
492	614	enum mtk_dev_state {
493	615	MTK_HW_INIT,
494	616	MTK_RESETTING
..	..	@@ -529,6 +651,10 @@
529	651	struct mtk_tx_dma *last_free;
530	652	u16 thresh;
531	653	atomic_t free_count;
	654	+ int dma_size;
	655	+ struct mtk_tx_dma dma_pdma; / For MT7628/88 PDMA handling */
	656	+ dma_addr_t phys_pdma;
	657	+ int cpu_idx;
532	658	};
533	659
534	660	/* PDMA rx ring mode */
..	..	@@ -558,34 +684,165 @@
558	684	u32 crx_idx_reg;
559	685	};
560	686
561		-#define MTK_TRGMII BIT(0)
562		-#define MTK_GMAC1_TRGMII (BIT(1) \| MTK_TRGMII)
563		-#define MTK_ESW BIT(4)
564		-#define MTK_GMAC1_ESW (BIT(5) \| MTK_ESW)
565		-#define MTK_SGMII BIT(8)
566		-#define MTK_GMAC1_SGMII (BIT(9) \| MTK_SGMII)
567		-#define MTK_GMAC2_SGMII (BIT(10) \| MTK_SGMII)
568		-#define MTK_DUAL_GMAC_SHARED_SGMII (BIT(11) \| MTK_GMAC1_SGMII \| \
569		- MTK_GMAC2_SGMII)
570		-#define MTK_HWLRO BIT(12)
	687	+enum mkt_eth_capabilities {
	688	+ MTK_RGMII_BIT = 0,
	689	+ MTK_TRGMII_BIT,
	690	+ MTK_SGMII_BIT,
	691	+ MTK_ESW_BIT,
	692	+ MTK_GEPHY_BIT,
	693	+ MTK_MUX_BIT,
	694	+ MTK_INFRA_BIT,
	695	+ MTK_SHARED_SGMII_BIT,
	696	+ MTK_HWLRO_BIT,
	697	+ MTK_SHARED_INT_BIT,
	698	+ MTK_TRGMII_MT7621_CLK_BIT,
	699	+ MTK_QDMA_BIT,
	700	+ MTK_SOC_MT7628_BIT,
	701	+
	702	+ /* MUX BITS*/
	703	+ MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
	704	+ MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
	705	+ MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
	706	+ MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
	707	+ MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
	708	+
	709	+ /* PATH BITS */
	710	+ MTK_ETH_PATH_GMAC1_RGMII_BIT,
	711	+ MTK_ETH_PATH_GMAC1_TRGMII_BIT,
	712	+ MTK_ETH_PATH_GMAC1_SGMII_BIT,
	713	+ MTK_ETH_PATH_GMAC2_RGMII_BIT,
	714	+ MTK_ETH_PATH_GMAC2_SGMII_BIT,
	715	+ MTK_ETH_PATH_GMAC2_GEPHY_BIT,
	716	+ MTK_ETH_PATH_GDM1_ESW_BIT,
	717	+};
	718	+
	719	+/* Supported hardware group on SoCs */
	720	+#define MTK_RGMII BIT(MTK_RGMII_BIT)
	721	+#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
	722	+#define MTK_SGMII BIT(MTK_SGMII_BIT)
	723	+#define MTK_ESW BIT(MTK_ESW_BIT)
	724	+#define MTK_GEPHY BIT(MTK_GEPHY_BIT)
	725	+#define MTK_MUX BIT(MTK_MUX_BIT)
	726	+#define MTK_INFRA BIT(MTK_INFRA_BIT)
	727	+#define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT)
	728	+#define MTK_HWLRO BIT(MTK_HWLRO_BIT)
	729	+#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
	730	+#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
	731	+#define MTK_QDMA BIT(MTK_QDMA_BIT)
	732	+#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
	733	+
	734	+#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
	735	+ BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
	736	+#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
	737	+ BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
	738	+#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
	739	+ BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
	740	+#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
	741	+ BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
	742	+#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
	743	+ BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
	744	+
	745	+/* Supported path present on SoCs */
	746	+#define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
	747	+#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
	748	+#define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
	749	+#define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
	750	+#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
	751	+#define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
	752	+#define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
	753	+
	754	+#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII \| MTK_RGMII)
	755	+#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII \| MTK_TRGMII)
	756	+#define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII \| MTK_SGMII)
	757	+#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII \| MTK_RGMII)
	758	+#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII \| MTK_SGMII)
	759	+#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY \| MTK_GEPHY)
	760	+#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW \| MTK_ESW)
	761	+
	762	+/* MUXes present on SoCs */
	763	+/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
	764	+#define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \| MTK_MUX)
	765	+
	766	+/* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
	767	+#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
	768	+ (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \| MTK_MUX \| MTK_INFRA)
	769	+
	770	+/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
	771	+#define MTK_MUX_U3_GMAC2_TO_QPHY \
	772	+ (MTK_ETH_MUX_U3_GMAC2_TO_QPHY \| MTK_MUX \| MTK_INFRA)
	773	+
	774	+/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
	775	+#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
	776	+ (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \| MTK_MUX \| \
	777	+ MTK_SHARED_SGMII)
	778	+
	779	+/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
	780	+#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
	781	+ (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \| MTK_MUX)
	782	+
571	783	#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
	784	+
	785	+#define MT7621_CAPS (MTK_GMAC1_RGMII \| MTK_GMAC1_TRGMII \| \
	786	+ MTK_GMAC2_RGMII \| MTK_SHARED_INT \| \
	787	+ MTK_TRGMII_MT7621_CLK \| MTK_QDMA)
	788	+
	789	+#define MT7622_CAPS (MTK_GMAC1_RGMII \| MTK_GMAC1_SGMII \| MTK_GMAC2_RGMII \| \
	790	+ MTK_GMAC2_SGMII \| MTK_GDM1_ESW \| \
	791	+ MTK_MUX_GDM1_TO_GMAC1_ESW \| \
	792	+ MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \| MTK_QDMA)
	793	+
	794	+#define MT7623_CAPS (MTK_GMAC1_RGMII \| MTK_GMAC1_TRGMII \| MTK_GMAC2_RGMII \| \
	795	+ MTK_QDMA)
	796	+
	797	+#define MT7628_CAPS (MTK_SHARED_INT \| MTK_SOC_MT7628)
	798	+
	799	+#define MT7629_CAPS (MTK_GMAC1_SGMII \| MTK_GMAC2_SGMII \| MTK_GMAC2_GEPHY \| \
	800	+ MTK_GDM1_ESW \| MTK_MUX_GDM1_TO_GMAC1_ESW \| \
	801	+ MTK_MUX_GMAC2_GMAC0_TO_GEPHY \| \
	802	+ MTK_MUX_U3_GMAC2_TO_QPHY \| \
	803	+ MTK_MUX_GMAC12_TO_GEPHY_SGMII \| MTK_QDMA)
572	804
573	805	/* struct mtk_eth_data - This is the structure holding all differences
574	806	* among various plaforms
	807	+ * @ana_rgc3: The offset for register ANA_RGC3 related to
	808	+ * sgmiisys syscon
575	809	* @caps Flags shown the extra capability for the SoC
	810	+ * @hw_features Flags shown HW features
576	811	* @required_clks Flags shown the bitmap for required clocks on
577	812	* the target SoC
578	813	* @required_pctl A bool value to show whether the SoC requires
579	814	* the extra setup for those pins used by GMAC.
580	815	*/
581	816	struct mtk_soc_data {
	817	+ u32 ana_rgc3;
582	818	u32 caps;
583	819	u32 required_clks;
584	820	bool required_pctl;
	821	+ netdev_features_t hw_features;
585	822	};
586	823
587	824	/* currently no SoC has more than 2 macs */
588	825	#define MTK_MAX_DEVS 2
	826	+
	827	+#define MTK_SGMII_PHYSPEED_AN BIT(31)
	828	+#define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
	829	+#define MTK_SGMII_PHYSPEED_1000 BIT(0)
	830	+#define MTK_SGMII_PHYSPEED_2500 BIT(1)
	831	+#define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x))
	832	+
	833	+/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
	834	+ * characteristics
	835	+ * @regmap: The register map pointing at the range used to setup
	836	+ * SGMII modes
	837	+ * @flags: The enum refers to which mode the sgmii wants to run on
	838	+ * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
	839	+ */
	840	+
	841	+struct mtk_sgmii {
	842	+ struct regmap *regmap[MTK_MAX_DEVS];
	843	+ u32 flags[MTK_MAX_DEVS];
	844	+ u32 ana_rgc3;
	845	+};
589	846
590	847	/* struct mtk_eth - This is the main datasructure for holding the state
591	848	* of the driver
..	..	@@ -602,8 +859,8 @@
602	859	* @msg_enable: Ethtool msg level
603	860	* @ethsys: The register map pointing at the range used to setup
604	861	* MII modes
605		- * @sgmiisys: The register map pointing at the range used to setup
606		- * SGMII modes
	862	+ * @infra: The register map pointing at the range used to setup
	863	+ * SGMII and GePHY path
607	864	* @pctl: The register map pointing at the range used to setup
608	865	* GMAC port drive/slew values
609	866	* @dma_refcnt: track how many netdevs are using the DMA engine
..	..	@@ -635,7 +892,8 @@
635	892	u32 msg_enable;
636	893	unsigned long sysclk;
637	894	struct regmap *ethsys;
638		- struct regmap *sgmiisys;
	895	+ struct regmap *infra;
	896	+ struct mtk_sgmii *sgmii;
639	897	struct regmap *pctl;
640	898	bool hwlro;
641	899	refcount_t dma_refcnt;
..	..	@@ -654,27 +912,33 @@
654	912	unsigned long state;
655	913
656	914	const struct mtk_soc_data *soc;
	915	+
	916	+ u32 tx_int_mask_reg;
	917	+ u32 tx_int_status_reg;
	918	+ u32 rx_dma_l4_valid;
	919	+ int ip_align;
657	920	};
658	921
659	922	/* struct mtk_mac - the structure that holds the info about the MACs of the
660	923	* SoC
661	924	* @id: The number of the MAC
662		- * @ge_mode: Interface mode kept for setup restoring
	925	+ * @interface: Interface mode kept for detecting change in hw settings
663	926	* @of_node: Our devicetree node
664	927	* @hw: Backpointer to our main datastruture
665	928	* @hw_stats: Packet statistics counter
666		- * @trgmii Indicate if the MAC uses TRGMII connected to internal
667		- switch
668	929	*/
669	930	struct mtk_mac {
670	931	int id;
671		- int ge_mode;
	932	+ phy_interface_t interface;
	933	+ unsigned int mode;
	934	+ int speed;
672	935	struct device_node *of_node;
	936	+ struct phylink *phylink;
	937	+ struct phylink_config phylink_config;
673	938	struct mtk_eth *hw;
674	939	struct mtk_hw_stats *hw_stats;
675	940	__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
676	941	int hwlro_ip_cnt;
677		- bool trgmii;
678	942	};
679	943
680	944	/* the struct describing the SoC. these are declared in the soc_xyz.c files */
..	..	@@ -686,4 +950,15 @@
686	950	void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
687	951	u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
688	952
	953	+int mtk_sgmii_init(struct mtk_sgmii ss, struct device_node np,
	954	+ u32 ana_rgc3);
	955	+int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
	956	+int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
	957	+ const struct phylink_link_state *state);
	958	+void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
	959	+
	960	+int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
	961	+int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
	962	+int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
	963	+
689	964	#endif /* MTK_ETH_H */