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2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
....@@ -284,12 +284,12 @@
284284 #define CCM_REG_GR_ARB_TYPE					 0xd015c
285285 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
286286    highest priority is 3. It is supposed; that the Store channel priority is
287
-   the compliment to 4 of the rest priorities - Aggregation channel; Load
287
+   the complement to 4 of the rest priorities - Aggregation channel; Load
288288    (FIC0) channel and Load (FIC1). */
289289 #define CCM_REG_GR_LD0_PR					 0xd0164
290290 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
291291    highest priority is 3. It is supposed; that the Store channel priority is
292
-   the compliment to 4 of the rest priorities - Aggregation channel; Load
292
+   the complement to 4 of the rest priorities - Aggregation channel; Load
293293    (FIC0) channel and Load (FIC1). */
294294 #define CCM_REG_GR_LD1_PR					 0xd0168
295295 /* [RW 2] General flags index. */
....@@ -4489,11 +4489,11 @@
44894489 #define TCM_REG_GR_ARB_TYPE					 0x50114
44904490 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
44914491    highest priority is 3. It is supposed that the Store channel is the
4492
-   compliment of the other 3 groups. */
4492
+   complement of the other 3 groups. */
44934493 #define TCM_REG_GR_LD0_PR					 0x5011c
44944494 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
44954495    highest priority is 3. It is supposed that the Store channel is the
4496
-   compliment of the other 3 groups. */
4496
+   complement of the other 3 groups. */
44974497 #define TCM_REG_GR_LD1_PR					 0x50120
44984498 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
44994499    sent to STORM; for a specific connection type. The double REG-pairs are
....@@ -5020,11 +5020,11 @@
50205020 #define UCM_REG_GR_ARB_TYPE					 0xe0144
50215021 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
50225022    highest priority is 3. It is supposed that the Store channel group is
5023
-   compliment to the others. */
5023
+   complement to the others. */
50245024 #define UCM_REG_GR_LD0_PR					 0xe014c
50255025 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
50265026    highest priority is 3. It is supposed that the Store channel group is
5027
-   compliment to the others. */
5027
+   complement to the others. */
50285028 #define UCM_REG_GR_LD1_PR					 0xe0150
50295029 /* [RW 2] The queue index for invalidate counter flag decision. */
50305030 #define UCM_REG_INV_CFLG_Q					 0xe00e4
....@@ -5523,11 +5523,11 @@
55235523 #define XCM_REG_GR_ARB_TYPE					 0x2020c
55245524 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
55255525    highest priority is 3. It is supposed that the Channel group is the
5526
-   compliment of the other 3 groups. */
5526
+   complement of the other 3 groups. */
55275527 #define XCM_REG_GR_LD0_PR					 0x20214
55285528 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
55295529    highest priority is 3. It is supposed that the Channel group is the
5530
-   compliment of the other 3 groups. */
5530
+   complement of the other 3 groups. */
55315531 #define XCM_REG_GR_LD1_PR					 0x20218
55325532 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
55335533    disregarded; acknowledge output is deasserted; all other signals are
....@@ -7639,6 +7639,82 @@
76397639 	(0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
76407640 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
76417641 
7642
+/* IdleChk registers */
7643
+#define PXP_REG_HST_VF_DISABLED_ERROR_VALID			 0x1030bc
7644
+#define PXP_REG_HST_VF_DISABLED_ERROR_DATA			 0x1030b8
7645
+#define PXP_REG_HST_PER_VIOLATION_VALID				 0x1030e0
7646
+#define PXP_REG_HST_INCORRECT_ACCESS_VALID			 0x1030cc
7647
+#define PXP2_REG_RD_CPL_ERR_DETAILS				 0x120778
7648
+#define PXP2_REG_RD_CPL_ERR_DETAILS2				 0x12077c
7649
+#define PXP2_REG_RQ_GARB					 0x120748
7650
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q0			 0x15c1bc
7651
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q1			 0x15c1c0
7652
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q2			 0x15c1c4
7653
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q3			 0x15c1c8
7654
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q4			 0x15c1cc
7655
+#define PBF_REG_DISABLE_NEW_TASK_PROC_Q5			 0x15c1d0
7656
+#define PBF_REG_CREDIT_Q2					 0x140344
7657
+#define PBF_REG_CREDIT_Q3					 0x140348
7658
+#define PBF_REG_CREDIT_Q4					 0x14034c
7659
+#define PBF_REG_CREDIT_Q5					 0x140350
7660
+#define PBF_REG_INIT_CRD_Q2					 0x15c238
7661
+#define PBF_REG_INIT_CRD_Q3					 0x15c23c
7662
+#define PBF_REG_INIT_CRD_Q4					 0x15c240
7663
+#define PBF_REG_INIT_CRD_Q5					 0x15c244
7664
+#define PBF_REG_TASK_CNT_Q0					 0x140374
7665
+#define PBF_REG_TASK_CNT_Q1					 0x140378
7666
+#define PBF_REG_TASK_CNT_Q2					 0x14037c
7667
+#define PBF_REG_TASK_CNT_Q3					 0x140380
7668
+#define PBF_REG_TASK_CNT_Q4					 0x140384
7669
+#define PBF_REG_TASK_CNT_Q5					 0x140388
7670
+#define PBF_REG_TASK_CNT_LB_Q					 0x140370
7671
+#define QM_REG_BYTECRD0						 0x16e6fc
7672
+#define QM_REG_BYTECRD1						 0x16e700
7673
+#define QM_REG_BYTECRD2						 0x16e704
7674
+#define QM_REG_BYTECRD3						 0x16e7ac
7675
+#define QM_REG_BYTECRD4						 0x16e7b0
7676
+#define QM_REG_BYTECRD5						 0x16e7b4
7677
+#define QM_REG_BYTECRD6						 0x16e7b8
7678
+#define QM_REG_BYTECRDCMDQ_0					 0x16e6e8
7679
+#define QM_REG_BYTECRDERRREG					 0x16e708
7680
+#define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID			 0xa714
7681
+#define QM_REG_VOQCREDIT_2					 0x1682d8
7682
+#define QM_REG_VOQCREDIT_3					 0x1682dc
7683
+#define QM_REG_VOQCREDIT_5					 0x1682e4
7684
+#define QM_REG_VOQCREDIT_6					 0x1682e8
7685
+#define QM_REG_VOQINITCREDIT_3					 0x16806c
7686
+#define QM_REG_VOQINITCREDIT_6					 0x168078
7687
+#define QM_REG_FWVOQ0TOHWVOQ					 0x16e7bc
7688
+#define QM_REG_FWVOQ1TOHWVOQ					 0x16e7c0
7689
+#define QM_REG_FWVOQ2TOHWVOQ					 0x16e7c4
7690
+#define QM_REG_FWVOQ3TOHWVOQ					 0x16e7c8
7691
+#define QM_REG_FWVOQ4TOHWVOQ					 0x16e7cc
7692
+#define QM_REG_FWVOQ5TOHWVOQ					 0x16e7d0
7693
+#define QM_REG_FWVOQ6TOHWVOQ					 0x16e7d4
7694
+#define QM_REG_FWVOQ7TOHWVOQ					 0x16e7d8
7695
+#define NIG_REG_INGRESS_EOP_PORT0_EMPTY				 0x104ec
7696
+#define NIG_REG_INGRESS_EOP_PORT1_EMPTY				 0x104f8
7697
+#define NIG_REG_INGRESS_RMP0_DSCR_EMPTY				 0x10530
7698
+#define NIG_REG_INGRESS_RMP1_DSCR_EMPTY				 0x10538
7699
+#define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY			 0x10508
7700
+#define NIG_REG_EGRESS_MNG0_FIFO_EMPTY				 0x10460
7701
+#define NIG_REG_EGRESS_MNG1_FIFO_EMPTY				 0x10474
7702
+#define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY				 0x10418
7703
+#define NIG_REG_EGRESS_DELAY0_EMPTY				 0x10420
7704
+#define NIG_REG_EGRESS_DELAY1_EMPTY				 0x10428
7705
+#define NIG_REG_LLH0_FIFO_EMPTY					 0x10548
7706
+#define NIG_REG_LLH1_FIFO_EMPTY					 0x10558
7707
+#define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY			 0x182a8
7708
+#define NIG_REG_P0_TLLH_FIFO_EMPTY				 0x18308
7709
+#define NIG_REG_P0_HBUF_DSCR_EMPTY				 0x18318
7710
+#define NIG_REG_P1_HBUF_DSCR_EMPTY				 0x18348
7711
+#define NIG_REG_P0_RX_MACFIFO_EMPTY				 0x18570
7712
+#define NIG_REG_P0_TX_MACFIFO_EMPTY				 0x18578
7713
+#define NIG_REG_EGRESS_DELAY2_EMPTY				 0x1862c
7714
+#define NIG_REG_EGRESS_DELAY3_EMPTY				 0x18630
7715
+#define NIG_REG_EGRESS_DELAY4_EMPTY				 0x18634
7716
+#define NIG_REG_EGRESS_DELAY5_EMPTY				 0x18638
7717
+
76427718 /******************************************************************************
76437719  * Description:
76447720  *	   Calculates crc 8 on a word value: polynomial 0-1-2-8
....@@ -7697,6 +7773,4 @@
76977773 
76987774 	return crc_res;
76997775 }
7700
-
7701
-
77027776 #endif /* BNX2X_REG_H */