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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
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1 | 2 | /* |
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2 | | - * |
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| 3 | + * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. |
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3 | 4 | * Intel Management Engine Interface (Intel MEI) Linux driver |
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4 | | - * Copyright (c) 2003-2012, Intel Corporation. |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify it |
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7 | | - * under the terms and conditions of the GNU General Public License, |
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8 | | - * version 2, as published by the Free Software Foundation. |
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9 | | - * |
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10 | | - * This program is distributed in the hope it will be useful, but WITHOUT |
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11 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 | | - * more details. |
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14 | | - * |
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15 | 5 | */ |
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| 6 | + |
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16 | 7 | #include <linux/module.h> |
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17 | | -#include <linux/moduleparam.h> |
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18 | 8 | #include <linux/kernel.h> |
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19 | 9 | #include <linux/device.h> |
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20 | | -#include <linux/fs.h> |
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21 | 10 | #include <linux/errno.h> |
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22 | 11 | #include <linux/types.h> |
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23 | | -#include <linux/fcntl.h> |
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24 | 12 | #include <linux/pci.h> |
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25 | | -#include <linux/poll.h> |
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26 | | -#include <linux/ioctl.h> |
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27 | | -#include <linux/cdev.h> |
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28 | 13 | #include <linux/sched.h> |
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29 | | -#include <linux/uuid.h> |
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30 | | -#include <linux/compat.h> |
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31 | | -#include <linux/jiffies.h> |
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32 | 14 | #include <linux/interrupt.h> |
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33 | 15 | |
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34 | 16 | #include <linux/pm_domain.h> |
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.. | .. |
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77 | 59 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, |
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78 | 60 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, |
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79 | 61 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, |
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80 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, |
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81 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, |
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| 62 | + {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, |
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| 63 | + {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, |
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82 | 64 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, |
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83 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, |
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| 65 | + {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, |
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84 | 66 | {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, |
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85 | 67 | {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, |
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86 | 68 | |
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87 | 69 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, |
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88 | 70 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, |
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89 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, |
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90 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, |
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91 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)}, |
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| 71 | + {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
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| 72 | + {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, |
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| 73 | + {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, |
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| 74 | + {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, |
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92 | 75 | |
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93 | 76 | {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, |
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94 | 77 | {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, |
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.. | .. |
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99 | 82 | |
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100 | 83 | {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, |
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101 | 84 | {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, |
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| 85 | + {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)}, |
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102 | 86 | |
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103 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH8_CFG)}, |
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104 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)}, |
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105 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH8_CFG)}, |
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106 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)}, |
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| 87 | + {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, |
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| 88 | + {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
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| 89 | + {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, |
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| 90 | + {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, |
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107 | 91 | |
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108 | 92 | {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, |
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109 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, |
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| 93 | + {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
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110 | 94 | {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, |
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111 | 95 | {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, |
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112 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)}, |
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| 96 | + {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
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113 | 97 | |
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114 | 98 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, |
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115 | 99 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)}, |
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116 | 100 | |
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117 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH12_CFG)}, |
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| 101 | + {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, |
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| 102 | + {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, |
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118 | 103 | |
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119 | | - {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)}, |
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| 104 | + {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, |
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| 105 | + |
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| 106 | + {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, |
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120 | 107 | {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, |
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121 | 108 | |
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122 | 109 | {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, |
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| 110 | + |
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| 111 | + {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, |
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| 112 | + |
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| 113 | + {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)}, |
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| 114 | + {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)}, |
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| 115 | + {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)}, |
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| 116 | + {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)}, |
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| 117 | + |
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| 118 | + {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)}, |
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| 119 | + |
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| 120 | + {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)}, |
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123 | 121 | |
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124 | 122 | /* required last entry */ |
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125 | 123 | {0, } |
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.. | .. |
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134 | 132 | static inline void mei_me_set_pm_domain(struct mei_device *dev) {} |
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135 | 133 | static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} |
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136 | 134 | #endif /* CONFIG_PM */ |
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| 135 | + |
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| 136 | +static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) |
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| 137 | +{ |
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| 138 | + struct pci_dev *pdev = to_pci_dev(dev->dev); |
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| 139 | + |
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| 140 | + return pci_read_config_dword(pdev, where, val); |
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| 141 | +} |
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137 | 142 | |
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138 | 143 | /** |
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139 | 144 | * mei_me_quirk_probe - probe for devices that doesn't valid ME interface |
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.. | .. |
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206 | 211 | } |
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207 | 212 | |
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208 | 213 | /* allocates and initializes the mei dev structure */ |
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209 | | - dev = mei_me_dev_init(pdev, cfg); |
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| 214 | + dev = mei_me_dev_init(&pdev->dev, cfg); |
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210 | 215 | if (!dev) { |
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211 | 216 | err = -ENOMEM; |
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212 | 217 | goto end; |
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213 | 218 | } |
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214 | 219 | hw = to_me_hw(dev); |
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215 | 220 | hw->mem_addr = pcim_iomap_table(pdev)[0]; |
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| 221 | + hw->read_fws = mei_me_read_fws; |
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216 | 222 | |
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217 | 223 | pci_enable_msi(pdev); |
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| 224 | + |
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| 225 | + hw->irq = pdev->irq; |
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218 | 226 | |
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219 | 227 | /* request and enable interrupt */ |
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220 | 228 | irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; |
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.. | .. |
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248 | 256 | * MEI requires to resume from runtime suspend mode |
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249 | 257 | * in order to perform link reset flow upon system suspend. |
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250 | 258 | */ |
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251 | | - dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); |
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| 259 | + dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); |
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252 | 260 | |
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253 | 261 | /* |
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254 | 262 | * ME maps runtime suspend/resume to D0i states, |
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.. | .. |
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401 | 409 | #ifdef CONFIG_PM |
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402 | 410 | static int mei_me_pm_runtime_idle(struct device *device) |
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403 | 411 | { |
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404 | | - struct pci_dev *pdev = to_pci_dev(device); |
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405 | 412 | struct mei_device *dev; |
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406 | 413 | |
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407 | | - dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n"); |
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| 414 | + dev_dbg(device, "rpm: me: runtime_idle\n"); |
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408 | 415 | |
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409 | | - dev = pci_get_drvdata(pdev); |
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| 416 | + dev = dev_get_drvdata(device); |
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410 | 417 | if (!dev) |
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411 | 418 | return -ENODEV; |
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412 | 419 | if (mei_write_is_idle(dev)) |
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.. | .. |
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417 | 424 | |
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418 | 425 | static int mei_me_pm_runtime_suspend(struct device *device) |
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419 | 426 | { |
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420 | | - struct pci_dev *pdev = to_pci_dev(device); |
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421 | 427 | struct mei_device *dev; |
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422 | 428 | int ret; |
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423 | 429 | |
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424 | | - dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n"); |
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| 430 | + dev_dbg(device, "rpm: me: runtime suspend\n"); |
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425 | 431 | |
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426 | | - dev = pci_get_drvdata(pdev); |
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| 432 | + dev = dev_get_drvdata(device); |
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427 | 433 | if (!dev) |
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428 | 434 | return -ENODEV; |
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429 | 435 | |
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.. | .. |
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436 | 442 | |
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437 | 443 | mutex_unlock(&dev->device_lock); |
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438 | 444 | |
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439 | | - dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret); |
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| 445 | + dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); |
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440 | 446 | |
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441 | 447 | if (ret && ret != -EAGAIN) |
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442 | 448 | schedule_work(&dev->reset_work); |
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.. | .. |
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446 | 452 | |
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447 | 453 | static int mei_me_pm_runtime_resume(struct device *device) |
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448 | 454 | { |
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449 | | - struct pci_dev *pdev = to_pci_dev(device); |
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450 | 455 | struct mei_device *dev; |
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451 | 456 | int ret; |
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452 | 457 | |
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453 | | - dev_dbg(&pdev->dev, "rpm: me: runtime resume\n"); |
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| 458 | + dev_dbg(device, "rpm: me: runtime resume\n"); |
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454 | 459 | |
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455 | | - dev = pci_get_drvdata(pdev); |
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| 460 | + dev = dev_get_drvdata(device); |
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456 | 461 | if (!dev) |
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457 | 462 | return -ENODEV; |
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458 | 463 | |
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.. | .. |
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462 | 467 | |
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463 | 468 | mutex_unlock(&dev->device_lock); |
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464 | 469 | |
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465 | | - dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret); |
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| 470 | + dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); |
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466 | 471 | |
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467 | 472 | if (ret) |
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468 | 473 | schedule_work(&dev->reset_work); |
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