forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920
kernel/drivers/misc/mei/hw-me-regs.h
....@@ -1,68 +1,8 @@
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-/******************************************************************************
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+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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+/*
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+ * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
24 * Intel Management Engine Interface (Intel MEI) Linux driver
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- * Intel MEI Interface Header
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- *
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- * This file is provided under a dual BSD/GPLv2 license. When using or
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- * redistributing this file, you may do so under either license.
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- *
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- * GPL LICENSE SUMMARY
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- *
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- * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of version 2 of the GNU General Public License as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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- * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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- * USA
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- *
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- * The full GNU General Public License is included in this distribution
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- * in the file called LICENSE.GPL.
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- *
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- * Contact Information:
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- * Intel Corporation.
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- * linux-mei@linux.intel.com
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- * http://www.intel.com
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- *
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- * BSD LICENSE
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- *
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- * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
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- * All rights reserved.
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- *
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- * Redistribution and use in source and binary forms, with or without
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- * modification, are permitted provided that the following conditions
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- * are met:
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- *
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- * * Redistributions of source code must retain the above copyright
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- * notice, this list of conditions and the following disclaimer.
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- * * Redistributions in binary form must reproduce the above copyright
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- * notice, this list of conditions and the following disclaimer in
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- * the documentation and/or other materials provided with the
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- * distribution.
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- * * Neither the name Intel Corporation nor the names of its
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- * contributors may be used to endorse or promote products derived
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- * from this software without specific prior written permission.
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- *
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- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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- *
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- *****************************************************************************/
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+ */
666 #ifndef _MEI_HW_MEI_REGS_H_
677 #define _MEI_HW_MEI_REGS_H_
688
....@@ -119,6 +59,7 @@
11959
12060 #define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */
12161 #define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */
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+#define MEI_DEV_ID_SPT_3 0x9D3E /* Sunrise Point 3 (iToutch) */
12263 #define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */
12364 #define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */
12465
....@@ -133,11 +74,12 @@
13374
13475 #define MEI_DEV_ID_KBP 0xA2BA /* Kaby Point */
13576 #define MEI_DEV_ID_KBP_2 0xA2BB /* Kaby Point 2 */
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+#define MEI_DEV_ID_KBP_3 0xA2BE /* Kaby Point 3 (iTouch) */
13678
13779 #define MEI_DEV_ID_CNP_LP 0x9DE0 /* Cannon Point LP */
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-#define MEI_DEV_ID_CNP_LP_4 0x9DE4 /* Cannon Point LP 4 (iTouch) */
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+#define MEI_DEV_ID_CNP_LP_3 0x9DE4 /* Cannon Point LP 3 (iTouch) */
13981 #define MEI_DEV_ID_CNP_H 0xA360 /* Cannon Point H */
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-#define MEI_DEV_ID_CNP_H_4 0xA364 /* Cannon Point H 4 (iTouch) */
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+#define MEI_DEV_ID_CNP_H_3 0xA364 /* Cannon Point H 3 (iTouch) */
14183
14284 #define MEI_DEV_ID_CMP_LP 0x02e0 /* Comet Point LP */
14385 #define MEI_DEV_ID_CMP_LP_3 0x02e4 /* Comet Point LP 3 (iTouch) */
....@@ -152,10 +94,24 @@
15294 #define MEI_DEV_ID_ICP_LP 0x34E0 /* Ice Lake Point LP */
15395 #define MEI_DEV_ID_ICP_N 0x38E0 /* Ice Lake Point N */
15496
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+#define MEI_DEV_ID_JSP_N 0x4DE0 /* Jasper Lake Point N */
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+
15599 #define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */
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+#define MEI_DEV_ID_TGP_H 0x43E0 /* Tiger Lake Point H */
156101
157102 #define MEI_DEV_ID_MCC 0x4B70 /* Mule Creek Canyon (EHL) */
158103 #define MEI_DEV_ID_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */
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+
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+#define MEI_DEV_ID_EBG 0x1BE0 /* Emmitsburg WS */
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+
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+#define MEI_DEV_ID_ADP_S 0x7AE8 /* Alder Lake Point S */
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+#define MEI_DEV_ID_ADP_LP 0x7A60 /* Alder Lake Point LP */
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+#define MEI_DEV_ID_ADP_P 0x51E0 /* Alder Lake Point P */
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+#define MEI_DEV_ID_ADP_N 0x54E0 /* Alder Lake Point N */
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+
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+#define MEI_DEV_ID_RPL_S 0x7A68 /* Raptor Lake Point S */
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+
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+#define MEI_DEV_ID_MTL_M 0x7E70 /* Meteor Lake Point M */
159115
160116 /*
161117 * MEI HW Section
....@@ -164,8 +120,12 @@
164120 /* Host Firmware Status Registers in PCI Config Space */
165121 #define PCI_CFG_HFS_1 0x40
166122 # define PCI_CFG_HFS_1_D0I3_MSK 0x80000000
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+# define PCI_CFG_HFS_1_OPMODE_MSK 0xf0000 /* OP MODE Mask: SPS <= 4.0 */
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+# define PCI_CFG_HFS_1_OPMODE_SPS 0xf0000 /* SPS SKU : SPS <= 4.0 */
167125 #define PCI_CFG_HFS_2 0x48
168126 #define PCI_CFG_HFS_3 0x60
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+# define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070
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+# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
169129 #define PCI_CFG_HFS_4 0x64
170130 #define PCI_CFG_HFS_5 0x68
171131 #define PCI_CFG_HFS_6 0x6C
....@@ -230,7 +190,8 @@
230190 #define ME_IS_HRA 0x00000002
231191 /* ME Interrupt Enable HRA - host read only access to ME_IE */
232192 #define ME_IE_HRA 0x00000001
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-
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+/* TRC control shadow register */
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+#define ME_TRC 0x00000030
234195
235196 /* H_HPG_CSR register bits */
236197 #define H_HPG_CSR_PGIHEXR 0x00000001