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1 | | -/****************************************************************************** |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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| 2 | +/* |
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| 3 | + * Copyright (c) 2003-2019, Intel Corporation. All rights reserved. |
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2 | 4 | * Intel Management Engine Interface (Intel MEI) Linux driver |
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3 | | - * Intel MEI Interface Header |
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4 | | - * |
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5 | | - * This file is provided under a dual BSD/GPLv2 license. When using or |
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6 | | - * redistributing this file, you may do so under either license. |
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7 | | - * |
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8 | | - * GPL LICENSE SUMMARY |
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9 | | - * |
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10 | | - * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
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11 | | - * |
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12 | | - * This program is free software; you can redistribute it and/or modify |
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13 | | - * it under the terms of version 2 of the GNU General Public License as |
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14 | | - * published by the Free Software Foundation. |
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15 | | - * |
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16 | | - * This program is distributed in the hope that it will be useful, but |
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17 | | - * WITHOUT ANY WARRANTY; without even the implied warranty of |
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18 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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19 | | - * General Public License for more details. |
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20 | | - * |
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21 | | - * You should have received a copy of the GNU General Public License |
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22 | | - * along with this program; if not, write to the Free Software |
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23 | | - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
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24 | | - * USA |
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25 | | - * |
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26 | | - * The full GNU General Public License is included in this distribution |
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27 | | - * in the file called LICENSE.GPL. |
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28 | | - * |
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29 | | - * Contact Information: |
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30 | | - * Intel Corporation. |
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31 | | - * linux-mei@linux.intel.com |
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32 | | - * http://www.intel.com |
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33 | | - * |
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34 | | - * BSD LICENSE |
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35 | | - * |
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36 | | - * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
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37 | | - * All rights reserved. |
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38 | | - * |
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39 | | - * Redistribution and use in source and binary forms, with or without |
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40 | | - * modification, are permitted provided that the following conditions |
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41 | | - * are met: |
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42 | | - * |
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43 | | - * * Redistributions of source code must retain the above copyright |
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44 | | - * notice, this list of conditions and the following disclaimer. |
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45 | | - * * Redistributions in binary form must reproduce the above copyright |
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46 | | - * notice, this list of conditions and the following disclaimer in |
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47 | | - * the documentation and/or other materials provided with the |
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48 | | - * distribution. |
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49 | | - * * Neither the name Intel Corporation nor the names of its |
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50 | | - * contributors may be used to endorse or promote products derived |
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51 | | - * from this software without specific prior written permission. |
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52 | | - * |
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53 | | - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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54 | | - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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55 | | - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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56 | | - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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57 | | - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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58 | | - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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59 | | - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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60 | | - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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61 | | - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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62 | | - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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63 | | - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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64 | | - * |
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65 | | - *****************************************************************************/ |
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| 5 | + */ |
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66 | 6 | #ifndef _MEI_HW_MEI_REGS_H_ |
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67 | 7 | #define _MEI_HW_MEI_REGS_H_ |
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68 | 8 | |
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.. | .. |
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119 | 59 | |
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120 | 60 | #define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */ |
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121 | 61 | #define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */ |
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| 62 | +#define MEI_DEV_ID_SPT_3 0x9D3E /* Sunrise Point 3 (iToutch) */ |
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122 | 63 | #define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */ |
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123 | 64 | #define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */ |
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124 | 65 | |
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.. | .. |
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133 | 74 | |
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134 | 75 | #define MEI_DEV_ID_KBP 0xA2BA /* Kaby Point */ |
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135 | 76 | #define MEI_DEV_ID_KBP_2 0xA2BB /* Kaby Point 2 */ |
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| 77 | +#define MEI_DEV_ID_KBP_3 0xA2BE /* Kaby Point 3 (iTouch) */ |
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136 | 78 | |
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137 | 79 | #define MEI_DEV_ID_CNP_LP 0x9DE0 /* Cannon Point LP */ |
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138 | | -#define MEI_DEV_ID_CNP_LP_4 0x9DE4 /* Cannon Point LP 4 (iTouch) */ |
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| 80 | +#define MEI_DEV_ID_CNP_LP_3 0x9DE4 /* Cannon Point LP 3 (iTouch) */ |
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139 | 81 | #define MEI_DEV_ID_CNP_H 0xA360 /* Cannon Point H */ |
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140 | | -#define MEI_DEV_ID_CNP_H_4 0xA364 /* Cannon Point H 4 (iTouch) */ |
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| 82 | +#define MEI_DEV_ID_CNP_H_3 0xA364 /* Cannon Point H 3 (iTouch) */ |
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141 | 83 | |
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142 | 84 | #define MEI_DEV_ID_CMP_LP 0x02e0 /* Comet Point LP */ |
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143 | 85 | #define MEI_DEV_ID_CMP_LP_3 0x02e4 /* Comet Point LP 3 (iTouch) */ |
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.. | .. |
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152 | 94 | #define MEI_DEV_ID_ICP_LP 0x34E0 /* Ice Lake Point LP */ |
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153 | 95 | #define MEI_DEV_ID_ICP_N 0x38E0 /* Ice Lake Point N */ |
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154 | 96 | |
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| 97 | +#define MEI_DEV_ID_JSP_N 0x4DE0 /* Jasper Lake Point N */ |
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| 98 | + |
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155 | 99 | #define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */ |
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| 100 | +#define MEI_DEV_ID_TGP_H 0x43E0 /* Tiger Lake Point H */ |
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156 | 101 | |
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157 | 102 | #define MEI_DEV_ID_MCC 0x4B70 /* Mule Creek Canyon (EHL) */ |
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158 | 103 | #define MEI_DEV_ID_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */ |
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| 104 | + |
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| 105 | +#define MEI_DEV_ID_EBG 0x1BE0 /* Emmitsburg WS */ |
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| 106 | + |
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| 107 | +#define MEI_DEV_ID_ADP_S 0x7AE8 /* Alder Lake Point S */ |
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| 108 | +#define MEI_DEV_ID_ADP_LP 0x7A60 /* Alder Lake Point LP */ |
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| 109 | +#define MEI_DEV_ID_ADP_P 0x51E0 /* Alder Lake Point P */ |
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| 110 | +#define MEI_DEV_ID_ADP_N 0x54E0 /* Alder Lake Point N */ |
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| 111 | + |
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| 112 | +#define MEI_DEV_ID_RPL_S 0x7A68 /* Raptor Lake Point S */ |
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| 113 | + |
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| 114 | +#define MEI_DEV_ID_MTL_M 0x7E70 /* Meteor Lake Point M */ |
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159 | 115 | |
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160 | 116 | /* |
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161 | 117 | * MEI HW Section |
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.. | .. |
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164 | 120 | /* Host Firmware Status Registers in PCI Config Space */ |
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165 | 121 | #define PCI_CFG_HFS_1 0x40 |
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166 | 122 | # define PCI_CFG_HFS_1_D0I3_MSK 0x80000000 |
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| 123 | +# define PCI_CFG_HFS_1_OPMODE_MSK 0xf0000 /* OP MODE Mask: SPS <= 4.0 */ |
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| 124 | +# define PCI_CFG_HFS_1_OPMODE_SPS 0xf0000 /* SPS SKU : SPS <= 4.0 */ |
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167 | 125 | #define PCI_CFG_HFS_2 0x48 |
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168 | 126 | #define PCI_CFG_HFS_3 0x60 |
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| 127 | +# define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070 |
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| 128 | +# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060 |
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169 | 129 | #define PCI_CFG_HFS_4 0x64 |
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170 | 130 | #define PCI_CFG_HFS_5 0x68 |
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171 | 131 | #define PCI_CFG_HFS_6 0x6C |
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.. | .. |
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230 | 190 | #define ME_IS_HRA 0x00000002 |
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231 | 191 | /* ME Interrupt Enable HRA - host read only access to ME_IE */ |
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232 | 192 | #define ME_IE_HRA 0x00000001 |
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233 | | - |
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| 193 | +/* TRC control shadow register */ |
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| 194 | +#define ME_TRC 0x00000030 |
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234 | 195 | |
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235 | 196 | /* H_HPG_CSR register bits */ |
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236 | 197 | #define H_HPG_CSR_PGIHEXR 0x00000001 |
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