add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/mfd/display-serdes/rohm/rohm-bu18rl82.c
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@@ -45,6 +45,7 @@
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 struct serdes_function_data {
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 	u8 gpio_rx_en:1;
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 	u16 gpio_id;
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+	u16 mdelay;
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 };
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 static const char *serdes_gpio_groups[] = {
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@@ -71,6 +72,16 @@
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 	.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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 	.data = (void *)(const struct serdes_function_data []) { \
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 		{ .gpio_rx_en = 0, .gpio_id = id + 2 } \
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+	}, \
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+} \
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+
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+#define FUNCTION_DES_DELAY_MS(ms) \
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+{ \
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+	.name = "DELAY_"#ms"MS", \
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+	.group_names = serdes_gpio_groups, \
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+	.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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+	.data = (void *)(const struct serdes_function_data []) { \
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+		{ .mdelay = ms, } \
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 	}, \
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 } \
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@@ -154,6 +165,12 @@
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 	FUNCTION_DESC_GPIO_OUTPUT_HIGH(),
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 	FUNCTION_DESC_GPIO_OUTPUT_LOW(),
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+
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+	FUNCTION_DES_DELAY_MS(10),
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+	FUNCTION_DES_DELAY_MS(50),
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+	FUNCTION_DES_DELAY_MS(100),
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+	FUNCTION_DES_DELAY_MS(200),
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+	FUNCTION_DES_DELAY_MS(500),
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 };
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 static struct serdes_chip_pinctrl_info bu18rl82_pinctrl_info = {
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@@ -203,34 +220,33 @@
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 static int bu18rl82_bridge_init(struct serdes *serdes)
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 {
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-	return 0;
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-
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 	bu18rl82_bridge_swrst(serdes);
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 	return 0;
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 }
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-static int bu18rl82_bridge_enable(struct serdes *serdes)
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+static int bu18rl82_bridge_pre_enable(struct serdes *serdes)
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 {
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 	int ret = 0;
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 	/* 1:enable 0:disable */
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 	bu18rl82_enable_hwint(serdes, 0);
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234
 
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+	msleep(100);
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+
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 	SERDES_DBG_CHIP("%s: serdes %s ret=%d\n", __func__,
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 			serdes->chip_data->name, ret);
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 	return ret;
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 }
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-static int bu18rl82_bridge_disable(struct serdes *serdes)
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+static int bu18rl82_bridge_post_disable(struct serdes *serdes)
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 {
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 	return 0;
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 }
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 static struct serdes_chip_bridge_ops bu18rl82_bridge_ops = {
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-	.init = bu18rl82_bridge_init,
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-	.enable = bu18rl82_bridge_enable,
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-	.disable = bu18rl82_bridge_disable,
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+	.enable = bu18rl82_bridge_pre_enable,
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+	.disable = bu18rl82_bridge_post_disable,
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 };
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 static int bu18rl82_pinctrl_config_get(struct serdes *serdes,
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@@ -320,6 +336,7 @@
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 	struct function_desc *func;
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 	struct group_desc *grp;
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 	int i, offset;
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+	u16 ms;
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 	func = pinmux_generic_get_function(pinctrl->pctl, function);
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 	if (!func)
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@@ -335,6 +352,7 @@
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 	if (func->data) {
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 		struct serdes_function_data *fdata = func->data;
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+		ms = fdata->mdelay;
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 		for (i = 0; i < grp->num_pins; i++) {
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 			offset = grp->pins[i] - pinctrl->pin_base;
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@@ -344,22 +362,29 @@
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 			else
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 				SERDES_DBG_CHIP("%s: serdes chip %s gpio_id=0x%x, offset=%d\n",
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 						__func__, serdes->chip_data->name, fdata->gpio_id, offset);
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-			serdes_set_bits(serdes, bu18rl82_gpio_oen[offset].reg,
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-					bu18rl82_gpio_oen[offset].mask,
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-					FIELD_PREP(BIT(3), fdata->gpio_rx_en));
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365
 
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-			serdes_set_bits(serdes, bu18rl82_gpio_id_low[offset].reg,
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-					bu18rl82_gpio_id_low[offset].mask,
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-					FIELD_PREP(GENMASK(7, 0),
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-					(fdata->gpio_id & 0xff)));
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+			if (!ms) {
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+				serdes_set_bits(serdes, bu18rl82_gpio_oen[offset].reg,
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+						bu18rl82_gpio_oen[offset].mask,
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+						FIELD_PREP(BIT(3), fdata->gpio_rx_en));
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-			serdes_set_bits(serdes, bu18rl82_gpio_id_high[offset].reg,
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-					bu18rl82_gpio_id_high[offset].mask,
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-					FIELD_PREP(GENMASK(2, 0),
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-					((fdata->gpio_id >> 8) & 0x7)));
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-			serdes_set_bits(serdes, bu18rl82_gpio_pden[offset].reg,
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-					bu18rl82_gpio_pden[offset].mask,
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-					FIELD_PREP(BIT(4), 0));
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+				serdes_set_bits(serdes, bu18rl82_gpio_id_low[offset].reg,
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+						bu18rl82_gpio_id_low[offset].mask,
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+						FIELD_PREP(GENMASK(7, 0),
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+						(fdata->gpio_id & 0xff)));
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+
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+				serdes_set_bits(serdes, bu18rl82_gpio_id_high[offset].reg,
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+						bu18rl82_gpio_id_high[offset].mask,
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+						FIELD_PREP(GENMASK(2, 0),
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+						((fdata->gpio_id >> 8) & 0x7)));
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+				serdes_set_bits(serdes, bu18rl82_gpio_pden[offset].reg,
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+						bu18rl82_gpio_pden[offset].mask,
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+						FIELD_PREP(BIT(4), 0));
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+			} else {
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+				mdelay(ms);
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+				SERDES_DBG_CHIP("%s: delay %d ms\n",
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+						__func__, ms);
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+			}
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 		}
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 	}
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..
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@@ -447,6 +472,7 @@
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 	.serdes_id	= ROHM_ID_BU18RL82,
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 	.bridge_type	= TYPE_BRIDGE_BRIDGE,
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 	.connector_type	= DRM_MODE_CONNECTOR_LVDS,
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+	.chip_init	= bu18rl82_bridge_init,
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 	.regmap_config	= &bu18rl82_regmap_config,
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 	.pinctrl_info	= &bu18rl82_pinctrl_info,
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 	.bridge_ops	= &bu18rl82_bridge_ops,