~hc/RK356X_SDK_RELEASE.git

..	..	@@ -35,6 +35,9 @@
35	35	*
36	36	* Description: RDMA Controller HW interface
37	37	*/
	38	+
	39	+#define dev_fmt(fmt) "QPLIB: " fmt
	40	+
38	41	#include <linux/interrupt.h>
39	42	#include <linux/spinlock.h>
40	43	#include <linux/pci.h>
..	..	@@ -47,17 +50,19 @@
47	50	#include "qplib_sp.h"
48	51	#include "qplib_fp.h"
49	52
50		-static void bnxt_qplib_service_creq(unsigned long data);
	53	+static void bnxt_qplib_service_creq(struct tasklet_struct *t);
51	54
52	55	/* Hardware communication channel */
53	56	static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
54	57	{
	58	+ struct bnxt_qplib_cmdq_ctx *cmdq;
55	59	u16 cbit;
56	60	int rc;
57	61
58		- cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
59		- rc = wait_event_timeout(rcfw->waitq,
60		- !test_bit(cbit, rcfw->cmdq_bitmap),
	62	+ cmdq = &rcfw->cmdq;
	63	+ cbit = cookie % rcfw->cmdq_depth;
	64	+ rc = wait_event_timeout(cmdq->waitq,
	65	+ !test_bit(cbit, cmdq->cmdq_bitmap),
61	66	msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS));
62	67	return rc ? 0 : -ETIMEDOUT;
63	68	};
..	..	@@ -65,15 +70,17 @@
65	70	static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
66	71	{
67	72	u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT;
	73	+ struct bnxt_qplib_cmdq_ctx *cmdq;
68	74	u16 cbit;
69	75
70		- cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
71		- if (!test_bit(cbit, rcfw->cmdq_bitmap))
	76	+ cmdq = &rcfw->cmdq;
	77	+ cbit = cookie % rcfw->cmdq_depth;
	78	+ if (!test_bit(cbit, cmdq->cmdq_bitmap))
72	79	goto done;
73	80	do {
74	81	mdelay(1); /* 1m sec */
75		- bnxt_qplib_service_creq((unsigned long)rcfw);
76		- } while (test_bit(cbit, rcfw->cmdq_bitmap) && --count);
	82	+ bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
	83	+ } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count);
77	84	done:
78	85	return count ? 0 : -ETIMEDOUT;
79	86	};
..	..	@@ -81,58 +88,68 @@
81	88	static int __send_message(struct bnxt_qplib_rcfw rcfw, struct cmdq_base req,
82	89	struct creq_base resp, void sb, u8 is_block)
83	90	{
84		- struct bnxt_qplib_cmdqe cmdqe, *cmdq_ptr;
85		- struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
86		- struct bnxt_qplib_crsq *crsqe;
	91	+ struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
	92	+ struct bnxt_qplib_hwq *hwq = &cmdq->hwq;
	93	+ struct bnxt_qplib_crsqe *crsqe;
	94	+ struct bnxt_qplib_cmdqe *cmdqe;
87	95	u32 sw_prod, cmdq_prod;
	96	+ struct pci_dev *pdev;
88	97	unsigned long flags;
89	98	u32 size, opcode;
90	99	u16 cookie, cbit;
91	100	u8 *preq;
92	101
	102	+ pdev = rcfw->pdev;
	103	+
93	104	opcode = req->opcode;
94		- if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&
	105	+ if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
95	106	(opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&
96	107	opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW &&
97	108	opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) {
98		- dev_err(&rcfw->pdev->dev,
99		- "QPLIB: RCFW not initialized, reject opcode 0x%x",
100		- opcode);
	109	+ dev_err(&pdev->dev,
	110	+ "RCFW not initialized, reject opcode 0x%x\n", opcode);
101	111	return -EINVAL;
102	112	}
103	113
104		- if (test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&
	114	+ if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
105	115	opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {
106		- dev_err(&rcfw->pdev->dev, "QPLIB: RCFW already initialized!");
	116	+ dev_err(&pdev->dev, "RCFW already initialized!\n");
107	117	return -EINVAL;
108	118	}
109	119
110		- if (test_bit(FIRMWARE_TIMED_OUT, &rcfw->flags))
	120	+ if (test_bit(FIRMWARE_TIMED_OUT, &cmdq->flags))
111	121	return -ETIMEDOUT;
112	122
113	123	/* Cmdq are in 16-byte units, each request can consume 1 or more
114	124	* cmdqe
115	125	*/
116		- spin_lock_irqsave(&cmdq->lock, flags);
117		- if (req->cmd_size >= HWQ_FREE_SLOTS(cmdq)) {
118		- dev_err(&rcfw->pdev->dev, "QPLIB: RCFW: CMDQ is full!");
119		- spin_unlock_irqrestore(&cmdq->lock, flags);
	126	+ spin_lock_irqsave(&hwq->lock, flags);
	127	+ if (req->cmd_size >= HWQ_FREE_SLOTS(hwq)) {
	128	+ dev_err(&pdev->dev, "RCFW: CMDQ is full!\n");
	129	+ spin_unlock_irqrestore(&hwq->lock, flags);
120	130	return -EAGAIN;
121	131	}
122	132
123	133
124		- cookie = rcfw->seq_num & RCFW_MAX_COOKIE_VALUE;
125		- cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
	134	+ cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE;
	135	+ cbit = cookie % rcfw->cmdq_depth;
126	136	if (is_block)
127	137	cookie \|= RCFW_CMD_IS_BLOCKING;
128	138
129		- set_bit(cbit, rcfw->cmdq_bitmap);
	139	+ set_bit(cbit, cmdq->cmdq_bitmap);
130	140	req->cookie = cpu_to_le16(cookie);
131	141	crsqe = &rcfw->crsqe_tbl[cbit];
132	142	if (crsqe->resp) {
133		- spin_unlock_irqrestore(&cmdq->lock, flags);
	143	+ spin_unlock_irqrestore(&hwq->lock, flags);
134	144	return -EBUSY;
135	145	}
	146	+
	147	+ size = req->cmd_size;
	148	+ /* change the cmd_size to the number of 16byte cmdq unit.
	149	+ * req->cmd_size is modified here
	150	+ */
	151	+ bnxt_qplib_set_cmd_slots(req);
	152	+
136	153	memset(resp, 0, sizeof(*resp));
137	154	crsqe->resp = (struct creq_qp_event *)resp;
138	155	crsqe->resp->cookie = req->cookie;
..	..	@@ -145,16 +162,14 @@
145	162	BNXT_QPLIB_CMDQE_UNITS;
146	163	}
147	164
148		- cmdq_ptr = (struct bnxt_qplib_cmdqe **)cmdq->pbl_ptr;
149	165	preq = (u8 *)req;
150		- size = req->cmd_size * BNXT_QPLIB_CMDQE_UNITS;
151	166	do {
152	167	/* Locate the next cmdq slot */
153		- sw_prod = HWQ_CMP(cmdq->prod, cmdq);
154		- cmdqe = &cmdq_ptr[get_cmdq_pg(sw_prod)][get_cmdq_idx(sw_prod)];
	168	+ sw_prod = HWQ_CMP(hwq->prod, hwq);
	169	+ cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL);
155	170	if (!cmdqe) {
156		- dev_err(&rcfw->pdev->dev,
157		- "QPLIB: RCFW request failed with no cmdqe!");
	171	+ dev_err(&pdev->dev,
	172	+ "RCFW request failed with no cmdqe!\n");
158	173	goto done;
159	174	}
160	175	/* Copy a segment of the req cmd to the cmdq */
..	..	@@ -162,31 +177,27 @@
162	177	memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe)));
163	178	preq += min_t(u32, size, sizeof(*cmdqe));
164	179	size -= min_t(u32, size, sizeof(*cmdqe));
165		- cmdq->prod++;
166		- rcfw->seq_num++;
	180	+ hwq->prod++;
167	181	} while (size > 0);
	182	+ cmdq->seq_num++;
168	183
169		- rcfw->seq_num++;
170		-
171		- cmdq_prod = cmdq->prod;
172		- if (test_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags)) {
	184	+ cmdq_prod = hwq->prod & 0xFFFF;
	185	+ if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) {
173	186	/* The very first doorbell write
174	187	* is required to set this flag
175	188	* which prompts the FW to reset
176	189	* its internal pointers
177	190	*/
178	191	cmdq_prod \|= BIT(FIRMWARE_FIRST_FLAG);
179		- clear_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags);
	192	+ clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
180	193	}
181	194
182	195	/* ring CMDQ DB */
183	196	wmb();
184		- writel(cmdq_prod, rcfw->cmdq_bar_reg_iomem +
185		- rcfw->cmdq_bar_reg_prod_off);
186		- writel(RCFW_CMDQ_TRIG_VAL, rcfw->cmdq_bar_reg_iomem +
187		- rcfw->cmdq_bar_reg_trig_off);
	197	+ writel(cmdq_prod, cmdq->cmdq_mbox.prod);
	198	+ writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
188	199	done:
189		- spin_unlock_irqrestore(&cmdq->lock, flags);
	200	+ spin_unlock_irqrestore(&hwq->lock, flags);
190	201	/* Return the CREQ response pointer */
191	202	return 0;
192	203	}
..	..	@@ -210,7 +221,7 @@
210	221
211	222	if (!retry_cnt \|\| (rc != -EAGAIN && rc != -EBUSY)) {
212	223	/* send failed */
213		- dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x send failed",
	224	+ dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n",
214	225	cookie, opcode);
215	226	return rc;
216	227	}
..	..	@@ -224,15 +235,15 @@
224	235	rc = __wait_for_resp(rcfw, cookie);
225	236	if (rc) {
226	237	/* timed out */
227		- dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x timedout (%d)msec",
	238	+ dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n",
228	239	cookie, opcode, RCFW_CMD_WAIT_TIME_MS);
229		- set_bit(FIRMWARE_TIMED_OUT, &rcfw->flags);
	240	+ set_bit(FIRMWARE_TIMED_OUT, &rcfw->cmdq.flags);
230	241	return rc;
231	242	}
232	243
233	244	if (evnt->status) {
234	245	/* failed with status */
235		- dev_err(&rcfw->pdev->dev, "QPLIB: cmdq[%#x]=%#x status %#x",
	246	+ dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n",
236	247	cookie, opcode, evnt->status);
237	248	rc = -EFAULT;
238	249	}
..	..	@@ -243,6 +254,8 @@
243	254	static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,
244	255	struct creq_func_event *func_event)
245	256	{
	257	+ int rc;
	258	+
246	259	switch (func_event->event) {
247	260	case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
248	261	break;
..	..	@@ -276,37 +289,44 @@
276	289	default:
277	290	return -EINVAL;
278	291	}
279		- return 0;
	292	+
	293	+ rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL);
	294	+ return rc;
280	295	}
281	296
282	297	static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
283		- struct creq_qp_event *qp_event)
	298	+ struct creq_qp_event *qp_event,
	299	+ u32 *num_wait)
284	300	{
285		- struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
286	301	struct creq_qp_error_notification *err_event;
287		- struct bnxt_qplib_crsq *crsqe;
288		- unsigned long flags;
	302	+ struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq;
	303	+ struct bnxt_qplib_crsqe *crsqe;
289	304	struct bnxt_qplib_qp *qp;
290	305	u16 cbit, blocked = 0;
291		- u16 cookie;
	306	+ struct pci_dev *pdev;
	307	+ unsigned long flags;
	308	+ u32 wait_cmds = 0;
292	309	__le16 mcookie;
293		- u32 qp_id;
	310	+ u16 cookie;
	311	+ int rc = 0;
	312	+ u32 qp_id, tbl_indx;
294	313
	314	+ pdev = rcfw->pdev;
295	315	switch (qp_event->event) {
296	316	case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
297	317	err_event = (struct creq_qp_error_notification *)qp_event;
298	318	qp_id = le32_to_cpu(err_event->xid);
299		- qp = rcfw->qp_tbl[qp_id].qp_handle;
300		- dev_dbg(&rcfw->pdev->dev,
301		- "QPLIB: Received QP error notification");
302		- dev_dbg(&rcfw->pdev->dev,
303		- "QPLIB: qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
	319	+ tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw);
	320	+ qp = rcfw->qp_tbl[tbl_indx].qp_handle;
	321	+ dev_dbg(&pdev->dev, "Received QP error notification\n");
	322	+ dev_dbg(&pdev->dev,
	323	+ "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
304	324	qp_id, err_event->req_err_state_reason,
305	325	err_event->res_err_state_reason);
306	326	if (!qp)
307	327	break;
308	328	bnxt_qplib_mark_qp_error(qp);
309		- rcfw->aeq_handler(rcfw, qp_event, qp);
	329	+ rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp);
310	330	break;
311	331	default:
312	332	/*
..	..	@@ -318,55 +338,59 @@
318	338	*
319	339	*/
320	340
321		- spin_lock_irqsave_nested(&cmdq->lock, flags,
	341	+ spin_lock_irqsave_nested(&hwq->lock, flags,
322	342	SINGLE_DEPTH_NESTING);
323	343	cookie = le16_to_cpu(qp_event->cookie);
324	344	mcookie = qp_event->cookie;
325	345	blocked = cookie & RCFW_CMD_IS_BLOCKING;
326	346	cookie &= RCFW_MAX_COOKIE_VALUE;
327		- cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
	347	+ cbit = cookie % rcfw->cmdq_depth;
328	348	crsqe = &rcfw->crsqe_tbl[cbit];
329	349	if (crsqe->resp &&
330	350	crsqe->resp->cookie == mcookie) {
331	351	memcpy(crsqe->resp, qp_event, sizeof(*qp_event));
332	352	crsqe->resp = NULL;
333	353	} else {
334		- dev_err(&rcfw->pdev->dev,
335		- "QPLIB: CMD %s resp->cookie = %#x, evnt->cookie = %#x",
336		- crsqe->resp ? "mismatch" : "collision",
337		- crsqe->resp ? crsqe->resp->cookie : 0, mcookie);
	354	+ if (crsqe->resp && crsqe->resp->cookie)
	355	+ dev_err(&pdev->dev,
	356	+ "CMD %s cookie sent=%#x, recd=%#x\n",
	357	+ crsqe->resp ? "mismatch" : "collision",
	358	+ crsqe->resp ? crsqe->resp->cookie : 0,
	359	+ mcookie);
338	360	}
339		- if (!test_and_clear_bit(cbit, rcfw->cmdq_bitmap))
340		- dev_warn(&rcfw->pdev->dev,
341		- "QPLIB: CMD bit %d was not requested", cbit);
342		- cmdq->cons += crsqe->req_size;
	361	+ if (!test_and_clear_bit(cbit, rcfw->cmdq.cmdq_bitmap))
	362	+ dev_warn(&pdev->dev,
	363	+ "CMD bit %d was not requested\n", cbit);
	364	+ hwq->cons += crsqe->req_size;
343	365	crsqe->req_size = 0;
344	366
345	367	if (!blocked)
346		- wake_up(&rcfw->waitq);
347		- spin_unlock_irqrestore(&cmdq->lock, flags);
	368	+ wait_cmds++;
	369	+ spin_unlock_irqrestore(&hwq->lock, flags);
348	370	}
349		- return 0;
	371	+ *num_wait += wait_cmds;
	372	+ return rc;
350	373	}
351	374
352	375	/* SP - CREQ Completion handlers */
353		-static void bnxt_qplib_service_creq(unsigned long data)
	376	+static void bnxt_qplib_service_creq(struct tasklet_struct *t)
354	377	{
355		- struct bnxt_qplib_rcfw rcfw = (struct bnxt_qplib_rcfw )data;
356		- struct bnxt_qplib_hwq *creq = &rcfw->creq;
357		- struct creq_base creqe, *creq_ptr;
	378	+ struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet);
	379	+ struct bnxt_qplib_creq_ctx *creq = &rcfw->creq;
	380	+ u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
	381	+ struct bnxt_qplib_hwq *hwq = &creq->hwq;
	382	+ struct creq_base *creqe;
358	383	u32 sw_cons, raw_cons;
359	384	unsigned long flags;
360		- u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
	385	+ u32 num_wakeup = 0;
361	386
362	387	/* Service the CREQ until budget is over */
363		- spin_lock_irqsave(&creq->lock, flags);
364		- raw_cons = creq->cons;
	388	+ spin_lock_irqsave(&hwq->lock, flags);
	389	+ raw_cons = hwq->cons;
365	390	while (budget > 0) {
366		- sw_cons = HWQ_CMP(raw_cons, creq);
367		- creq_ptr = (struct creq_base **)creq->pbl_ptr;
368		- creqe = &creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)];
369		- if (!CREQ_CMP_VALID(creqe, raw_cons, creq->max_elements))
	391	+ sw_cons = HWQ_CMP(raw_cons, hwq);
	392	+ creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL);
	393	+ if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements))
370	394	break;
371	395	/* The valid test of the entry must be done first before
372	396	* reading any further.
..	..	@@ -377,49 +401,53 @@
377	401	switch (type) {
378	402	case CREQ_BASE_TYPE_QP_EVENT:
379	403	bnxt_qplib_process_qp_event
380		- (rcfw, (struct creq_qp_event *)creqe);
381		- rcfw->creq_qp_event_processed++;
	404	+ (rcfw, (struct creq_qp_event *)creqe,
	405	+ &num_wakeup);
	406	+ creq->stats.creq_qp_event_processed++;
382	407	break;
383	408	case CREQ_BASE_TYPE_FUNC_EVENT:
384	409	if (!bnxt_qplib_process_func_event
385	410	(rcfw, (struct creq_func_event *)creqe))
386		- rcfw->creq_func_event_processed++;
	411	+ creq->stats.creq_func_event_processed++;
387	412	else
388		- dev_warn
389		- (&rcfw->pdev->dev, "QPLIB:aeqe:%#x Not handled",
390		- type);
	413	+ dev_warn(&rcfw->pdev->dev,
	414	+ "aeqe:%#x Not handled\n", type);
391	415	break;
392	416	default:
393		- dev_warn(&rcfw->pdev->dev, "QPLIB: creqe with ");
394		- dev_warn(&rcfw->pdev->dev,
395		- "QPLIB: op_event = 0x%x not handled", type);
	417	+ if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT)
	418	+ dev_warn(&rcfw->pdev->dev,
	419	+ "creqe with event 0x%x not handled\n",
	420	+ type);
396	421	break;
397	422	}
398	423	raw_cons++;
399	424	budget--;
400	425	}
401	426
402		- if (creq->cons != raw_cons) {
403		- creq->cons = raw_cons;
404		- CREQ_DB_REARM(rcfw->creq_bar_reg_iomem, raw_cons,
405		- creq->max_elements);
	427	+ if (hwq->cons != raw_cons) {
	428	+ hwq->cons = raw_cons;
	429	+ bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo,
	430	+ rcfw->res->cctx, true);
406	431	}
407		- spin_unlock_irqrestore(&creq->lock, flags);
	432	+ spin_unlock_irqrestore(&hwq->lock, flags);
	433	+ if (num_wakeup)
	434	+ wake_up_nr(&rcfw->cmdq.waitq, num_wakeup);
408	435	}
409	436
410	437	static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance)
411	438	{
412	439	struct bnxt_qplib_rcfw *rcfw = dev_instance;
413		- struct bnxt_qplib_hwq *creq = &rcfw->creq;
414		- struct creq_base **creq_ptr;
	440	+ struct bnxt_qplib_creq_ctx *creq;
	441	+ struct bnxt_qplib_hwq *hwq;
415	442	u32 sw_cons;
416	443
	444	+ creq = &rcfw->creq;
	445	+ hwq = &creq->hwq;
417	446	/* Prefetch the CREQ element */
418		- sw_cons = HWQ_CMP(creq->cons, creq);
419		- creq_ptr = (struct creq_base **)rcfw->creq.pbl_ptr;
420		- prefetch(&creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)]);
	447	+ sw_cons = HWQ_CMP(hwq->cons, hwq);
	448	+ prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL));
421	449
422		- tasklet_schedule(&rcfw->worker);
	450	+ tasklet_schedule(&creq->creq_tasklet);
423	451
424	452	return IRQ_HANDLED;
425	453	}
..	..	@@ -438,33 +466,17 @@
438	466	if (rc)
439	467	return rc;
440	468
441		- clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);
	469	+ clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
442	470	return 0;
443		-}
444		-
445		-static int __get_pbl_pg_idx(struct bnxt_qplib_pbl *pbl)
446		-{
447		- return (pbl->pg_size == ROCE_PG_SIZE_4K ?
448		- CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K :
449		- pbl->pg_size == ROCE_PG_SIZE_8K ?
450		- CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K :
451		- pbl->pg_size == ROCE_PG_SIZE_64K ?
452		- CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K :
453		- pbl->pg_size == ROCE_PG_SIZE_2M ?
454		- CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M :
455		- pbl->pg_size == ROCE_PG_SIZE_8M ?
456		- CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M :
457		- pbl->pg_size == ROCE_PG_SIZE_1G ?
458		- CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G :
459		- CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K);
460	471	}
461	472
462	473	int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
463	474	struct bnxt_qplib_ctx *ctx, int is_virtfn)
464	475	{
465		- struct cmdq_initialize_fw req;
466	476	struct creq_initialize_fw_resp resp;
467		- u16 cmd_flags = 0, level;
	477	+ struct cmdq_initialize_fw req;
	478	+ u16 cmd_flags = 0;
	479	+ u8 pgsz, lvl;
468	480	int rc;
469	481
470	482	RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags);
..	..	@@ -474,38 +486,41 @@
474	486	req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT -
475	487	RCFW_DBR_BASE_PAGE_SHIFT);
476	488	/*
477		- * VFs need not setup the HW context area, PF
	489	+ * Gen P5 devices doesn't require this allocation
	490	+ * as the L2 driver does the same for RoCE also.
	491	+ * Also, VFs need not setup the HW context area, PF
478	492	* shall setup this area for VF. Skipping the
479	493	* HW programming
480	494	*/
481	495	if (is_virtfn)
482	496	goto skip_ctx_setup;
	497	+ if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx))
	498	+ goto config_vf_res;
483	499
484		- level = ctx->qpc_tbl.level;
485		- req.qpc_pg_size_qpc_lvl = (level << CMDQ_INITIALIZE_FW_QPC_LVL_SFT) \|
486		- __get_pbl_pg_idx(&ctx->qpc_tbl.pbl[level]);
487		- level = ctx->mrw_tbl.level;
488		- req.mrw_pg_size_mrw_lvl = (level << CMDQ_INITIALIZE_FW_MRW_LVL_SFT) \|
489		- __get_pbl_pg_idx(&ctx->mrw_tbl.pbl[level]);
490		- level = ctx->srqc_tbl.level;
491		- req.srq_pg_size_srq_lvl = (level << CMDQ_INITIALIZE_FW_SRQ_LVL_SFT) \|
492		- __get_pbl_pg_idx(&ctx->srqc_tbl.pbl[level]);
493		- level = ctx->cq_tbl.level;
494		- req.cq_pg_size_cq_lvl = (level << CMDQ_INITIALIZE_FW_CQ_LVL_SFT) \|
495		- __get_pbl_pg_idx(&ctx->cq_tbl.pbl[level]);
496		- level = ctx->srqc_tbl.level;
497		- req.srq_pg_size_srq_lvl = (level << CMDQ_INITIALIZE_FW_SRQ_LVL_SFT) \|
498		- __get_pbl_pg_idx(&ctx->srqc_tbl.pbl[level]);
499		- level = ctx->cq_tbl.level;
500		- req.cq_pg_size_cq_lvl = (level << CMDQ_INITIALIZE_FW_CQ_LVL_SFT) \|
501		- __get_pbl_pg_idx(&ctx->cq_tbl.pbl[level]);
502		- level = ctx->tim_tbl.level;
503		- req.tim_pg_size_tim_lvl = (level << CMDQ_INITIALIZE_FW_TIM_LVL_SFT) \|
504		- __get_pbl_pg_idx(&ctx->tim_tbl.pbl[level]);
505		- level = ctx->tqm_pde_level;
506		- req.tqm_pg_size_tqm_lvl = (level << CMDQ_INITIALIZE_FW_TQM_LVL_SFT) \|
507		- __get_pbl_pg_idx(&ctx->tqm_pde.pbl[level]);
508		-
	500	+ lvl = ctx->qpc_tbl.level;
	501	+ pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl);
	502	+ req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) \|
	503	+ lvl;
	504	+ lvl = ctx->mrw_tbl.level;
	505	+ pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl);
	506	+ req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) \|
	507	+ lvl;
	508	+ lvl = ctx->srqc_tbl.level;
	509	+ pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl);
	510	+ req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) \|
	511	+ lvl;
	512	+ lvl = ctx->cq_tbl.level;
	513	+ pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl);
	514	+ req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) \|
	515	+ lvl;
	516	+ lvl = ctx->tim_tbl.level;
	517	+ pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl);
	518	+ req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) \|
	519	+ lvl;
	520	+ lvl = ctx->tqm_ctx.pde.level;
	521	+ pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde);
	522	+ req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) \|
	523	+ lvl;
509	524	req.qpc_page_dir =
510	525	cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
511	526	req.mrw_page_dir =
..	..	@@ -517,13 +532,14 @@
517	532	req.tim_page_dir =
518	533	cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
519	534	req.tqm_page_dir =
520		- cpu_to_le64(ctx->tqm_pde.pbl[PBL_LVL_0].pg_map_arr[0]);
	535	+ cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]);
521	536
522	537	req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements);
523	538	req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements);
524	539	req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements);
525	540	req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements);
526	541
	542	+config_vf_res:
527	543	req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
528	544	req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
529	545	req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
..	..	@@ -536,50 +552,78 @@
536	552	NULL, 0);
537	553	if (rc)
538	554	return rc;
539		- set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);
	555	+ set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
540	556	return 0;
541	557	}
542	558
543	559	void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
544	560	{
	561	+ kfree(rcfw->cmdq.cmdq_bitmap);
545	562	kfree(rcfw->qp_tbl);
546	563	kfree(rcfw->crsqe_tbl);
547		- bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->cmdq);
548		- bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->creq);
	564	+ bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq);
	565	+ bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq);
549	566	rcfw->pdev = NULL;
550	567	}
551	568
552		-int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
	569	+int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
553	570	struct bnxt_qplib_rcfw *rcfw,
	571	+ struct bnxt_qplib_ctx *ctx,
554	572	int qp_tbl_sz)
555	573	{
556		- rcfw->pdev = pdev;
557		- rcfw->creq.max_elements = BNXT_QPLIB_CREQE_MAX_CNT;
558		- if (bnxt_qplib_alloc_init_hwq(rcfw->pdev, &rcfw->creq, NULL, 0,
559		- &rcfw->creq.max_elements,
560		- BNXT_QPLIB_CREQE_UNITS, 0, PAGE_SIZE,
561		- HWQ_TYPE_L2_CMPL)) {
	574	+ struct bnxt_qplib_hwq_attr hwq_attr = {};
	575	+ struct bnxt_qplib_sg_info sginfo = {};
	576	+ struct bnxt_qplib_cmdq_ctx *cmdq;
	577	+ struct bnxt_qplib_creq_ctx *creq;
	578	+ u32 bmap_size = 0;
	579	+
	580	+ rcfw->pdev = res->pdev;
	581	+ cmdq = &rcfw->cmdq;
	582	+ creq = &rcfw->creq;
	583	+ rcfw->res = res;
	584	+
	585	+ sginfo.pgsize = PAGE_SIZE;
	586	+ sginfo.pgshft = PAGE_SHIFT;
	587	+
	588	+ hwq_attr.sginfo = &sginfo;
	589	+ hwq_attr.res = rcfw->res;
	590	+ hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT;
	591	+ hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS;
	592	+ hwq_attr.type = bnxt_qplib_get_hwq_type(res);
	593	+
	594	+ if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) {
562	595	dev_err(&rcfw->pdev->dev,
563		- "QPLIB: HW channel CREQ allocation failed");
	596	+ "HW channel CREQ allocation failed\n");
564	597	goto fail;
565	598	}
566		- rcfw->cmdq.max_elements = BNXT_QPLIB_CMDQE_MAX_CNT;
567		- if (bnxt_qplib_alloc_init_hwq(rcfw->pdev, &rcfw->cmdq, NULL, 0,
568		- &rcfw->cmdq.max_elements,
569		- BNXT_QPLIB_CMDQE_UNITS, 0, PAGE_SIZE,
570		- HWQ_TYPE_CTX)) {
	599	+ if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK)
	600	+ rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256;
	601	+ else
	602	+ rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192;
	603	+
	604	+ sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth);
	605	+ hwq_attr.depth = rcfw->cmdq_depth & 0x7FFFFFFF;
	606	+ hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS;
	607	+ hwq_attr.type = HWQ_TYPE_CTX;
	608	+ if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) {
571	609	dev_err(&rcfw->pdev->dev,
572		- "QPLIB: HW channel CMDQ allocation failed");
	610	+ "HW channel CMDQ allocation failed\n");
573	611	goto fail;
574	612	}
575	613
576		- rcfw->crsqe_tbl = kcalloc(rcfw->cmdq.max_elements,
	614	+ rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements,
577	615	sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
578	616	if (!rcfw->crsqe_tbl)
579	617	goto fail;
580	618
581		- rcfw->qp_tbl_size = qp_tbl_sz;
582		- rcfw->qp_tbl = kcalloc(qp_tbl_sz, sizeof(struct bnxt_qplib_qp_node),
	619	+ bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth) * sizeof(unsigned long);
	620	+ cmdq->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL);
	621	+ if (!cmdq->cmdq_bitmap)
	622	+ goto fail;
	623	+
	624	+ /* Allocate one extra to hold the QP1 entries */
	625	+ rcfw->qp_tbl_size = qp_tbl_sz + 1;
	626	+ rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node),
583	627	GFP_KERNEL);
584	628	if (!rcfw->qp_tbl)
585	629	goto fail;
..	..	@@ -593,153 +637,224 @@
593	637
594	638	void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill)
595	639	{
596		- tasklet_disable(&rcfw->worker);
597		- /* Mask h/w interrupts */
598		- CREQ_DB(rcfw->creq_bar_reg_iomem, rcfw->creq.cons,
599		- rcfw->creq.max_elements);
600		- /* Sync with last running IRQ-handler */
601		- synchronize_irq(rcfw->vector);
602		- if (kill)
603		- tasklet_kill(&rcfw->worker);
	640	+ struct bnxt_qplib_creq_ctx *creq;
604	641
605		- if (rcfw->requested) {
606		- free_irq(rcfw->vector, rcfw);
607		- rcfw->requested = false;
608		- }
	642	+ creq = &rcfw->creq;
	643	+
	644	+ if (!creq->requested)
	645	+ return;
	646	+
	647	+ tasklet_disable(&creq->creq_tasklet);
	648	+ /* Mask h/w interrupts */
	649	+ bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false);
	650	+ /* Sync with last running IRQ-handler */
	651	+ synchronize_irq(creq->msix_vec);
	652	+ if (kill)
	653	+ tasklet_kill(&creq->creq_tasklet);
	654	+
	655	+ free_irq(creq->msix_vec, rcfw);
	656	+ kfree(creq->irq_name);
	657	+ creq->irq_name = NULL;
	658	+ creq->requested = false;
609	659	}
610	660
611	661	void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
612	662	{
	663	+ struct bnxt_qplib_creq_ctx *creq;
	664	+ struct bnxt_qplib_cmdq_ctx *cmdq;
613	665	unsigned long indx;
614	666
	667	+ creq = &rcfw->creq;
	668	+ cmdq = &rcfw->cmdq;
	669	+ /* Make sure the HW channel is stopped! */
615	670	bnxt_qplib_rcfw_stop_irq(rcfw, true);
616	671
617		- iounmap(rcfw->cmdq_bar_reg_iomem);
618		- iounmap(rcfw->creq_bar_reg_iomem);
	672	+ iounmap(cmdq->cmdq_mbox.reg.bar_reg);
	673	+ iounmap(creq->creq_db.reg.bar_reg);
619	674
620		- indx = find_first_bit(rcfw->cmdq_bitmap, rcfw->bmap_size);
621		- if (indx != rcfw->bmap_size)
	675	+ indx = find_first_bit(cmdq->cmdq_bitmap, rcfw->cmdq_depth);
	676	+ if (indx != rcfw->cmdq_depth)
622	677	dev_err(&rcfw->pdev->dev,
623		- "QPLIB: disabling RCFW with pending cmd-bit %lx", indx);
624		- kfree(rcfw->cmdq_bitmap);
625		- rcfw->bmap_size = 0;
	678	+ "disabling RCFW with pending cmd-bit %lx\n", indx);
626	679
627		- rcfw->cmdq_bar_reg_iomem = NULL;
628		- rcfw->creq_bar_reg_iomem = NULL;
629		- rcfw->aeq_handler = NULL;
630		- rcfw->vector = 0;
	680	+ cmdq->cmdq_mbox.reg.bar_reg = NULL;
	681	+ creq->creq_db.reg.bar_reg = NULL;
	682	+ creq->aeq_handler = NULL;
	683	+ creq->msix_vec = 0;
631	684	}
632	685
633	686	int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
634	687	bool need_init)
635	688	{
	689	+ struct bnxt_qplib_creq_ctx *creq;
	690	+ struct bnxt_qplib_res *res;
636	691	int rc;
637	692
638		- if (rcfw->requested)
	693	+ creq = &rcfw->creq;
	694	+ res = rcfw->res;
	695	+
	696	+ if (creq->requested)
639	697	return -EFAULT;
640	698
641		- rcfw->vector = msix_vector;
	699	+ creq->msix_vec = msix_vector;
642	700	if (need_init)
643		- tasklet_init(&rcfw->worker,
644		- bnxt_qplib_service_creq, (unsigned long)rcfw);
	701	+ tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq);
645	702	else
646		- tasklet_enable(&rcfw->worker);
647		- rc = request_irq(rcfw->vector, bnxt_qplib_creq_irq, 0,
648		- "bnxt_qplib_creq", rcfw);
649		- if (rc)
	703	+ tasklet_enable(&creq->creq_tasklet);
	704	+
	705	+ creq->irq_name = kasprintf(GFP_KERNEL, "bnxt_re-creq@pci:%s",
	706	+ pci_name(res->pdev));
	707	+ if (!creq->irq_name)
	708	+ return -ENOMEM;
	709	+ rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0,
	710	+ creq->irq_name, rcfw);
	711	+ if (rc) {
	712	+ kfree(creq->irq_name);
	713	+ creq->irq_name = NULL;
	714	+ tasklet_disable(&creq->creq_tasklet);
650	715	return rc;
651		- rcfw->requested = true;
652		- CREQ_DB_REARM(rcfw->creq_bar_reg_iomem, rcfw->creq.cons,
653		- rcfw->creq.max_elements);
	716	+ }
	717	+ creq->requested = true;
	718	+
	719	+ bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, res->cctx, true);
654	720
655	721	return 0;
656	722	}
657	723
658		-int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
659		- struct bnxt_qplib_rcfw *rcfw,
	724	+static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw, bool is_vf)
	725	+{
	726	+ struct bnxt_qplib_cmdq_mbox *mbox;
	727	+ resource_size_t bar_reg;
	728	+ struct pci_dev *pdev;
	729	+ u16 prod_offt;
	730	+ int rc = 0;
	731	+
	732	+ pdev = rcfw->pdev;
	733	+ mbox = &rcfw->cmdq.cmdq_mbox;
	734	+
	735	+ mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION;
	736	+ mbox->reg.len = RCFW_COMM_SIZE;
	737	+ mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id);
	738	+ if (!mbox->reg.bar_base) {
	739	+ dev_err(&pdev->dev,
	740	+ "QPLIB: CMDQ BAR region %d resc start is 0!\n",
	741	+ mbox->reg.bar_id);
	742	+ return -ENOMEM;
	743	+ }
	744	+
	745	+ bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET;
	746	+ mbox->reg.len = RCFW_COMM_SIZE;
	747	+ mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len);
	748	+ if (!mbox->reg.bar_reg) {
	749	+ dev_err(&pdev->dev,
	750	+ "QPLIB: CMDQ BAR region %d mapping failed\n",
	751	+ mbox->reg.bar_id);
	752	+ return -ENOMEM;
	753	+ }
	754	+
	755	+ prod_offt = is_vf ? RCFW_VF_COMM_PROD_OFFSET :
	756	+ RCFW_PF_COMM_PROD_OFFSET;
	757	+ mbox->prod = (void __iomem *)(mbox->reg.bar_reg + prod_offt);
	758	+ mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET);
	759	+ return rc;
	760	+}
	761	+
	762	+static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt)
	763	+{
	764	+ struct bnxt_qplib_creq_db *creq_db;
	765	+ resource_size_t bar_reg;
	766	+ struct pci_dev *pdev;
	767	+
	768	+ pdev = rcfw->pdev;
	769	+ creq_db = &rcfw->creq.creq_db;
	770	+
	771	+ creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION;
	772	+ creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id);
	773	+ if (!creq_db->reg.bar_id)
	774	+ dev_err(&pdev->dev,
	775	+ "QPLIB: CREQ BAR region %d resc start is 0!",
	776	+ creq_db->reg.bar_id);
	777	+
	778	+ bar_reg = creq_db->reg.bar_base + reg_offt;
	779	+ /* Unconditionally map 8 bytes to support 57500 series */
	780	+ creq_db->reg.len = 8;
	781	+ creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len);
	782	+ if (!creq_db->reg.bar_reg) {
	783	+ dev_err(&pdev->dev,
	784	+ "QPLIB: CREQ BAR region %d mapping failed",
	785	+ creq_db->reg.bar_id);
	786	+ return -ENOMEM;
	787	+ }
	788	+ creq_db->dbinfo.db = creq_db->reg.bar_reg;
	789	+ creq_db->dbinfo.hwq = &rcfw->creq.hwq;
	790	+ creq_db->dbinfo.xid = rcfw->creq.ring_id;
	791	+ return 0;
	792	+}
	793	+
	794	+static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw)
	795	+{
	796	+ struct bnxt_qplib_cmdq_ctx *cmdq;
	797	+ struct bnxt_qplib_creq_ctx *creq;
	798	+ struct bnxt_qplib_cmdq_mbox *mbox;
	799	+ struct cmdq_init init = {0};
	800	+
	801	+ cmdq = &rcfw->cmdq;
	802	+ creq = &rcfw->creq;
	803	+ mbox = &cmdq->cmdq_mbox;
	804	+
	805	+ init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]);
	806	+ init.cmdq_size_cmdq_lvl =
	807	+ cpu_to_le16(((rcfw->cmdq_depth <<
	808	+ CMDQ_INIT_CMDQ_SIZE_SFT) &
	809	+ CMDQ_INIT_CMDQ_SIZE_MASK) \|
	810	+ ((cmdq->hwq.level <<
	811	+ CMDQ_INIT_CMDQ_LVL_SFT) &
	812	+ CMDQ_INIT_CMDQ_LVL_MASK));
	813	+ init.creq_ring_id = cpu_to_le16(creq->ring_id);
	814	+ /* Write to the Bono mailbox register */
	815	+ __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4);
	816	+}
	817	+
	818	+int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
660	819	int msix_vector,
661	820	int cp_bar_reg_off, int virt_fn,
662		- int (aeq_handler)(struct bnxt_qplib_rcfw ,
663		- void , void ))
	821	+ aeq_handler_t aeq_handler)
664	822	{
665		- resource_size_t res_base;
666		- struct cmdq_init init;
667		- u16 bmap_size;
	823	+ struct bnxt_qplib_cmdq_ctx *cmdq;
	824	+ struct bnxt_qplib_creq_ctx *creq;
668	825	int rc;
669	826
670		- /* General */
671		- rcfw->seq_num = 0;
672		- set_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags);
673		- bmap_size = BITS_TO_LONGS(RCFW_MAX_OUTSTANDING_CMD *
674		- sizeof(unsigned long));
675		- rcfw->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL);
676		- if (!rcfw->cmdq_bitmap)
677		- return -ENOMEM;
678		- rcfw->bmap_size = bmap_size;
	827	+ cmdq = &rcfw->cmdq;
	828	+ creq = &rcfw->creq;
679	829
680		- /* CMDQ */
681		- rcfw->cmdq_bar_reg = RCFW_COMM_PCI_BAR_REGION;
682		- res_base = pci_resource_start(pdev, rcfw->cmdq_bar_reg);
683		- if (!res_base)
684		- return -ENOMEM;
	830	+ /* Clear to defaults */
685	831
686		- rcfw->cmdq_bar_reg_iomem = ioremap_nocache(res_base +
687		- RCFW_COMM_BASE_OFFSET,
688		- RCFW_COMM_SIZE);
689		- if (!rcfw->cmdq_bar_reg_iomem) {
690		- dev_err(&rcfw->pdev->dev,
691		- "QPLIB: CMDQ BAR region %d mapping failed",
692		- rcfw->cmdq_bar_reg);
693		- return -ENOMEM;
694		- }
	832	+ cmdq->seq_num = 0;
	833	+ set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
	834	+ init_waitqueue_head(&cmdq->waitq);
695	835
696		- rcfw->cmdq_bar_reg_prod_off = virt_fn ? RCFW_VF_COMM_PROD_OFFSET :
697		- RCFW_PF_COMM_PROD_OFFSET;
	836	+ creq->stats.creq_qp_event_processed = 0;
	837	+ creq->stats.creq_func_event_processed = 0;
	838	+ creq->aeq_handler = aeq_handler;
698	839
699		- rcfw->cmdq_bar_reg_trig_off = RCFW_COMM_TRIG_OFFSET;
	840	+ rc = bnxt_qplib_map_cmdq_mbox(rcfw, virt_fn);
	841	+ if (rc)
	842	+ return rc;
700	843
701		- /* CREQ */
702		- rcfw->creq_bar_reg = RCFW_COMM_CONS_PCI_BAR_REGION;
703		- res_base = pci_resource_start(pdev, rcfw->creq_bar_reg);
704		- if (!res_base)
705		- dev_err(&rcfw->pdev->dev,
706		- "QPLIB: CREQ BAR region %d resc start is 0!",
707		- rcfw->creq_bar_reg);
708		- rcfw->creq_bar_reg_iomem = ioremap_nocache(res_base + cp_bar_reg_off,
709		- 4);
710		- if (!rcfw->creq_bar_reg_iomem) {
711		- dev_err(&rcfw->pdev->dev,
712		- "QPLIB: CREQ BAR region %d mapping failed",
713		- rcfw->creq_bar_reg);
714		- iounmap(rcfw->cmdq_bar_reg_iomem);
715		- rcfw->cmdq_bar_reg_iomem = NULL;
716		- return -ENOMEM;
717		- }
718		- rcfw->creq_qp_event_processed = 0;
719		- rcfw->creq_func_event_processed = 0;
720		-
721		- if (aeq_handler)
722		- rcfw->aeq_handler = aeq_handler;
723		- init_waitqueue_head(&rcfw->waitq);
	844	+ rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off);
	845	+ if (rc)
	846	+ return rc;
724	847
725	848	rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true);
726	849	if (rc) {
727	850	dev_err(&rcfw->pdev->dev,
728		- "QPLIB: Failed to request IRQ for CREQ rc = 0x%x", rc);
	851	+ "Failed to request IRQ for CREQ rc = 0x%x\n", rc);
729	852	bnxt_qplib_disable_rcfw_channel(rcfw);
730	853	return rc;
731	854	}
732	855
733		- init.cmdq_pbl = cpu_to_le64(rcfw->cmdq.pbl[PBL_LVL_0].pg_map_arr[0]);
734		- init.cmdq_size_cmdq_lvl = cpu_to_le16(
735		- ((BNXT_QPLIB_CMDQE_MAX_CNT << CMDQ_INIT_CMDQ_SIZE_SFT) &
736		- CMDQ_INIT_CMDQ_SIZE_MASK) \|
737		- ((rcfw->cmdq.level << CMDQ_INIT_CMDQ_LVL_SFT) &
738		- CMDQ_INIT_CMDQ_LVL_MASK));
739		- init.creq_ring_id = cpu_to_le16(rcfw->creq_ring_id);
	856	+ bnxt_qplib_start_rcfw(rcfw);
740	857
741		- /* Write to the Bono mailbox register */
742		- __iowrite32_copy(rcfw->cmdq_bar_reg_iomem, &init, sizeof(init) / 4);
743	858	return 0;
744	859	}
745	860
..	..	@@ -754,8 +869,8 @@
754	869	return NULL;
755	870
756	871	sbuf->size = size;
757		- sbuf->sb = dma_zalloc_coherent(&rcfw->pdev->dev, sbuf->size,
758		- &sbuf->dma_addr, GFP_ATOMIC);
	872	+ sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size,
	873	+ &sbuf->dma_addr, GFP_ATOMIC);
759	874	if (!sbuf->sb)
760	875	goto bail;
761	876