forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920
kernel/drivers/iio/adc/stx104.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * IIO driver for the Apex Embedded Systems STX104
34 * Copyright (C) 2016 William Breathitt Gray
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License, version 2, as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but
10
- * WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12
- * General Public License for more details.
135 */
146 #include <linux/bitops.h>
157 #include <linux/device.h>
....@@ -23,7 +15,9 @@
2315 #include <linux/kernel.h>
2416 #include <linux/module.h>
2517 #include <linux/moduleparam.h>
18
+#include <linux/mutex.h>
2619 #include <linux/spinlock.h>
20
+#include <linux/types.h>
2721
2822 #define STX104_OUT_CHAN(chan) { \
2923 .type = IIO_VOLTAGE, \
....@@ -53,13 +47,37 @@
5347 MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
5448
5549 /**
50
+ * struct stx104_reg - device register structure
51
+ * @ssr_ad: Software Strobe Register and ADC Data
52
+ * @achan: ADC Channel
53
+ * @dio: Digital I/O
54
+ * @dac: DAC Channels
55
+ * @cir_asr: Clear Interrupts and ADC Status
56
+ * @acr: ADC Control
57
+ * @pccr_fsh: Pacer Clock Control and FIFO Status MSB
58
+ * @acfg: ADC Configuration
59
+ */
60
+struct stx104_reg {
61
+ u16 ssr_ad;
62
+ u8 achan;
63
+ u8 dio;
64
+ u16 dac[2];
65
+ u8 cir_asr;
66
+ u8 acr;
67
+ u8 pccr_fsh;
68
+ u8 acfg;
69
+};
70
+
71
+/**
5672 * struct stx104_iio - IIO device private data structure
73
+ * @lock: synchronization lock to prevent I/O race conditions
5774 * @chan_out_states: channels' output states
58
- * @base: base port address of the IIO device
75
+ * @reg: I/O address offset for the device registers
5976 */
6077 struct stx104_iio {
78
+ struct mutex lock;
6179 unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
62
- unsigned int base;
80
+ struct stx104_reg __iomem *reg;
6381 };
6482
6583 /**
....@@ -72,7 +90,7 @@
7290 struct stx104_gpio {
7391 struct gpio_chip chip;
7492 spinlock_t lock;
75
- unsigned int base;
93
+ u8 __iomem *base;
7694 unsigned int out_state;
7795 };
7896
....@@ -80,6 +98,7 @@
8098 struct iio_chan_spec const *chan, int *val, int *val2, long mask)
8199 {
82100 struct stx104_iio *const priv = iio_priv(indio_dev);
101
+ struct stx104_reg __iomem *const reg = priv->reg;
83102 unsigned int adc_config;
84103 int adbu;
85104 int gain;
....@@ -87,7 +106,7 @@
87106 switch (mask) {
88107 case IIO_CHAN_INFO_HARDWAREGAIN:
89108 /* get gain configuration */
90
- adc_config = inb(priv->base + 11);
109
+ adc_config = ioread8(&reg->acfg);
91110 gain = adc_config & 0x3;
92111
93112 *val = 1 << gain;
....@@ -98,25 +117,31 @@
98117 return IIO_VAL_INT;
99118 }
100119
120
+ mutex_lock(&priv->lock);
121
+
101122 /* select ADC channel */
102
- outb(chan->channel | (chan->channel << 4), priv->base + 2);
123
+ iowrite8(chan->channel | (chan->channel << 4), &reg->achan);
103124
104
- /* trigger ADC sample capture and wait for completion */
105
- outb(0, priv->base);
106
- while (inb(priv->base + 8) & BIT(7));
125
+ /* trigger ADC sample capture by writing to the 8-bit
126
+ * Software Strobe Register and wait for completion
127
+ */
128
+ iowrite8(0, &reg->ssr_ad);
129
+ while (ioread8(&reg->cir_asr) & BIT(7));
107130
108
- *val = inw(priv->base);
131
+ *val = ioread16(&reg->ssr_ad);
132
+
133
+ mutex_unlock(&priv->lock);
109134 return IIO_VAL_INT;
110135 case IIO_CHAN_INFO_OFFSET:
111136 /* get ADC bipolar/unipolar configuration */
112
- adc_config = inb(priv->base + 11);
137
+ adc_config = ioread8(&reg->acfg);
113138 adbu = !(adc_config & BIT(2));
114139
115140 *val = -32768 * adbu;
116141 return IIO_VAL_INT;
117142 case IIO_CHAN_INFO_SCALE:
118143 /* get ADC bipolar/unipolar and gain configuration */
119
- adc_config = inb(priv->base + 11);
144
+ adc_config = ioread8(&reg->acfg);
120145 adbu = !(adc_config & BIT(2));
121146 gain = adc_config & 0x3;
122147
....@@ -138,16 +163,16 @@
138163 /* Only four gain states (x1, x2, x4, x8) */
139164 switch (val) {
140165 case 1:
141
- outb(0, priv->base + 11);
166
+ iowrite8(0, &priv->reg->acfg);
142167 break;
143168 case 2:
144
- outb(1, priv->base + 11);
169
+ iowrite8(1, &priv->reg->acfg);
145170 break;
146171 case 4:
147
- outb(2, priv->base + 11);
172
+ iowrite8(2, &priv->reg->acfg);
148173 break;
149174 case 8:
150
- outb(3, priv->base + 11);
175
+ iowrite8(3, &priv->reg->acfg);
151176 break;
152177 default:
153178 return -EINVAL;
....@@ -160,9 +185,12 @@
160185 if ((unsigned int)val > 65535)
161186 return -EINVAL;
162187
163
- priv->chan_out_states[chan->channel] = val;
164
- outw(val, priv->base + 4 + 2 * chan->channel);
188
+ mutex_lock(&priv->lock);
165189
190
+ priv->chan_out_states[chan->channel] = val;
191
+ iowrite16(val, &priv->reg->dac[chan->channel]);
192
+
193
+ mutex_unlock(&priv->lock);
166194 return 0;
167195 }
168196 return -EINVAL;
....@@ -230,7 +258,7 @@
230258 if (offset >= 4)
231259 return -EINVAL;
232260
233
- return !!(inb(stx104gpio->base) & BIT(offset));
261
+ return !!(ioread8(stx104gpio->base) & BIT(offset));
234262 }
235263
236264 static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
....@@ -238,7 +266,7 @@
238266 {
239267 struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
240268
241
- *bits = inb(stx104gpio->base);
269
+ *bits = ioread8(stx104gpio->base);
242270
243271 return 0;
244272 }
....@@ -260,7 +288,7 @@
260288 else
261289 stx104gpio->out_state &= ~mask;
262290
263
- outb(stx104gpio->out_state, stx104gpio->base);
291
+ iowrite8(stx104gpio->out_state, stx104gpio->base);
264292
265293 spin_unlock_irqrestore(&stx104gpio->lock, flags);
266294 }
....@@ -287,7 +315,7 @@
287315
288316 stx104gpio->out_state &= ~*mask;
289317 stx104gpio->out_state |= *mask & *bits;
290
- outb(stx104gpio->out_state, stx104gpio->base);
318
+ iowrite8(stx104gpio->out_state, stx104gpio->base);
291319
292320 spin_unlock_irqrestore(&stx104gpio->lock, flags);
293321 }
....@@ -314,11 +342,16 @@
314342 return -EBUSY;
315343 }
316344
345
+ priv = iio_priv(indio_dev);
346
+ priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT);
347
+ if (!priv->reg)
348
+ return -ENOMEM;
349
+
317350 indio_dev->info = &stx104_info;
318351 indio_dev->modes = INDIO_DIRECT_MODE;
319352
320353 /* determine if differential inputs */
321
- if (inb(base[id] + 8) & BIT(5)) {
354
+ if (ioread8(&priv->reg->cir_asr) & BIT(5)) {
322355 indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
323356 indio_dev->channels = stx104_channels_diff;
324357 } else {
....@@ -327,20 +360,18 @@
327360 }
328361
329362 indio_dev->name = dev_name(dev);
330
- indio_dev->dev.parent = dev;
331363
332
- priv = iio_priv(indio_dev);
333
- priv->base = base[id];
364
+ mutex_init(&priv->lock);
334365
335366 /* configure device for software trigger operation */
336
- outb(0, base[id] + 9);
367
+ iowrite8(0, &priv->reg->acr);
337368
338369 /* initialize gain setting to x1 */
339
- outb(0, base[id] + 11);
370
+ iowrite8(0, &priv->reg->acfg);
340371
341372 /* initialize DAC output to 0V */
342
- outw(0, base[id] + 4);
343
- outw(0, base[id] + 6);
373
+ iowrite16(0, &priv->reg->dac[0]);
374
+ iowrite16(0, &priv->reg->dac[1]);
344375
345376 stx104gpio->chip.label = dev_name(dev);
346377 stx104gpio->chip.parent = dev;
....@@ -355,7 +386,7 @@
355386 stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
356387 stx104gpio->chip.set = stx104_gpio_set;
357388 stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
358
- stx104gpio->base = base[id] + 3;
389
+ stx104gpio->base = &priv->reg->dio;
359390 stx104gpio->out_state = 0x0;
360391
361392 spin_lock_init(&stx104gpio->lock);