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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * IIO driver for the Apex Embedded Systems STX104 |
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3 | 4 | * Copyright (C) 2016 William Breathitt Gray |
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4 | | - * |
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5 | | - * This program is free software; you can redistribute it and/or modify |
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6 | | - * it under the terms of the GNU General Public License, version 2, as |
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7 | | - * published by the Free Software Foundation. |
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8 | | - * |
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9 | | - * This program is distributed in the hope that it will be useful, but |
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10 | | - * WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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12 | | - * General Public License for more details. |
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13 | 5 | */ |
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14 | 6 | #include <linux/bitops.h> |
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15 | 7 | #include <linux/device.h> |
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.. | .. |
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23 | 15 | #include <linux/kernel.h> |
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24 | 16 | #include <linux/module.h> |
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25 | 17 | #include <linux/moduleparam.h> |
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| 18 | +#include <linux/mutex.h> |
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26 | 19 | #include <linux/spinlock.h> |
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| 20 | +#include <linux/types.h> |
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27 | 21 | |
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28 | 22 | #define STX104_OUT_CHAN(chan) { \ |
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29 | 23 | .type = IIO_VOLTAGE, \ |
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.. | .. |
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53 | 47 | MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); |
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54 | 48 | |
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55 | 49 | /** |
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| 50 | + * struct stx104_reg - device register structure |
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| 51 | + * @ssr_ad: Software Strobe Register and ADC Data |
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| 52 | + * @achan: ADC Channel |
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| 53 | + * @dio: Digital I/O |
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| 54 | + * @dac: DAC Channels |
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| 55 | + * @cir_asr: Clear Interrupts and ADC Status |
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| 56 | + * @acr: ADC Control |
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| 57 | + * @pccr_fsh: Pacer Clock Control and FIFO Status MSB |
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| 58 | + * @acfg: ADC Configuration |
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| 59 | + */ |
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| 60 | +struct stx104_reg { |
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| 61 | + u16 ssr_ad; |
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| 62 | + u8 achan; |
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| 63 | + u8 dio; |
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| 64 | + u16 dac[2]; |
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| 65 | + u8 cir_asr; |
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| 66 | + u8 acr; |
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| 67 | + u8 pccr_fsh; |
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| 68 | + u8 acfg; |
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| 69 | +}; |
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| 70 | + |
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| 71 | +/** |
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56 | 72 | * struct stx104_iio - IIO device private data structure |
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| 73 | + * @lock: synchronization lock to prevent I/O race conditions |
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57 | 74 | * @chan_out_states: channels' output states |
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58 | | - * @base: base port address of the IIO device |
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| 75 | + * @reg: I/O address offset for the device registers |
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59 | 76 | */ |
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60 | 77 | struct stx104_iio { |
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| 78 | + struct mutex lock; |
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61 | 79 | unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; |
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62 | | - unsigned int base; |
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| 80 | + struct stx104_reg __iomem *reg; |
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63 | 81 | }; |
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64 | 82 | |
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65 | 83 | /** |
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.. | .. |
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72 | 90 | struct stx104_gpio { |
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73 | 91 | struct gpio_chip chip; |
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74 | 92 | spinlock_t lock; |
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75 | | - unsigned int base; |
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| 93 | + u8 __iomem *base; |
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76 | 94 | unsigned int out_state; |
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77 | 95 | }; |
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78 | 96 | |
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.. | .. |
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80 | 98 | struct iio_chan_spec const *chan, int *val, int *val2, long mask) |
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81 | 99 | { |
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82 | 100 | struct stx104_iio *const priv = iio_priv(indio_dev); |
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| 101 | + struct stx104_reg __iomem *const reg = priv->reg; |
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83 | 102 | unsigned int adc_config; |
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84 | 103 | int adbu; |
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85 | 104 | int gain; |
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.. | .. |
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87 | 106 | switch (mask) { |
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88 | 107 | case IIO_CHAN_INFO_HARDWAREGAIN: |
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89 | 108 | /* get gain configuration */ |
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90 | | - adc_config = inb(priv->base + 11); |
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| 109 | + adc_config = ioread8(®->acfg); |
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91 | 110 | gain = adc_config & 0x3; |
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92 | 111 | |
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93 | 112 | *val = 1 << gain; |
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.. | .. |
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98 | 117 | return IIO_VAL_INT; |
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99 | 118 | } |
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100 | 119 | |
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| 120 | + mutex_lock(&priv->lock); |
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| 121 | + |
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101 | 122 | /* select ADC channel */ |
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102 | | - outb(chan->channel | (chan->channel << 4), priv->base + 2); |
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| 123 | + iowrite8(chan->channel | (chan->channel << 4), ®->achan); |
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103 | 124 | |
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104 | | - /* trigger ADC sample capture and wait for completion */ |
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105 | | - outb(0, priv->base); |
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106 | | - while (inb(priv->base + 8) & BIT(7)); |
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| 125 | + /* trigger ADC sample capture by writing to the 8-bit |
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| 126 | + * Software Strobe Register and wait for completion |
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| 127 | + */ |
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| 128 | + iowrite8(0, ®->ssr_ad); |
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| 129 | + while (ioread8(®->cir_asr) & BIT(7)); |
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107 | 130 | |
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108 | | - *val = inw(priv->base); |
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| 131 | + *val = ioread16(®->ssr_ad); |
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| 132 | + |
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| 133 | + mutex_unlock(&priv->lock); |
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109 | 134 | return IIO_VAL_INT; |
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110 | 135 | case IIO_CHAN_INFO_OFFSET: |
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111 | 136 | /* get ADC bipolar/unipolar configuration */ |
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112 | | - adc_config = inb(priv->base + 11); |
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| 137 | + adc_config = ioread8(®->acfg); |
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113 | 138 | adbu = !(adc_config & BIT(2)); |
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114 | 139 | |
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115 | 140 | *val = -32768 * adbu; |
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116 | 141 | return IIO_VAL_INT; |
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117 | 142 | case IIO_CHAN_INFO_SCALE: |
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118 | 143 | /* get ADC bipolar/unipolar and gain configuration */ |
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119 | | - adc_config = inb(priv->base + 11); |
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| 144 | + adc_config = ioread8(®->acfg); |
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120 | 145 | adbu = !(adc_config & BIT(2)); |
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121 | 146 | gain = adc_config & 0x3; |
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122 | 147 | |
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.. | .. |
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138 | 163 | /* Only four gain states (x1, x2, x4, x8) */ |
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139 | 164 | switch (val) { |
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140 | 165 | case 1: |
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141 | | - outb(0, priv->base + 11); |
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| 166 | + iowrite8(0, &priv->reg->acfg); |
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142 | 167 | break; |
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143 | 168 | case 2: |
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144 | | - outb(1, priv->base + 11); |
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| 169 | + iowrite8(1, &priv->reg->acfg); |
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145 | 170 | break; |
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146 | 171 | case 4: |
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147 | | - outb(2, priv->base + 11); |
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| 172 | + iowrite8(2, &priv->reg->acfg); |
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148 | 173 | break; |
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149 | 174 | case 8: |
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150 | | - outb(3, priv->base + 11); |
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| 175 | + iowrite8(3, &priv->reg->acfg); |
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151 | 176 | break; |
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152 | 177 | default: |
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153 | 178 | return -EINVAL; |
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.. | .. |
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160 | 185 | if ((unsigned int)val > 65535) |
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161 | 186 | return -EINVAL; |
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162 | 187 | |
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163 | | - priv->chan_out_states[chan->channel] = val; |
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164 | | - outw(val, priv->base + 4 + 2 * chan->channel); |
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| 188 | + mutex_lock(&priv->lock); |
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165 | 189 | |
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| 190 | + priv->chan_out_states[chan->channel] = val; |
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| 191 | + iowrite16(val, &priv->reg->dac[chan->channel]); |
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| 192 | + |
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| 193 | + mutex_unlock(&priv->lock); |
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166 | 194 | return 0; |
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167 | 195 | } |
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168 | 196 | return -EINVAL; |
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.. | .. |
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230 | 258 | if (offset >= 4) |
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231 | 259 | return -EINVAL; |
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232 | 260 | |
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233 | | - return !!(inb(stx104gpio->base) & BIT(offset)); |
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| 261 | + return !!(ioread8(stx104gpio->base) & BIT(offset)); |
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234 | 262 | } |
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235 | 263 | |
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236 | 264 | static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
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.. | .. |
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238 | 266 | { |
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239 | 267 | struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip); |
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240 | 268 | |
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241 | | - *bits = inb(stx104gpio->base); |
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| 269 | + *bits = ioread8(stx104gpio->base); |
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242 | 270 | |
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243 | 271 | return 0; |
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244 | 272 | } |
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.. | .. |
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260 | 288 | else |
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261 | 289 | stx104gpio->out_state &= ~mask; |
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262 | 290 | |
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263 | | - outb(stx104gpio->out_state, stx104gpio->base); |
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| 291 | + iowrite8(stx104gpio->out_state, stx104gpio->base); |
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264 | 292 | |
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265 | 293 | spin_unlock_irqrestore(&stx104gpio->lock, flags); |
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266 | 294 | } |
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.. | .. |
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287 | 315 | |
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288 | 316 | stx104gpio->out_state &= ~*mask; |
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289 | 317 | stx104gpio->out_state |= *mask & *bits; |
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290 | | - outb(stx104gpio->out_state, stx104gpio->base); |
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| 318 | + iowrite8(stx104gpio->out_state, stx104gpio->base); |
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291 | 319 | |
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292 | 320 | spin_unlock_irqrestore(&stx104gpio->lock, flags); |
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293 | 321 | } |
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.. | .. |
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314 | 342 | return -EBUSY; |
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315 | 343 | } |
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316 | 344 | |
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| 345 | + priv = iio_priv(indio_dev); |
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| 346 | + priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT); |
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| 347 | + if (!priv->reg) |
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| 348 | + return -ENOMEM; |
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| 349 | + |
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317 | 350 | indio_dev->info = &stx104_info; |
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318 | 351 | indio_dev->modes = INDIO_DIRECT_MODE; |
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319 | 352 | |
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320 | 353 | /* determine if differential inputs */ |
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321 | | - if (inb(base[id] + 8) & BIT(5)) { |
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| 354 | + if (ioread8(&priv->reg->cir_asr) & BIT(5)) { |
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322 | 355 | indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); |
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323 | 356 | indio_dev->channels = stx104_channels_diff; |
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324 | 357 | } else { |
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.. | .. |
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327 | 360 | } |
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328 | 361 | |
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329 | 362 | indio_dev->name = dev_name(dev); |
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330 | | - indio_dev->dev.parent = dev; |
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331 | 363 | |
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332 | | - priv = iio_priv(indio_dev); |
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333 | | - priv->base = base[id]; |
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| 364 | + mutex_init(&priv->lock); |
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334 | 365 | |
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335 | 366 | /* configure device for software trigger operation */ |
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336 | | - outb(0, base[id] + 9); |
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| 367 | + iowrite8(0, &priv->reg->acr); |
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337 | 368 | |
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338 | 369 | /* initialize gain setting to x1 */ |
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339 | | - outb(0, base[id] + 11); |
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| 370 | + iowrite8(0, &priv->reg->acfg); |
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340 | 371 | |
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341 | 372 | /* initialize DAC output to 0V */ |
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342 | | - outw(0, base[id] + 4); |
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343 | | - outw(0, base[id] + 6); |
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| 373 | + iowrite16(0, &priv->reg->dac[0]); |
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| 374 | + iowrite16(0, &priv->reg->dac[1]); |
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344 | 375 | |
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345 | 376 | stx104gpio->chip.label = dev_name(dev); |
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346 | 377 | stx104gpio->chip.parent = dev; |
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.. | .. |
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355 | 386 | stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; |
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356 | 387 | stx104gpio->chip.set = stx104_gpio_set; |
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357 | 388 | stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; |
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358 | | - stx104gpio->base = base[id] + 3; |
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| 389 | + stx104gpio->base = &priv->reg->dio; |
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359 | 390 | stx104gpio->out_state = 0x0; |
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360 | 391 | |
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361 | 392 | spin_lock_init(&stx104gpio->lock); |
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