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2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920 
 kernel/drivers/i2c/busses/i2c-bcm2835.c
....@@ -1,23 +1,18 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * BCM2835 master mode driver
3
- *
4
- * This software is licensed under the terms of the GNU General Public
5
- * License version 2, as published by the Free Software Foundation, and
6
- * may be copied, distributed, and modified under those terms.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
146 #include <linux/clk.h>
7
+#include <linux/clkdev.h>
8
+#include <linux/clk-provider.h>
159 #include <linux/completion.h>
1610 #include <linux/err.h>
1711 #include <linux/i2c.h>
1812 #include <linux/interrupt.h>
1913 #include <linux/io.h>
2014 #include <linux/module.h>
15
+#include <linux/of_device.h>
2116 #include <linux/platform_device.h>
2217 #include <linux/slab.h>
2318 
....@@ -28,6 +23,11 @@
2823 #define BCM2835_I2C_FIFO	0x10
2924 #define BCM2835_I2C_DIV		0x14
3025 #define BCM2835_I2C_DEL		0x18
26
+/*
27
+ * 16-bit field for the number of SCL cycles to wait after rising SCL
28
+ * before deciding the slave is not responding. 0 disables the
29
+ * timeout detection.
30
+ */
3131 #define BCM2835_I2C_CLKT	0x1c
3232 
3333 #define BCM2835_I2C_C_READ	BIT(0)
....@@ -59,12 +59,11 @@
5959 struct bcm2835_i2c_dev {
6060 	struct device *dev;
6161 	void __iomem *regs;
62
-	struct clk *clk;
6362 	int irq;
64
-	u32 bus_clk_rate;
6563 	struct i2c_adapter adapter;
6664 	struct completion completion;
6765 	struct i2c_msg *curr_msg;
66
+	struct clk *bus_clk;
6867 	int num_msgs;
6968 	u32 msg_err;
7069 	u8 *msg_buf;
....@@ -82,12 +81,17 @@
8281 	return readl(i2c_dev->regs + reg);
8382 }
8483 
85
-static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
86
-{
87
-	u32 divider, redl, fedl;
84
+#define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw)
85
+struct clk_bcm2835_i2c {
86
+	struct clk_hw hw;
87
+	struct bcm2835_i2c_dev *i2c_dev;
88
+};
8889 
89
-	divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
90
-			       i2c_dev->bus_clk_rate);
90
+static int clk_bcm2835_i2c_calc_divider(unsigned long rate,
91
+				unsigned long parent_rate)
92
+{
93
+	u32 divider = DIV_ROUND_UP(parent_rate, rate);
94
+
9195 	/*
9296 	 * Per the datasheet, the register is always interpreted as an even
9397 	 * number, by rounding down. In other words, the LSB is ignored. So,
....@@ -96,12 +100,23 @@
96100 	if (divider & 1)
97101 		divider++;
98102 	if ((divider < BCM2835_I2C_CDIV_MIN) ||
99
-	    (divider > BCM2835_I2C_CDIV_MAX)) {
100
-		dev_err_ratelimited(i2c_dev->dev, "Invalid clock-frequency\n");
103
+	    (divider > BCM2835_I2C_CDIV_MAX))
101104 		return -EINVAL;
102
-	}
103105 
104
-	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
106
+	return divider;
107
+}
108
+
109
+static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate,
110
+				unsigned long parent_rate)
111
+{
112
+	struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
113
+	u32 redl, fedl;
114
+	u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
115
+
116
+	if (divider == -EINVAL)
117
+		return -EINVAL;
118
+
119
+	bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
105120 
106121 	/*
107122 	 * Number of core clocks to wait after falling edge before
....@@ -116,10 +131,63 @@
116131 	 */
117132 	redl = max(divider / 4, 1u);
118133 
119
-	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
134
+	bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,
120135 			   (fedl << BCM2835_I2C_FEDL_SHIFT) |
121136 			   (redl << BCM2835_I2C_REDL_SHIFT));
122137 	return 0;
138
+}
139
+
140
+static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate,
141
+				unsigned long *parent_rate)
142
+{
143
+	u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate);
144
+
145
+	return DIV_ROUND_UP(*parent_rate, divider);
146
+}
147
+
148
+static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw,
149
+						unsigned long parent_rate)
150
+{
151
+	struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
152
+	u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
153
+
154
+	return DIV_ROUND_UP(parent_rate, divider);
155
+}
156
+
157
+static const struct clk_ops clk_bcm2835_i2c_ops = {
158
+	.set_rate = clk_bcm2835_i2c_set_rate,
159
+	.round_rate = clk_bcm2835_i2c_round_rate,
160
+	.recalc_rate = clk_bcm2835_i2c_recalc_rate,
161
+};
162
+
163
+static struct clk *bcm2835_i2c_register_div(struct device *dev,
164
+					struct clk *mclk,
165
+					struct bcm2835_i2c_dev *i2c_dev)
166
+{
167
+	struct clk_init_data init;
168
+	struct clk_bcm2835_i2c *priv;
169
+	char name[32];
170
+	const char *mclk_name;
171
+
172
+	snprintf(name, sizeof(name), "%s_div", dev_name(dev));
173
+
174
+	mclk_name = __clk_get_name(mclk);
175
+
176
+	init.ops = &clk_bcm2835_i2c_ops;
177
+	init.name = name;
178
+	init.parent_names = (const char* []) { mclk_name };
179
+	init.num_parents = 1;
180
+	init.flags = 0;
181
+
182
+	priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL);
183
+	if (priv == NULL)
184
+		return ERR_PTR(-ENOMEM);
185
+
186
+	priv->hw.init = &init;
187
+	priv->i2c_dev = i2c_dev;
188
+
189
+	clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev));
190
+	return devm_clk_register(dev, &priv->hw);
123191 }
124192 
125193 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
....@@ -279,7 +347,7 @@
279347 {
280348 	struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
281349 	unsigned long time_left;
282
-	int i, ret;
350
+	int i;
283351 
284352 	for (i = 0; i < (num - 1); i++)
285353 		if (msgs[i].flags & I2C_M_RD) {
....@@ -287,10 +355,6 @@
287355 				      "only one read message supported, has to be last\n");
288356 			return -EOPNOTSUPP;
289357 		}
290
-
291
-	ret = bcm2835_i2c_set_divider(i2c_dev);
292
-	if (ret)
293
-		return ret;
294358 
295359 	i2c_dev->curr_msg = msgs;
296360 	i2c_dev->num_msgs = num;
....@@ -332,8 +396,8 @@
332396 };
333397 
334398 /*
335
- * This HW was reported to have problems with clock stretching:
336
- * http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
399
+ * The BCM2835 was reported to have problems with clock stretching:
400
+ * https://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
337401  * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
338402  */
339403 static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
....@@ -346,6 +410,8 @@
346410 	struct resource *mem, *irq;
347411 	int ret;
348412 	struct i2c_adapter *adap;
413
+	struct clk *mclk;
414
+	u32 bus_clk_rate;
349415 
350416 	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
351417 	if (!i2c_dev)
....@@ -359,19 +425,36 @@
359425 	if (IS_ERR(i2c_dev->regs))
360426 		return PTR_ERR(i2c_dev->regs);
361427 
362
-	i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
363
-	if (IS_ERR(i2c_dev->clk)) {
364
-		if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER)
365
-			dev_err(&pdev->dev, "Could not get clock\n");
366
-		return PTR_ERR(i2c_dev->clk);
428
+	mclk = devm_clk_get(&pdev->dev, NULL);
429
+	if (IS_ERR(mclk))
430
+		return dev_err_probe(&pdev->dev, PTR_ERR(mclk),
431
+				     "Could not get clock\n");
432
+
433
+	i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
434
+
435
+	if (IS_ERR(i2c_dev->bus_clk)) {
436
+		dev_err(&pdev->dev, "Could not register clock\n");
437
+		return PTR_ERR(i2c_dev->bus_clk);
367438 	}
368439 
369440 	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
370
-				   &i2c_dev->bus_clk_rate);
441
+				   &bus_clk_rate);
371442 	if (ret < 0) {
372443 		dev_warn(&pdev->dev,
373444 			 "Could not read clock-frequency property\n");
374
-		i2c_dev->bus_clk_rate = 100000;
445
+		bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
446
+	}
447
+
448
+	ret = clk_set_rate_exclusive(i2c_dev->bus_clk, bus_clk_rate);
449
+	if (ret < 0) {
450
+		dev_err(&pdev->dev, "Could not set clock frequency\n");
451
+		return ret;
452
+	}
453
+
454
+	ret = clk_prepare_enable(i2c_dev->bus_clk);
455
+	if (ret) {
456
+		dev_err(&pdev->dev, "Couldn't prepare clock");
457
+		return ret;
375458 	}
376459 
377460 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
....@@ -392,12 +475,19 @@
392475 	i2c_set_adapdata(adap, i2c_dev);
393476 	adap->owner = THIS_MODULE;
394477 	adap->class = I2C_CLASS_DEPRECATED;
395
-	strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name));
478
+	snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)",
479
+		 of_node_full_name(pdev->dev.of_node));
396480 	adap->algo = &bcm2835_i2c_algo;
397481 	adap->dev.parent = &pdev->dev;
398482 	adap->dev.of_node = pdev->dev.of_node;
399
-	adap->quirks = &bcm2835_i2c_quirks;
483
+	adap->quirks = of_device_get_match_data(&pdev->dev);
400484 
485
+	/*
486
+	 * Disable the hardware clock stretching timeout. SMBUS
487
+	 * specifies a limit for how long the device can stretch the
488
+	 * clock, but core I2C doesn't.
489
+	 */
490
+	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_CLKT, 0);
401491 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
402492 
403493 	ret = i2c_add_adapter(adap);
....@@ -411,6 +501,9 @@
411501 {
412502 	struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
413503 
504
+	clk_rate_exclusive_put(i2c_dev->bus_clk);
505
+	clk_disable_unprepare(i2c_dev->bus_clk);
506
+
414507 	free_irq(i2c_dev->irq, i2c_dev);
415508 	i2c_del_adapter(&i2c_dev->adapter);
416509 
....@@ -418,7 +511,8 @@
418511 }
419512 
420513 static const struct of_device_id bcm2835_i2c_of_match[] = {
421
-	{ .compatible = "brcm,bcm2835-i2c" },
514
+	{ .compatible = "brcm,bcm2711-i2c" },
515
+	{ .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks },
422516 	{},
423517 };
424518 MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);