~hc/RK356X_SDK_RELEASE.git

..	..	@@ -4,17 +4,22 @@
4	4	* Author: Andy Yan <andy.yan@rock-chips.com>
5	5	*/
6	6	#include <drm/drm.h>
7		-#include <drm/drmP.h>
8	7	#include <drm/drm_atomic.h>
	8	+#include <drm/drm_atomic_uapi.h>
9	9	#include <drm/drm_crtc.h>
10	10	#include <drm/drm_crtc_helper.h>
	11	+#include <drm/drm_debugfs.h>
11	12	#include <drm/drm_flip_work.h>
	13	+#include <drm/drm_fourcc.h>
	14	+#include <drm/drm_gem_framebuffer_helper.h>
12	15	#include <drm/drm_plane_helper.h>
	16	+#include <drm/drm_probe_helper.h>
	17	+#include <drm/drm_self_refresh_helper.h>
	18	+
13	19	#include <drm/drm_writeback.h>
14	20	#ifdef CONFIG_DRM_ANALOGIX_DP
15	21	#include <drm/bridge/analogix_dp.h>
16	22	#endif
17		-#include <dt-bindings/soc/rockchip-system-status.h>
18	23
19	24	#include <linux/debugfs.h>
20	25	#include <linux/fixp-arith.h>
..	..	@@ -23,6 +28,8 @@
23	28	#include <linux/module.h>
24	29	#include <linux/platform_device.h>
25	30	#include <linux/clk.h>
	31	+#include <linux/clk-provider.h>
	32	+#include <linux/clk/clk-conf.h>
26	33	#include <linux/iopoll.h>
27	34	#include <linux/of.h>
28	35	#include <linux/of_device.h>
..	..	@@ -30,23 +37,28 @@
30	37	#include <linux/pm_runtime.h>
31	38	#include <linux/component.h>
32	39	#include <linux/regmap.h>
	40	+#include <linux/reset.h>
33	41	#include <linux/mfd/syscon.h>
34	42	#include <linux/delay.h>
35	43	#include <linux/swab.h>
36	44	#include <linux/sort.h>
37	45	#include <linux/rockchip/cpu.h>
	46	+#include <linux/workqueue.h>
	47	+#include <linux/types.h>
	48	+#include <soc/rockchip/rockchip_csu.h>
38	49	#include <soc/rockchip/rockchip_dmc.h>
39	50	#include <soc/rockchip/rockchip-system-status.h>
40	51	#include <uapi/linux/videodev2.h>
41	52
	53	+#include "../drm_crtc_internal.h"
42	54	#include "../drm_internal.h"
43	55
44	56	#include "rockchip_drm_drv.h"
45	57	#include "rockchip_drm_gem.h"
46	58	#include "rockchip_drm_fb.h"
47		-#include "rockchip_drm_psr.h"
48	59	#include "rockchip_drm_vop.h"
49	60	#include "rockchip_vop_reg.h"
	61	+#include "rockchip_post_csc.h"
50	62
51	63	#define _REG_SET(vop2, name, off, reg, mask, v, relaxed) \
52	64	vop2_mask_write(vop2, off + reg.offset, mask, reg.shift, v, reg.write_mask, relaxed)
..	..	@@ -78,6 +90,8 @@
78	90
79	91	#define VOP_CTRL_SET(x, name, v) \
80	92	REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
	93	+
	94	+#define VOP_CTRL_GET(x, name) vop2_read_reg(x, 0, &(x)->data->ctrl->name)
81	95
82	96	#define VOP_INTR_GET(vop2, name) \
83	97	vop2_read_reg(vop2, 0, &vop2->data->ctrl->name)
..	..	@@ -112,27 +126,32 @@
112	126	#define VOP_WIN_GET(vop2, win, name) \
113	127	vop2_read_reg(vop2, win->offset, &VOP_WIN_NAME(win, name))
114	128
	129	+#define VOP_WIN_GET_REG_BAK(vop2, win, name) \
	130	+ vop2_read_reg_bak(vop2, win->offset, &VOP_WIN_NAME(win, name))
	131	+
115	132	#define VOP_WIN_NAME(win, name) \
116	133	(vop2_get_win_regs(win, &win->regs->name)->name)
117	134
118	135	#define VOP_WIN_TO_INDEX(vop2_win) \
119	136	((vop2_win) - (vop2_win)->vop2->win)
120	137
121		-#define VOP_GRF_SET(vop2, reg, v) \
	138	+#define VOP_GRF_SET(vop2, grf, reg, v) \
122	139	do { \
123		- if (vop2->data->grf_ctrl) { \
124		- vop2_grf_writel(vop2, vop2->data->grf_ctrl->reg, v); \
	140	+ if (vop2->data->grf) { \
	141	+ vop2_grf_writel(vop2->grf, vop2->data->grf->reg, v); \
125	142	} \
126	143	} while (0)
127	144
128		-#define to_vop2_video_port(c) container_of(c, struct vop2_video_port, crtc)
129	145	#define to_vop2_win(x) container_of(x, struct vop2_win, base)
130	146	#define to_vop2_plane_state(x) container_of(x, struct vop2_plane_state, base)
131	147	#define to_wb_state(x) container_of(x, struct vop2_wb_connector_state, base)
132		-
133		-#ifndef drm_is_afbc
134		-#define drm_is_afbc(modifier) (((modifier) >> 56) == DRM_FORMAT_MOD_VENDOR_ARM)
135		-#endif
	148	+#define output_if_is_hdmi(x) (x & (VOP_OUTPUT_IF_HDMI0 \| VOP_OUTPUT_IF_HDMI1))
	149	+#define output_if_is_dp(x) (x & (VOP_OUTPUT_IF_DP0 \| VOP_OUTPUT_IF_DP1))
	150	+#define output_if_is_edp(x) (x & (VOP_OUTPUT_IF_eDP0 \| VOP_OUTPUT_IF_eDP1))
	151	+#define output_if_is_mipi(x) (x & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_MIPI1))
	152	+#define output_if_is_lvds(x) (x & (VOP_OUTPUT_IF_LVDS0 \| VOP_OUTPUT_IF_LVDS1))
	153	+#define output_if_is_dpi(x) (x & (VOP_OUTPUT_IF_BT656 \| VOP_OUTPUT_IF_BT1120 \| \
	154	+ VOP_OUTPUT_IF_RGB))
136	155
137	156	/*
138	157	* max two jobs a time, one is running(writing back),
..	..	@@ -141,7 +160,11 @@
141	160	#define VOP2_WB_JOB_MAX 2
142	161	#define VOP2_SYS_AXI_BUS_NUM 2
143	162
144		-#define VOP2_CLUSTER_YUV444_10 0x12
	163	+#define VOP2_MAX_VP_OUTPUT_WIDTH 4096
	164	+/* KHZ */
	165	+#define VOP2_MAX_DCLK_RATE 600000
	166	+/* KHZ */
	167	+#define VOP2_COMMON_ACLK_RATE 500000
145	168
146	169	enum vop2_data_format {
147	170	VOP2_FMT_ARGB8888 = 0,
..	..	@@ -233,6 +256,36 @@
233	256	ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
234	257	};
235	258
	259	+struct vop2_power_domain {
	260	+ struct vop2_power_domain *parent;
	261	+ struct vop2 *vop2;
	262	+ /*
	263	+ * @lock: protect power up/down procedure.
	264	+ * power on take effect immediately,
	265	+ * power down take effect by vsync.
	266	+ * we must check power_domain_status register
	267	+ * to make sure the power domain is down before
	268	+ * send a power on request.
	269	+ *
	270	+ */
	271	+ spinlock_t lock;
	272	+ unsigned int ref_count;
	273	+ bool on;
	274	+ /* @vp_mask: Bit mask of video port of the power domain's
	275	+ * module attached to.
	276	+ * For example: PD_CLUSTER0 belongs to module Cluster0, it's
	277	+ * bitmask is the VP which Cluster0 attached to. PD_ESMART is
	278	+ * shared between Esmart1/2/3, it's bitmask will be all the VP
	279	+ * which Esmart1/2/3 attached to.
	280	+ * This is used to check if we can power off a PD by vsync.
	281	+ */
	282	+ uint8_t vp_mask;
	283	+
	284	+ const struct vop2_power_domain_data *data;
	285	+ struct list_head list;
	286	+ struct delayed_work power_off_work;
	287	+};
	288	+
236	289	struct vop2_zpos {
237	290	struct drm_plane *plane;
238	291	int win_phys_id;
..	..	@@ -316,7 +369,6 @@
316	369	int global_alpha;
317	370	int blend_mode;
318	371	uint64_t color_key;
319		- void *yrgb_kvaddr;
320	372	unsigned long offset;
321	373	int pdaf_data_type;
322	374	bool async_commit;
..	..	@@ -338,11 +390,37 @@
338	390	bool two_win_mode;
339	391
340	392	/**
	393	+ * ---------------------------
	394	+ * \| \| \|
	395	+ * \| Left \| Right \|
	396	+ * \| \| \|
	397	+ * \| Cluster0 \| Cluster1 \|
	398	+ * ---------------------------
	399	+ */
	400	+
	401	+ /*
	402	+ * @splice_mode_right: As right part of the screen in splice mode.
	403	+ */
	404	+ bool splice_mode_right;
	405	+
	406	+ /**
	407	+ * @splice_win: splice win which used to splice for a plane
	408	+ * hdisplay > 4096
	409	+ */
	410	+ struct vop2_win *splice_win;
	411	+ struct vop2_win *left_win;
	412	+
	413	+ uint8_t splice_win_id;
	414	+
	415	+ struct vop2_power_domain *pd;
	416	+
	417	+ /**
341	418	* @phys_id: physical id for cluster0/1, esmart0/1, smart0/1
342	419	* Will be used as a identification for some register
343	420	* configuration such as OVL_LAYER_SEL/OVL_PORT_SEL.
344	421	*/
345	422	uint8_t phys_id;
	423	+
346	424	/**
347	425	* @win_id: graphic window id, a cluster maybe split into two
348	426	* graphics windows.
..	..	@@ -410,6 +488,7 @@
410	488	};
411	489
412	490	struct vop2_cluster {
	491	+ bool splice_mode;
413	492	struct vop2_win *main;
414	493	struct vop2_win *sub;
415	494	};
..	..	@@ -451,6 +530,17 @@
451	530
452	531	};
453	532
	533	+struct vop2_dsc {
	534	+ uint8_t id;
	535	+ uint8_t max_slice_num;
	536	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	537	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	538	+ bool enabled;
	539	+ char attach_vp_id;
	540	+ const struct vop2_dsc_regs *regs;
	541	+ struct vop2_power_domain *pd;
	542	+};
	543	+
454	544	enum vop2_wb_format {
455	545	VOP2_WB_ARGB8888,
456	546	VOP2_WB_BGR888,
..	..	@@ -471,12 +561,17 @@
471	561	};
472	562
473	563	struct vop2_video_port {
474		- struct drm_crtc crtc;
	564	+ struct rockchip_crtc rockchip_crtc;
	565	+ struct rockchip_mcu_timing mcu_timing;
475	566	struct vop2 *vop2;
	567	+ struct reset_control *dclk_rst;
476	568	struct clk *dclk;
	569	+ struct clk *dclk_parent;
477	570	uint8_t id;
478	571	bool layer_sel_update;
479	572	bool xmirror_en;
	573	+ bool need_reset_p2i_flag;
	574	+ atomic_t post_buf_empty_flag;
480	575	const struct vop2_video_port_regs *regs;
481	576
482	577	struct completion dsp_hold_completion;
..	..	@@ -524,15 +619,46 @@
524	619	int hdr_en;
525	620
526	621	/**
	622	+ * -----------------
	623	+ * \| \| \|
	624	+ * \| Left \| Right \|
	625	+ * \| \| \|
	626	+ * \| VP0 \| VP1 \|
	627	+ * -----------------
	628	+ * @splice_mode_right: As right part of the screen in splice mode.
	629	+ */
	630	+ bool splice_mode_right;
	631	+
	632	+ /**
	633	+ * @hdr10_at_splice_mode: enable hdr10 at splice mode on rk3588.
	634	+ */
	635	+ bool hdr10_at_splice_mode;
	636	+ /**
	637	+ * @left_vp: VP as left part of the screen in splice mode.
	638	+ */
	639	+ struct vop2_video_port *left_vp;
	640	+
	641	+ /**
527	642	* @win_mask: Bitmask of wins attached to the video port;
528	643	*/
529	644	uint32_t win_mask;
	645	+ /**
	646	+ * @enabled_win_mask: Bitmask of enabled wins attached to the video port;
	647	+ */
	648	+ uint32_t enabled_win_mask;
	649	+
530	650	/**
531	651	* @nr_layers: active layers attached to the video port;
532	652	*/
533	653	uint8_t nr_layers;
534	654
535	655	int cursor_win_id;
	656	+ /**
	657	+ * @output_if: output connector attached to the video port,
	658	+ * this flag is maintained in vop driver, updated in crtc_atomic_enable,
	659	+ * cleared in crtc_atomic_disable;
	660	+ */
	661	+ u32 output_if;
536	662
537	663	/**
538	664	* @active_tv_state: TV connector related states
..	..	@@ -555,6 +681,11 @@
555	681	bool gamma_lut_active;
556	682
557	683	/**
	684	+ * @lut_dma_rid: lut dma id
	685	+ */
	686	+ u16 lut_dma_rid;
	687	+
	688	+ /**
558	689	* @gamma_lut: atomic gamma look up table
559	690	*/
560	691	struct drm_color_lut *gamma_lut;
..	..	@@ -568,6 +699,11 @@
568	699	* @cubic_lut_gem_obj: gem obj to store cubic lut
569	700	*/
570	701	struct rockchip_gem_object *cubic_lut_gem_obj;
	702	+
	703	+ /**
	704	+ * @hdr_lut_gem_obj: gem obj to store hdr lut
	705	+ */
	706	+ struct rockchip_gem_object *hdr_lut_gem_obj;
571	707
572	708	/**
573	709	* @cubic_lut: cubic look up table
..	..	@@ -589,27 +725,81 @@
589	725	* @plane_mask_prop: plane mask interaction with userspace
590	726	*/
591	727	struct drm_property *plane_mask_prop;
	728	+ /**
	729	+ * @feature_prop: crtc feature interaction with userspace
	730	+ */
	731	+ struct drm_property *feature_prop;
	732	+
	733	+ /**
	734	+ * @variable_refresh_rate_prop: crtc variable refresh rate interaction with userspace
	735	+ */
	736	+ struct drm_property *variable_refresh_rate_prop;
	737	+
	738	+ /**
	739	+ * @max_refresh_rate_prop: crtc max refresh rate interaction with userspace
	740	+ */
	741	+ struct drm_property *max_refresh_rate_prop;
	742	+
	743	+ /**
	744	+ * @min_refresh_rate_prop: crtc min refresh rate interaction with userspace
	745	+ */
	746	+ struct drm_property *min_refresh_rate_prop;
	747	+
	748	+ /**
	749	+ * @hdr_ext_data_prop: hdr extend data interaction with userspace
	750	+ */
	751	+ struct drm_property *hdr_ext_data_prop;
	752	+
	753	+ int hdrvivid_mode;
	754	+
	755	+ /**
	756	+ * @acm_lut_data_prop: acm lut data interaction with userspace
	757	+ */
	758	+ struct drm_property *acm_lut_data_prop;
	759	+ /**
	760	+ * @post_csc_data_prop: post csc data interaction with userspace
	761	+ */
	762	+ struct drm_property *post_csc_data_prop;
	763	+ /**
	764	+ * @output_width_prop: vp max output width prop
	765	+ */
	766	+ struct drm_property *output_width_prop;
	767	+ /**
	768	+ * @output_dclk_prop: vp max output dclk prop
	769	+ */
	770	+ struct drm_property *output_dclk_prop;
592	771
593	772	/**
594	773	* @primary_plane_phy_id: vp primary plane phy id, the primary plane
595	774	* will be used to show uboot logo and kernel logo
596	775	*/
597	776	enum vop2_layer_phy_id primary_plane_phy_id;
	777	+
	778	+ struct post_acm acm_info;
	779	+ struct post_csc csc_info;
	780	+
	781	+ /**
	782	+ * @refresh_rate_change: indicate whether refresh rate change
	783	+ */
	784	+ bool refresh_rate_change;
	785	+};
	786	+
	787	+struct vop2_extend_pll {
	788	+ struct list_head list;
	789	+ struct clk *clk;
	790	+ char clk_name[32];
	791	+ u32 vp_mask;
598	792	};
599	793
600	794	struct vop2 {
601	795	u32 version;
602	796	struct device *dev;
603	797	struct drm_device *drm_dev;
	798	+ struct vop2_dsc dscs[ROCKCHIP_MAX_CRTC];
604	799	struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
605	800	struct vop2_wb wb;
606	801	struct dentry *debugfs;
607	802	struct drm_info_list *debugfs_files;
608		- struct drm_property *soc_id_prop;
609		- struct drm_property *vp_id_prop;
610		- struct drm_property *aclk_prop;
611		- struct drm_property *bg_prop;
612		- struct drm_property *line_flag_prop;
613	803	struct drm_prop_enum_list *plane_name_list;
614	804	bool is_iommu_enabled;
615	805	bool is_iommu_needed;
..	..	@@ -645,6 +835,9 @@
645	835
646	836	bool loader_protect;
647	837
	838	+ bool aclk_rate_reset;
	839	+ unsigned long aclk_rate;
	840	+
648	841	const struct vop2_data *data;
649	842	/* Number of win that registered as plane,
650	843	* maybe less than the total number of hardware
..	..	@@ -652,6 +845,7 @@
652	845	*/
653	846	uint32_t registered_num_wins;
654	847	uint8_t used_mixers;
	848	+ uint8_t esmart_lb_mode;
655	849	/**
656	850	* @active_vp_mask: Bitmask of active video ports;
657	851	*/
..	..	@@ -662,6 +856,10 @@
662	856	struct resource *res;
663	857	void __iomem *regs;
664	858	struct regmap *grf;
	859	+ struct regmap *sys_grf;
	860	+ struct regmap *vo0_grf;
	861	+ struct regmap *vo1_grf;
	862	+ struct regmap *sys_pmu;
665	863
666	864	/* physical map length of vop2 register */
667	865	uint32_t len;
..	..	@@ -684,11 +882,35 @@
684	882	unsigned int enable_count;
685	883	struct clk *hclk;
686	884	struct clk *aclk;
	885	+ struct clk *pclk;
	886	+ struct reset_control *ahb_rst;
	887	+ struct reset_control *axi_rst;
	888	+ struct csu_clk *csu_aclk;
	889	+
	890	+ /* list_head of extend clk */
	891	+ struct list_head extend_clk_list_head;
	892	+ /* list_head of internal clk */
	893	+ struct list_head clk_list_head;
	894	+ struct list_head pd_list_head;
	895	+ struct work_struct post_buf_empty_work;
	896	+ struct workqueue_struct *workqueue;
687	897
688	898	struct vop2_layer layers[ROCKCHIP_MAX_LAYER];
689	899	/* must put at the end of the struct */
690	900	struct vop2_win win[];
691	901	};
	902	+
	903	+struct vop2_clk {
	904	+ struct vop2 *vop2;
	905	+ struct list_head list;
	906	+ unsigned long rate;
	907	+ struct clk_hw hw;
	908	+ struct clk_divider div;
	909	+ int div_val;
	910	+ u8 parent_index;
	911	+};
	912	+
	913	+#define to_vop2_clk(_hw) container_of(_hw, struct vop2_clk, hw)
692	914
693	915	/*
694	916	* bus-format types.
..	..	@@ -704,22 +926,33 @@
704	926	{ MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" },
705	927	{ MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" },
706	928	{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" },
707		- { MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA, "RGB666_1X7X3_JEIDA" },
708	929	{ MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" },
709	930	{ MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" },
710	931	{ MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" },
711	932	{ MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" },
712		- { MEDIA_BUS_FMT_SRGB888_3X8, "SRGB888_3X8" },
713		- { MEDIA_BUS_FMT_SRGB888_DUMMY_4X8, "SRGB888_DUMMY_4X8" },
	933	+ { MEDIA_BUS_FMT_RGB565_2X8_LE, "RGB565_2X8_LE" },
	934	+ { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" },
	935	+ { MEDIA_BUS_FMT_RGB888_DUMMY_4X8, "RGB888_DUMMY_4X8" },
714	936	{ MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" },
715	937	{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" },
716	938	{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" },
717	939	{ MEDIA_BUS_FMT_UYVY8_2X8, "UYVY8_2X8" },
718	940	{ MEDIA_BUS_FMT_YUYV8_1X16, "YUYV8_1X16" },
719	941	{ MEDIA_BUS_FMT_UYVY8_1X16, "UYVY8_1X16" },
	942	+ { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1X30" },
	943	+ { MEDIA_BUS_FMT_YUYV10_1X20, "YUYV10_1X20" },
720	944	};
721	945
722	946	static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list)
	947	+
	948	+static inline struct vop2_video_port to_vop2_video_port(struct drm_crtc crtc)
	949	+{
	950	+ struct rockchip_crtc *rockchip_crtc;
	951	+
	952	+ rockchip_crtc = container_of(crtc, struct rockchip_crtc, crtc);
	953	+
	954	+ return container_of(rockchip_crtc, struct vop2_video_port, rockchip_crtc);
	955	+}
723	956
724	957	static void vop2_lock(struct vop2 *vop2)
725	958	{
..	..	@@ -733,17 +966,26 @@
733	966	mutex_unlock(&vop2->vop2_lock);
734	967	}
735	968
736		-static inline void vop2_grf_writel(struct vop2 *vop2, struct vop_reg reg, u32 v)
	969	+static inline void vop2_grf_writel(struct regmap *regmap, struct vop_reg reg, u32 v)
737	970	{
738	971	u32 val = 0;
739	972
740		- if (IS_ERR_OR_NULL(vop2->grf))
	973	+ if (IS_ERR_OR_NULL(regmap))
741	974	return;
742	975
743	976	if (reg.mask) {
744	977	val = (v << reg.shift) \| (reg.mask << (reg.shift + 16));
745		- regmap_write(vop2->grf, reg.offset, val);
	978	+ regmap_write(regmap, reg.offset, val);
746	979	}
	980	+}
	981	+
	982	+static inline uint32_t vop2_grf_readl(struct regmap regmap, const struct vop_reg reg)
	983	+{
	984	+ uint32_t v;
	985	+
	986	+ regmap_read(regmap, reg->offset, &v);
	987	+
	988	+ return v;
747	989	}
748	990
749	991	static inline void vop2_writel(struct vop2 *vop2, uint32_t offset, uint32_t v)
..	..	@@ -761,6 +1003,26 @@
761	1003	const struct vop_reg *reg)
762	1004	{
763	1005	return (vop2_readl(vop2, base + reg->offset) >> reg->shift) & reg->mask;
	1006	+}
	1007	+
	1008	+static inline uint32_t vop2_read_reg_bak(struct vop2 *vop2, uint32_t base,
	1009	+ const struct vop_reg *reg)
	1010	+{
	1011	+ return (vop2->regsbak[(base + reg->offset) >> 2] >> reg->shift) & reg->mask;
	1012	+}
	1013	+
	1014	+static inline uint32_t vop2_read_grf_reg(struct regmap regmap, const struct vop_reg reg)
	1015	+{
	1016	+ return (vop2_grf_readl(regmap, reg) >> reg->shift) & reg->mask;
	1017	+}
	1018	+
	1019	+static inline void vop2_write_reg_uncached(struct vop2 vop2, const struct vop_reg reg, uint32_t v)
	1020	+{
	1021	+ uint32_t offset = reg->offset;
	1022	+ uint32_t cached_val = vop2->regsbak[offset >> 2];
	1023	+
	1024	+ v = (cached_val & ~(reg->mask << reg->shift)) \| ((v & reg->mask) << reg->shift);
	1025	+ writel(v, vop2->regs + offset);
764	1026	}
765	1027
766	1028	static inline void vop2_mask_write(struct vop2 *vop2, uint32_t offset,
..	..	@@ -841,7 +1103,7 @@
841	1103	}
842	1104	}
843	1105
844		-void vop2_standby(struct drm_crtc *crtc, bool standby)
	1106	+static void vop2_crtc_standby(struct drm_crtc *crtc, bool standby)
845	1107	{
846	1108	struct vop2_video_port *vp = to_vop2_video_port(crtc);
847	1109	struct vop2 *vop2 = vp->vop2;
..	..	@@ -853,7 +1115,6 @@
853	1115	VOP_MODULE_SET(vop2, vp, standby, 0);
854	1116	}
855	1117	}
856		-EXPORT_SYMBOL(vop2_standby);
857	1118
858	1119	static inline const struct vop2_win_regs vop2_get_win_regs(struct vop2_win win,
859	1120	const struct vop_reg *reg)
..	..	@@ -899,6 +1160,32 @@
899	1160	return NULL;
900	1161	}
901	1162
	1163	+static struct vop2_power_domain vop2_find_pd_by_id(struct vop2 vop2, uint8_t id)
	1164	+{
	1165	+ struct vop2_power_domain pd, n;
	1166	+
	1167	+ list_for_each_entry_safe(pd, n, &vop2->pd_list_head, list) {
	1168	+ if (pd->data->id == id)
	1169	+ return pd;
	1170	+ }
	1171	+
	1172	+ return NULL;
	1173	+}
	1174	+
	1175	+static const struct vop2_connector_if_data vop2_find_connector_if_data(struct vop2 vop2, int id)
	1176	+{
	1177	+ const struct vop2_connector_if_data *if_data;
	1178	+ int i;
	1179	+
	1180	+ for (i = 0; i < vop2->data->nr_conns; i++) {
	1181	+ if_data = &vop2->data->conn[i];
	1182	+ if (if_data->id == id)
	1183	+ return if_data;
	1184	+ }
	1185	+
	1186	+ return NULL;
	1187	+}
	1188	+
902	1189	static struct drm_crtc vop2_find_crtc_by_plane_mask(struct vop2 vop2, uint8_t phys_id)
903	1190	{
904	1191	struct vop2_video_port *vp;
..	..	@@ -907,10 +1194,28 @@
907	1194	for (i = 0; i < vop2->data->nr_vps; i++) {
908	1195	vp = &vop2->vps[i];
909	1196	if (vp->plane_mask & BIT(phys_id))
910		- return &vp->crtc;
	1197	+ return &vp->rockchip_crtc.crtc;
911	1198	}
912	1199
913	1200	return NULL;
	1201	+}
	1202	+
	1203	+static int vop2_clk_reset(struct reset_control *rstc)
	1204	+{
	1205	+ int ret;
	1206	+
	1207	+ if (!rstc)
	1208	+ return 0;
	1209	+
	1210	+ ret = reset_control_assert(rstc);
	1211	+ if (ret < 0)
	1212	+ DRM_WARN("failed to assert reset\n");
	1213	+ udelay(10);
	1214	+ ret = reset_control_deassert(rstc);
	1215	+ if (ret < 0)
	1216	+ DRM_WARN("failed to deassert reset\n");
	1217	+
	1218	+ return ret;
914	1219	}
915	1220
916	1221	static void vop2_load_hdr2sdr_table(struct vop2_video_port *vp)
..	..	@@ -991,8 +1296,23 @@
991	1296	static uint32_t vop2_read_vcnt(struct vop2_video_port *vp)
992	1297	{
993	1298	uint32_t offset = RK3568_SYS_STATUS0 + (vp->id << 2);
	1299	+ uint32_t vcnt0, vcnt1;
	1300	+ int i = 0;
994	1301
995		- return vop2_readl(vp->vop2, offset) >> 16;
	1302	+ for (i = 0; i < 10; i++) {
	1303	+ vcnt0 = vop2_readl(vp->vop2, offset) >> 16;
	1304	+ vcnt1 = vop2_readl(vp->vop2, offset) >> 16;
	1305	+
	1306	+ if ((vcnt1 - vcnt0) <= 1)
	1307	+ break;
	1308	+ }
	1309	+
	1310	+ if (i == 10) {
	1311	+ DRM_DEV_ERROR(vp->vop2->dev, "read VP%d vcnt error: %d %d\n", vp->id, vcnt0, vcnt1);
	1312	+ vcnt1 = vop2_readl(vp->vop2, offset) >> 16;
	1313	+ }
	1314	+
	1315	+ return vcnt1;
996	1316	}
997	1317
998	1318	static void vop2_wait_for_irq_handler(struct drm_crtc *crtc)
..	..	@@ -1112,7 +1432,7 @@
1112	1432	done_bits &= ~BIT(vp->id);
1113	1433	vp_id = ffs(done_bits) - 1;
1114	1434	done_vp = &vop2->vps[vp_id];
1115		- adjusted_mode = &done_vp->crtc.state->adjusted_mode;
	1435	+ adjusted_mode = &done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1116	1436	vcnt = vop2_read_vcnt(done_vp);
1117	1437	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1118	1438	vcnt >>= 1;
..	..	@@ -1133,7 +1453,7 @@
1133	1453
1134	1454	first_vp_id = ffs(done_bits) - 1;
1135	1455	first_done_vp = &vop2->vps[first_vp_id];
1136		- first_mode = &first_done_vp->crtc.state->adjusted_mode;
	1456	+ first_mode = &first_done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1137	1457	/* set last 1/8 frame time as safe section */
1138	1458	vrefresh = drm_mode_vrefresh(first_mode);
1139	1459	if (!vrefresh) {
..	..	@@ -1145,7 +1465,7 @@
1145	1465	done_bits &= ~BIT(first_vp_id);
1146	1466	second_vp_id = ffs(done_bits) - 1;
1147	1467	second_done_vp = &vop2->vps[second_vp_id];
1148		- second_mode = &second_done_vp->crtc.state->adjusted_mode;
	1468	+ second_mode = &second_done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1149	1469	/* set last 1/8 frame time as safe section */
1150	1470	vrefresh = drm_mode_vrefresh(second_mode);
1151	1471	if (!vrefresh) {
..	..	@@ -1190,6 +1510,26 @@
1190	1510	return done_bits;
1191	1511	}
1192	1512
	1513	+static inline void rk3588_vop2_dsc_cfg_done(struct drm_crtc *crtc)
	1514	+{
	1515	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	1516	+ struct vop2 *vop2 = vp->vop2;
	1517	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	1518	+ struct vop2_dsc *dsc = &vop2->dscs[vcstate->dsc_id];
	1519	+
	1520	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	1521	+ dsc = &vop2->dscs[0];
	1522	+ if (vcstate->dsc_enable)
	1523	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1524	+ dsc = &vop2->dscs[1];
	1525	+ if (vcstate->dsc_enable)
	1526	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1527	+ } else {
	1528	+ if (vcstate->dsc_enable)
	1529	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1530	+ }
	1531	+}
	1532	+
1193	1533	static inline void rk3568_vop2_cfg_done(struct drm_crtc *crtc)
1194	1534	{
1195	1535	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -1224,6 +1564,9 @@
1224	1564	* This is rather low probability for miss some done bit.
1225	1565	*/
1226	1566	val \|= vop2_readl(vop2, RK3568_REG_CFG_DONE) & 0x7;
	1567	+
	1568	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
	1569	+
1227	1570	vop2_writel(vop2, 0, val);
1228	1571
1229	1572	/**
..	..	@@ -1240,10 +1583,16 @@
1240	1583	static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc)
1241	1584	{
1242	1585	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	1586	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	1587	+ const struct vop2_video_port_data *vp_data = &vp->vop2->data->vp[vp->id];
1243	1588	struct vop2 *vop2 = vp->vop2;
1244	1589	uint32_t val;
1245	1590
1246	1591	val = RK3568_VOP2_GLB_CFG_DONE_EN \| BIT(vp->id) \| (BIT(vp->id) << 16);
	1592	+ if (vcstate->splice_mode)
	1593	+ val \|= BIT(vp_data->splice_vp_id) \| (BIT(vp_data->splice_vp_id) << 16);
	1594	+
	1595	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
1247	1596
1248	1597	vop2_writel(vop2, 0, val);
1249	1598	}
..	..	@@ -1265,6 +1614,7 @@
1265	1614	} else {
1266	1615	vop2_writel(vop2, 0, val);
1267	1616	}
	1617	+
1268	1618	}
1269	1619
1270	1620	static inline void vop2_cfg_done(struct drm_crtc *crtc)
..	..	@@ -1276,6 +1626,178 @@
1276	1626	return rk3568_vop2_cfg_done(crtc);
1277	1627	else
1278	1628	return rk3588_vop2_cfg_done(crtc);
	1629	+}
	1630	+
	1631	+/*
	1632	+ * A PD can power off by vsync when it's module attached to
	1633	+ * a activated VP.
	1634	+ */
	1635	+static uint32_t vop2_power_domain_can_off_by_vsync(struct vop2_power_domain *pd)
	1636	+{
	1637	+ struct vop2 *vop2 = pd->vop2;
	1638	+
	1639	+ if (vop2->active_vp_mask & pd->vp_mask)
	1640	+ return true;
	1641	+ else
	1642	+ return false;
	1643	+}
	1644	+
	1645	+/*
	1646	+ * Read VOP internal power domain on/off status.
	1647	+ * We should query BISR_STS register in PMU for
	1648	+ * power up/down status when memory repair is enabled.
	1649	+ * Return value: 1 for power on, 0 for power off;
	1650	+ */
	1651	+static uint32_t vop2_power_domain_status(struct vop2_power_domain *pd)
	1652	+{
	1653	+ struct vop2 *vop2 = pd->vop2;
	1654	+
	1655	+ if (vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->bisr_en_status))
	1656	+ return vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->pmu_status);
	1657	+ else
	1658	+ return vop2_read_reg(vop2, 0, &pd->data->regs->status) ? 0 : 1;
	1659	+}
	1660	+
	1661	+static void vop2_wait_power_domain_off(struct vop2_power_domain *pd)
	1662	+{
	1663	+ struct vop2 *vop2 = pd->vop2;
	1664	+ int val;
	1665	+ int ret;
	1666	+
	1667	+ ret = readx_poll_timeout_atomic(vop2_power_domain_status, pd, val, !val, 0, 50 * 1000);
	1668	+
	1669	+ if (ret)
	1670	+ DRM_DEV_ERROR(vop2->dev, "wait pd%d off timeout power_ctrl: 0x%x\n",
	1671	+ ffs(pd->data->id) - 1, vop2_readl(vop2, 0x34));
	1672	+}
	1673	+
	1674	+static void vop2_wait_power_domain_on(struct vop2_power_domain *pd)
	1675	+{
	1676	+ struct vop2 *vop2 = pd->vop2;
	1677	+ int val;
	1678	+ int ret;
	1679	+
	1680	+ ret = readx_poll_timeout_atomic(vop2_power_domain_status, pd, val, val, 0, 50 * 1000);
	1681	+ if (ret)
	1682	+ DRM_DEV_ERROR(vop2->dev, "wait pd%d on timeout power_ctrl: 0x%x\n",
	1683	+ ffs(pd->data->id) - 1, vop2_readl(vop2, 0x34));
	1684	+}
	1685	+
	1686	+/*
	1687	+ * Power domain on take effect immediately
	1688	+ */
	1689	+static void vop2_power_domain_on(struct vop2_power_domain *pd)
	1690	+{
	1691	+ struct vop2 *vop2 = pd->vop2;
	1692	+
	1693	+ if (!pd->on) {
	1694	+ dev_dbg(vop2->dev, "pd%d on\n", ffs(pd->data->id) - 1);
	1695	+ vop2_wait_power_domain_off(pd);
	1696	+ VOP_MODULE_SET(vop2, pd->data, pd, 0);
	1697	+ vop2_wait_power_domain_on(pd);
	1698	+ pd->on = true;
	1699	+ }
	1700	+}
	1701	+
	1702	+/*
	1703	+ * Power domain off take effect by vsync.
	1704	+ */
	1705	+static void vop2_power_domain_off(struct vop2_power_domain *pd)
	1706	+{
	1707	+ struct vop2 *vop2 = pd->vop2;
	1708	+
	1709	+ dev_dbg(vop2->dev, "pd%d off\n", ffs(pd->data->id) - 1);
	1710	+ pd->on = false;
	1711	+ VOP_MODULE_SET(vop2, pd->data, pd, 1);
	1712	+}
	1713	+
	1714	+static void vop2_power_domain_get(struct vop2_power_domain *pd)
	1715	+{
	1716	+ if (pd->parent)
	1717	+ vop2_power_domain_get(pd->parent);
	1718	+
	1719	+ spin_lock(&pd->lock);
	1720	+ if (pd->ref_count == 0) {
	1721	+ if (pd->vop2->data->delayed_pd)
	1722	+ cancel_delayed_work(&pd->power_off_work);
	1723	+ vop2_power_domain_on(pd);
	1724	+ }
	1725	+ pd->ref_count++;
	1726	+ spin_unlock(&pd->lock);
	1727	+}
	1728	+
	1729	+static void vop2_power_domain_put(struct vop2_power_domain *pd)
	1730	+{
	1731	+ spin_lock(&pd->lock);
	1732	+
	1733	+ /*
	1734	+ * For a nested power domain(PD_Cluster0 is the parent of PD_CLuster1/2/3)
	1735	+ * the parent power domain must be enabled before child power domain
	1736	+ * is on.
	1737	+ *
	1738	+ * So we may met this condition: Cluster0 is not on a activated VP,
	1739	+ * but PD_Cluster0 must enabled as one of the child PD_CLUSTER1/2/3 is enabled.
	1740	+ * when all child PD is disabled, we want disable the parent
	1741	+ * PD(PD_CLUSTER0), but as module CLUSTER0 is not attcthed on a activated VP,
	1742	+ * the turn off operation(which is take effect by vsync) will never take effect.
	1743	+ * so we will see a "wait pd0 off timeout" log when we turn on PD_CLUSTER0 next time.
	1744	+ *
	1745	+ * So we have a check here
	1746	+ */
	1747	+ if (--pd->ref_count == 0 && vop2_power_domain_can_off_by_vsync(pd)) {
	1748	+ if (pd->vop2->data->delayed_pd)
	1749	+ schedule_delayed_work(&pd->power_off_work, msecs_to_jiffies(2500));
	1750	+ else
	1751	+ vop2_power_domain_off(pd);
	1752	+ }
	1753	+
	1754	+ spin_unlock(&pd->lock);
	1755	+ if (pd->parent)
	1756	+ vop2_power_domain_put(pd->parent);
	1757	+}
	1758	+
	1759	+/*
	1760	+ * Called if the pd ref_count reach 0 after 2.5
	1761	+ * seconds.
	1762	+ */
	1763	+static void vop2_power_domain_off_work(struct work_struct *work)
	1764	+{
	1765	+ struct vop2_power_domain *pd;
	1766	+
	1767	+ pd = container_of(to_delayed_work(work), struct vop2_power_domain, power_off_work);
	1768	+
	1769	+ spin_lock(&pd->lock);
	1770	+ if (pd->ref_count == 0)
	1771	+ vop2_power_domain_off(pd);
	1772	+ spin_unlock(&pd->lock);
	1773	+}
	1774	+
	1775	+static void vop2_win_enable(struct vop2_win *win)
	1776	+{
	1777	+ /*
	1778	+ * a win such as cursor update by async:
	1779	+ * first frame enable win pd, enable win, return without wait vsync
	1780	+ * second frame come, but the first frame may still not enabled
	1781	+ * in this case, the win pd is turn on by fist frame, so we don't
	1782	+ * need get pd again.
	1783	+ *
	1784	+ * another case:
	1785	+ * first frame: disable win, disable pd, return without wait vsync
	1786	+ * second frame come very soon, the previous win disable may still not
	1787	+ * take effect, but the pd is disable in progress, we should do pd_get
	1788	+ * at this situation.
	1789	+ *
	1790	+ * check the backup register for previous enable operation.
	1791	+ */
	1792	+ if (!VOP_WIN_GET_REG_BAK(win->vop2, win, enable)) {
	1793	+ if (win->pd) {
	1794	+ if (win->pd->data->id == VOP2_PD_ESMART)
	1795	+ return;
	1796	+
	1797	+ vop2_power_domain_get(win->pd);
	1798	+ win->pd->vp_mask \|= win->vp_mask;
	1799	+ }
	1800	+ }
1279	1801	}
1280	1802
1281	1803	static void vop2_win_multi_area_disable(struct vop2_win *parent)
..	..	@@ -1291,31 +1813,63 @@
1291	1813	}
1292	1814	}
1293	1815
1294		-static void vop2_win_disable(struct vop2_win *win)
	1816	+static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win)
1295	1817	{
1296	1818	struct vop2 *vop2 = win->vop2;
1297	1819
1298		- VOP_WIN_SET(vop2, win, enable, 0);
1299		- if (win->feature & WIN_FEATURE_CLUSTER_MAIN) {
1300		- struct vop2_win *sub_win;
1301		- int i = 0;
1302		-
1303		- for (i = 0; i < vop2->registered_num_wins; i++) {
1304		- sub_win = &vop2->win[i];
1305		-
1306		- if ((sub_win->phys_id == win->phys_id) &&
1307		- (sub_win->feature & WIN_FEATURE_CLUSTER_SUB))
1308		- VOP_WIN_SET(vop2, sub_win, enable, 0);
1309		- }
1310		-
1311		- VOP_CLUSTER_SET(vop2, win, enable, 0);
	1820	+ /* Disable the right splice win */
	1821	+ if (win->splice_win && !skip_splice_win) {
	1822	+ vop2_win_disable(win->splice_win, false);
	1823	+ win->splice_win = NULL;
1312	1824	}
1313	1825
1314		- /*
1315		- * disable all other multi area win if we want disable area0 here
1316		- */
1317		- if (!win->parent && (win->feature & WIN_FEATURE_MULTI_AREA))
1318		- vop2_win_multi_area_disable(win);
	1826	+ if (VOP_WIN_GET(vop2, win, enable) \|\| VOP_WIN_GET_REG_BAK(vop2, win, enable)) {
	1827	+ VOP_WIN_SET(vop2, win, enable, 0);
	1828	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN) {
	1829	+ struct vop2_win *sub_win;
	1830	+ int i = 0;
	1831	+
	1832	+ for (i = 0; i < vop2->registered_num_wins; i++) {
	1833	+ sub_win = &vop2->win[i];
	1834	+
	1835	+ if ((sub_win->phys_id == win->phys_id) &&
	1836	+ (sub_win->feature & WIN_FEATURE_CLUSTER_SUB))
	1837	+ VOP_WIN_SET(vop2, sub_win, enable, 0);
	1838	+ }
	1839	+
	1840	+ VOP_CLUSTER_SET(vop2, win, enable, 0);
	1841	+ }
	1842	+
	1843	+ /*
	1844	+ * disable all other multi area win if we want disable area0 here
	1845	+ */
	1846	+ if (!win->parent && (win->feature & WIN_FEATURE_MULTI_AREA))
	1847	+ vop2_win_multi_area_disable(win);
	1848	+
	1849	+ if (win->pd) {
	1850	+
	1851	+ /*
	1852	+ * Don't dynamic turn on/off PD_ESMART.
	1853	+ * (1) There is a design issue for PD_EMSART when attached
	1854	+ * on VP1/2/3, we found it will trigger POST_BUF_EMPTY irq at vp0
	1855	+ * in splice mode.
	1856	+ * (2) PD_ESMART will be closed at esmart layers attathed on VPs
	1857	+ * config done + FS, but different VP FS time is different, this
	1858	+ * maybe lead to PD_ESMART closed at wrong time and display error.
	1859	+ * (3) PD_ESMART power up maybe have 4 us delay, this will lead to POST_BUF_EMPTY.
	1860	+ */
	1861	+ if (win->pd->data->id == VOP2_PD_ESMART)
	1862	+ return;
	1863	+
	1864	+ vop2_power_domain_put(win->pd);
	1865	+ win->pd->vp_mask &= ~win->vp_mask;
	1866	+ }
	1867	+ }
	1868	+
	1869	+ if (win->left_win && win->splice_mode_right) {
	1870	+ win->left_win = NULL;
	1871	+ win->splice_mode_right = false;
	1872	+ }
1319	1873	}
1320	1874
1321	1875	static inline void vop2_write_lut(struct vop2 *vop2, uint32_t offset, uint32_t v)
..	..	@@ -1328,9 +1882,26 @@
1328	1882	return readl(vop2->lut_regs + offset);
1329	1883	}
1330	1884
	1885	+static bool is_linear_10bit_yuv(uint32_t format)
	1886	+{
	1887	+ switch (format) {
	1888	+ case DRM_FORMAT_NV15:
	1889	+ case DRM_FORMAT_NV20:
	1890	+ case DRM_FORMAT_NV30:
	1891	+ return true;
	1892	+ default:
	1893	+ return false;
	1894	+ }
	1895	+}
	1896	+
1331	1897	static enum vop2_data_format vop2_convert_format(uint32_t format)
1332	1898	{
1333	1899	switch (format) {
	1900	+ case DRM_FORMAT_XRGB2101010:
	1901	+ case DRM_FORMAT_ARGB2101010:
	1902	+ case DRM_FORMAT_XBGR2101010:
	1903	+ case DRM_FORMAT_ABGR2101010:
	1904	+ return VOP2_FMT_XRGB101010;
1334	1905	case DRM_FORMAT_XRGB8888:
1335	1906	case DRM_FORMAT_ARGB8888:
1336	1907	case DRM_FORMAT_XBGR8888:
..	..	@@ -1343,16 +1914,22 @@
1343	1914	case DRM_FORMAT_BGR565:
1344	1915	return VOP2_FMT_RGB565;
1345	1916	case DRM_FORMAT_NV12:
	1917	+ case DRM_FORMAT_NV21:
	1918	+ case DRM_FORMAT_YUV420_8BIT:
1346	1919	return VOP2_FMT_YUV420SP;
1347		- case DRM_FORMAT_NV12_10:
	1920	+ case DRM_FORMAT_NV15:
	1921	+ case DRM_FORMAT_YUV420_10BIT:
1348	1922	return VOP2_FMT_YUV420SP_10;
1349	1923	case DRM_FORMAT_NV16:
	1924	+ case DRM_FORMAT_NV61:
1350	1925	return VOP2_FMT_YUV422SP;
1351		- case DRM_FORMAT_NV16_10:
	1926	+ case DRM_FORMAT_NV20:
	1927	+ case DRM_FORMAT_Y210:
1352	1928	return VOP2_FMT_YUV422SP_10;
1353	1929	case DRM_FORMAT_NV24:
	1930	+ case DRM_FORMAT_NV42:
1354	1931	return VOP2_FMT_YUV444SP;
1355		- case DRM_FORMAT_NV24_10:
	1932	+ case DRM_FORMAT_NV30:
1356	1933	return VOP2_FMT_YUV444SP_10;
1357	1934	case DRM_FORMAT_YUYV:
1358	1935	case DRM_FORMAT_YVYU:
..	..	@@ -1369,6 +1946,11 @@
1369	1946	static enum vop2_afbc_format vop2_convert_afbc_format(uint32_t format)
1370	1947	{
1371	1948	switch (format) {
	1949	+ case DRM_FORMAT_XRGB2101010:
	1950	+ case DRM_FORMAT_ARGB2101010:
	1951	+ case DRM_FORMAT_XBGR2101010:
	1952	+ case DRM_FORMAT_ABGR2101010:
	1953	+ return VOP2_AFBC_FMT_ARGB2101010;
1372	1954	case DRM_FORMAT_XRGB8888:
1373	1955	case DRM_FORMAT_ARGB8888:
1374	1956	case DRM_FORMAT_XBGR8888:
..	..	@@ -1380,14 +1962,16 @@
1380	1962	case DRM_FORMAT_RGB565:
1381	1963	case DRM_FORMAT_BGR565:
1382	1964	return VOP2_AFBC_FMT_RGB565;
1383		- case DRM_FORMAT_NV12:
	1965	+ case DRM_FORMAT_YUV420_8BIT:
1384	1966	return VOP2_AFBC_FMT_YUV420;
1385		- case DRM_FORMAT_NV12_10:
	1967	+ case DRM_FORMAT_YUV420_10BIT:
1386	1968	return VOP2_AFBC_FMT_YUV420_10BIT;
1387		- case DRM_FORMAT_NV16:
	1969	+ case DRM_FORMAT_YVYU:
1388	1970	case DRM_FORMAT_YUYV:
	1971	+ case DRM_FORMAT_VYUY:
	1972	+ case DRM_FORMAT_UYVY:
1389	1973	return VOP2_AFBC_FMT_YUV422;
1390		- case DRM_FORMAT_NV16_10:
	1974	+ case DRM_FORMAT_Y210:
1391	1975	return VOP2_AFBC_FMT_YUV422_10BIT;
1392	1976
1393	1977	/* either of the below should not be reachable */
..	..	@@ -1411,11 +1995,11 @@
1411	1995	case DRM_FORMAT_NV24:
1412	1996	case DRM_FORMAT_NV42:
1413	1997	return VOP2_TILED_8X8_FMT_YUV444SP;
1414		- case DRM_FORMAT_NV12_10:
	1998	+ case DRM_FORMAT_NV15:
1415	1999	return VOP2_TILED_8X8_FMT_YUV420SP_10;
1416		- case DRM_FORMAT_NV16_10:
	2000	+ case DRM_FORMAT_NV20:
1417	2001	return VOP2_TILED_8X8_FMT_YUV422SP_10;
1418		- case DRM_FORMAT_NV24_10:
	2002	+ case DRM_FORMAT_NV30:
1419	2003	return VOP2_TILED_8X8_FMT_YUV444SP_10;
1420	2004	default:
1421	2005	DRM_WARN_ONCE("unsupported tiled format[%08x]\n", format);
..	..	@@ -1440,13 +2024,13 @@
1440	2024	case DRM_FORMAT_NV42:
1441	2025	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1442	2026	VOP3_TILED_8X8_FMT_YUV444SP : VOP3_TILED_4X4_FMT_YUV444SP;
1443		- case DRM_FORMAT_NV12_10:
	2027	+ case DRM_FORMAT_NV15:
1444	2028	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1445	2029	VOP3_TILED_8X8_FMT_YUV420SP_10 : VOP3_TILED_4X4_FMT_YUV420SP_10;
1446		- case DRM_FORMAT_NV16_10:
	2030	+ case DRM_FORMAT_NV20:
1447	2031	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1448	2032	VOP3_TILED_8X8_FMT_YUV422SP_10 : VOP3_TILED_4X4_FMT_YUV422SP_10;
1449		- case DRM_FORMAT_NV24_10:
	2033	+ case DRM_FORMAT_NV30:
1450	2034	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1451	2035	VOP3_TILED_8X8_FMT_YUV444SP_10 : VOP3_TILED_4X4_FMT_YUV444SP_10;
1452	2036	default:
..	..	@@ -1485,6 +2069,8 @@
1485	2069	static bool vop2_win_rb_swap(uint32_t format)
1486	2070	{
1487	2071	switch (format) {
	2072	+ case DRM_FORMAT_XBGR2101010:
	2073	+ case DRM_FORMAT_ABGR2101010:
1488	2074	case DRM_FORMAT_XBGR8888:
1489	2075	case DRM_FORMAT_ABGR8888:
1490	2076	case DRM_FORMAT_BGR888:
..	..	@@ -1499,7 +2085,7 @@
1499	2085	{
1500	2086	switch (format) {
1501	2087	case DRM_FORMAT_NV24:
1502		- case DRM_FORMAT_NV24_10:
	2088	+ case DRM_FORMAT_NV30:
1503	2089	return true;
1504	2090	default:
1505	2091	return false;
..	..	@@ -1512,8 +2098,9 @@
1512	2098	case DRM_FORMAT_NV12:
1513	2099	case DRM_FORMAT_NV16:
1514	2100	case DRM_FORMAT_YUYV:
1515		- case DRM_FORMAT_NV12_10:
1516		- case DRM_FORMAT_NV16_10:
	2101	+ case DRM_FORMAT_Y210:
	2102	+ case DRM_FORMAT_YUV420_8BIT:
	2103	+ case DRM_FORMAT_YUV420_10BIT:
1517	2104	return true;
1518	2105	default:
1519	2106	return false;
..	..	@@ -1526,9 +2113,9 @@
1526	2113	case DRM_FORMAT_NV12:
1527	2114	case DRM_FORMAT_NV16:
1528	2115	case DRM_FORMAT_NV24:
1529		- case DRM_FORMAT_NV12_10:
1530		- case DRM_FORMAT_NV16_10:
1531		- case DRM_FORMAT_NV24_10:
	2116	+ case DRM_FORMAT_NV15:
	2117	+ case DRM_FORMAT_NV20:
	2118	+ case DRM_FORMAT_NV30:
1532	2119	case DRM_FORMAT_YUYV:
1533	2120	case DRM_FORMAT_UYVY:
1534	2121	return true;
..	..	@@ -1572,6 +2159,19 @@
1572	2159	return false;
1573	2160	}
1574	2161
	2162	+static bool vop3_output_rb_swap(uint32_t bus_format, uint32_t output_mode)
	2163	+{
	2164	+ /*
	2165	+ * The default component order of serial rgb3x8 formats
	2166	+ * is BGR. So it is needed to enable RB swap.
	2167	+ */
	2168	+ if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 \|\|
	2169	+ bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
	2170	+ return true;
	2171	+ else
	2172	+ return false;
	2173	+}
	2174	+
1575	2175	static bool vop2_output_yc_swap(uint32_t bus_format)
1576	2176	{
1577	2177	switch (bus_format) {
..	..	@@ -1590,6 +2190,7 @@
1590	2190	switch (bus_format) {
1591	2191	case MEDIA_BUS_FMT_YUV8_1X24:
1592	2192	case MEDIA_BUS_FMT_YUV10_1X30:
	2193	+ case MEDIA_BUS_FMT_YUYV10_1X20:
1593	2194	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1594	2195	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1595	2196	case MEDIA_BUS_FMT_YUYV8_2X8:
..	..	@@ -1685,6 +2286,15 @@
1685	2286	return (win->feature & WIN_FEATURE_CLUSTER_SUB);
1686	2287	}
1687	2288
	2289	+static inline bool vop2_has_feature(struct vop2 *vop2, uint64_t feature)
	2290	+{
	2291	+ return (vop2->data->feature & feature);
	2292	+}
	2293	+
	2294	+/*
	2295	+ * 0: Full mode, 16 lines for one tail
	2296	+ * 1: half block mode
	2297	+ */
1688	2298	static int vop2_afbc_half_block_enable(struct vop2_plane_state *vpstate)
1689	2299	{
1690	2300	if (vpstate->rotate_270_en \|\| vpstate->rotate_90_en)
..	..	@@ -1693,11 +2303,15 @@
1693	2303	return 1;
1694	2304	}
1695	2305
1696		-static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate)
	2306	+/*
	2307	+ * @xoffset: the src x offset of the right win in splice mode, other wise it
	2308	+ * must be zero.
	2309	+ */
	2310	+static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate, int xoffset)
1697	2311	{
1698	2312	struct drm_rect *src = &vpstate->src;
1699	2313	struct drm_framebuffer *fb = vpstate->base.fb;
1700		- uint32_t bpp = fb->format->bpp[0];
	2314	+ uint32_t bpp = rockchip_drm_get_bpp(fb->format);
1701	2315	uint32_t vir_width = (fb->pitches[0] << 3) / (bpp ? bpp : 1);
1702	2316	uint32_t width = drm_rect_width(src) >> 16;
1703	2317	uint32_t height = drm_rect_height(src) >> 16;
..	..	@@ -1713,6 +2327,7 @@
1713	2327	uint8_t top_crop_line_num = 0;
1714	2328	uint8_t bottom_crop_line_num = 0;
1715	2329
	2330	+ act_xoffset += xoffset;
1716	2331	/* 16 pixel align */
1717	2332	if (height & 0xf)
1718	2333	align16_crop = 16 - (height & 0xf);
..	..	@@ -1864,7 +2479,7 @@
1864	2479	#define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \
1865	2480	(fac * (dst - 1) >> 16 < (src - 1))
1866	2481	#define VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac) \
1867		- (fac * (dst - 1) >> 16 <= (src - 1))
	2482	+ (fac * (dst - 1) >> 16 < (src - 1))
1868	2483
1869	2484	static uint16_t vop2_scale_factor(enum scale_mode mode,
1870	2485	int32_t filter_mode,
..	..	@@ -1956,12 +2571,12 @@
1956	2571	{
1957	2572	const struct vop2_data *vop2_data = vop2->data;
1958	2573	const struct vop2_win_data *win_data = &vop2_data->win[win->win_id];
1959		- const struct drm_format_info *info;
1960	2574	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
1961	2575	struct drm_framebuffer *fb = pstate->fb;
1962	2576	uint32_t pixel_format = fb->format->format;
1963		- int hsub = drm_format_horz_chroma_subsampling(pixel_format);
1964		- int vsub = drm_format_vert_chroma_subsampling(pixel_format);
	2577	+ const struct drm_format_info *info = drm_format_info(pixel_format);
	2578	+ uint8_t hsub = info->hsub;
	2579	+ uint8_t vsub = info->vsub;
1965	2580	uint16_t cbcr_src_w = src_w / hsub;
1966	2581	uint16_t cbcr_src_h = src_h / vsub;
1967	2582	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
..	..	@@ -1970,8 +2585,6 @@
1970	2585	uint8_t xgt2 = 0, xgt4 = 0;
1971	2586	uint8_t ygt2 = 0, ygt4 = 0;
1972	2587	uint32_t val;
1973		-
1974		- info = drm_format_info(pixel_format);
1975	2588
1976	2589	if (is_vop3(vop2)) {
1977	2590	if (src_w >= (4 * dst_w)) {
..	..	@@ -1983,12 +2596,30 @@
1983	2596	}
1984	2597	}
1985	2598
1986		- if (src_h >= (4 * dst_h)) {
1987		- ygt4 = 1;
1988		- src_h >>= 2;
1989		- } else if (src_h >= (2 * dst_h)) {
1990		- ygt2 = 1;
1991		- src_h >>= 1;
	2599	+ /**
	2600	+ * The rk3528 is processed as 2 pixel/cycle,
	2601	+ * so ygt2/ygt4 needs to be triggered in advance to improve performance
	2602	+ * when src_w is bigger than 1920.
	2603	+ * dst_h / src_h is at [1, 0.65) ygt2=0; ygt4=0;
	2604	+ * dst_h / src_h is at [0.65, 0.35) ygt2=1; ygt4=0;
	2605	+ * dst_h / src_h is at [0.35, 0) ygt2=0; ygt4=1;
	2606	+ */
	2607	+ if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) {
	2608	+ if (src_h >= (100 * dst_h / 35)) {
	2609	+ ygt4 = 1;
	2610	+ src_h >>= 2;
	2611	+ } else if ((src_h >= 100 * dst_h / 65) && (src_h < 100 * dst_h / 35)) {
	2612	+ ygt2 = 1;
	2613	+ src_h >>= 1;
	2614	+ }
	2615	+ } else {
	2616	+ if (src_h >= (4 * dst_h)) {
	2617	+ ygt4 = 1;
	2618	+ src_h >>= 2;
	2619	+ } else if (src_h >= (2 * dst_h)) {
	2620	+ ygt2 = 1;
	2621	+ src_h >>= 1;
	2622	+ }
1992	2623	}
1993	2624
1994	2625	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
..	..	@@ -2065,10 +2696,17 @@
2065	2696	if (!is_vop3(vop2) \|\|
2066	2697	(!vpstate->afbc_en && !vpstate->tiled_en) \|\|
2067	2698	win_data->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) {
2068		- if (cbcr_src_h >= (4 * dst_h))
2069		- ygt4 = 1;
2070		- else if (cbcr_src_h >= (2 * dst_h))
2071		- ygt2 = 1;
	2699	+ if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) {
	2700	+ if (cbcr_src_h >= (100 * dst_h / 35))
	2701	+ ygt4 = 1;
	2702	+ else if ((cbcr_src_h >= 100 * dst_h / 65) && (cbcr_src_h < 100 * dst_h / 35))
	2703	+ ygt2 = 1;
	2704	+ } else {
	2705	+ if (cbcr_src_h >= (4 * dst_h))
	2706	+ ygt4 = 1;
	2707	+ else if (cbcr_src_h >= (2 * dst_h))
	2708	+ ygt2 = 1;
	2709	+ }
2072	2710
2073	2711	if (ygt4)
2074	2712	cbcr_src_h >>= 2;
..	..	@@ -2166,7 +2804,7 @@
2166	2804	for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
2167	2805	win = vop2_find_win_by_phys_id(vop2, phys_id);
2168	2806	need_wait_win_disabled \|= VOP_WIN_GET(vop2, win, enable);
2169		- vop2_win_disable(win);
	2807	+ vop2_win_disable(win, false);
2170	2808	}
2171	2809
2172	2810	if (need_wait_win_disabled) {
..	..	@@ -2215,7 +2853,7 @@
2215	2853	struct vop2_plane_state *vpstate)
2216	2854	{
2217	2855	struct drm_plane_state *pstate = &vpstate->base;
2218		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
	2856	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->rockchip_crtc.crtc.state);
2219	2857	int is_input_yuv = pstate->fb->format->is_yuv;
2220	2858	int is_output_yuv = vcstate->yuv_overlay;
2221	2859	int input_csc = vpstate->color_space;
..	..	@@ -2230,29 +2868,49 @@
2230	2868	vpstate->r2y_en = 0;
2231	2869	vpstate->csc_mode = 0;
2232	2870
2233		- /* hdr2sdr and sdr2hdr will do csc itself */
2234		- if (vpstate->hdr2sdr_en) {
2235		- /*
2236		- * This is hdr2sdr enabled plane
2237		- * If it's RGB layer do hdr2sdr, we need to do r2y before send to hdr2sdr,
2238		- * because hdr2sdr only support yuv input.
2239		- */
2240		- if (!is_input_yuv) {
2241		- vpstate->r2y_en = 1;
2242		- vpstate->csc_mode = vop2_convert_csc_mode(output_csc, CSC_10BIT_DEPTH);
	2871	+ if (is_vop3(vp->vop2)) {
	2872	+ if (vpstate->hdr_in) {
	2873	+ if (is_input_yuv) {
	2874	+ vpstate->y2r_en = 1;
	2875	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2876	+ CSC_13BIT_DEPTH);
	2877	+ }
	2878	+ return;
	2879	+ } else if (vp->sdr2hdr_en) {
	2880	+ if (is_input_yuv) {
	2881	+ vpstate->y2r_en = 1;
	2882	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2883	+ csc_y2r_bit_depth);
	2884	+ }
	2885	+ return;
2243	2886	}
2244		- return;
2245		- } else if (!vpstate->hdr_in && vp->sdr2hdr_en) {
2246		- /*
2247		- * This is sdr2hdr enabled plane
2248		- * If it's YUV layer do sdr2hdr, we need to do y2r before send to sdr2hdr,
2249		- * because sdr2hdr only support rgb input.
2250		- */
2251		- if (is_input_yuv) {
2252		- vpstate->y2r_en = 1;
2253		- vpstate->csc_mode = vop2_convert_csc_mode(input_csc, csc_y2r_bit_depth);
	2887	+ } else {
	2888	+ /* hdr2sdr and sdr2hdr will do csc itself */
	2889	+ if (vpstate->hdr2sdr_en) {
	2890	+ /*
	2891	+ * This is hdr2sdr enabled plane
	2892	+ * If it's RGB layer do hdr2sdr, we need to do r2y before send to hdr2sdr,
	2893	+ * because hdr2sdr only support yuv input.
	2894	+ */
	2895	+ if (!is_input_yuv) {
	2896	+ vpstate->r2y_en = 1;
	2897	+ vpstate->csc_mode = vop2_convert_csc_mode(output_csc,
	2898	+ CSC_10BIT_DEPTH);
	2899	+ }
	2900	+ return;
	2901	+ } else if (!vpstate->hdr_in && vp->sdr2hdr_en) {
	2902	+ /*
	2903	+ * This is sdr2hdr enabled plane
	2904	+ * If it's YUV layer do sdr2hdr, we need to do y2r before send to sdr2hdr,
	2905	+ * because sdr2hdr only support rgb input.
	2906	+ */
	2907	+ if (is_input_yuv) {
	2908	+ vpstate->y2r_en = 1;
	2909	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2910	+ csc_y2r_bit_depth);
	2911	+ }
	2912	+ return;
2254	2913	}
2255		- return;
2256	2914	}
2257	2915
2258	2916	if (is_input_yuv && !is_output_yuv) {
..	..	@@ -2380,8 +3038,14 @@
2380	3038	if (ret < 0)
2381	3039	goto err_disable_hclk;
2382	3040
	3041	+ ret = clk_enable(vop2->pclk);
	3042	+ if (ret < 0)
	3043	+ goto err_disable_aclk;
	3044	+
2383	3045	return 0;
2384	3046
	3047	+err_disable_aclk:
	3048	+ clk_disable(vop2->aclk);
2385	3049	err_disable_hclk:
2386	3050	clk_disable(vop2->hclk);
2387	3051	return ret;
..	..	@@ -2389,6 +3053,7 @@
2389	3053
2390	3054	static void vop2_core_clks_disable(struct vop2 *vop2)
2391	3055	{
	3056	+ clk_disable(vop2->pclk);
2392	3057	clk_disable(vop2->aclk);
2393	3058	clk_disable(vop2->hclk);
2394	3059	}
..	..	@@ -2499,6 +3164,18 @@
2499	3164	return MODE_OK;
2500	3165	}
2501	3166
	3167	+static inline bool
	3168	+vop2_wb_connector_changed_only(struct drm_crtc_state cstate, struct drm_connector conn)
	3169	+{
	3170	+ struct drm_crtc_state *old_state;
	3171	+ u32 changed_connectors;
	3172	+
	3173	+ old_state = drm_atomic_get_old_crtc_state(cstate->state, cstate->crtc);
	3174	+ changed_connectors = cstate->connector_mask ^ old_state->connector_mask;
	3175	+
	3176	+ return BIT(drm_connector_index(conn)) == changed_connectors;
	3177	+}
	3178	+
2502	3179	static int vop2_wb_encoder_atomic_check(struct drm_encoder *encoder,
2503	3180	struct drm_crtc_state *cstate,
2504	3181	struct drm_connector_state *conn_state)
..	..	@@ -2507,7 +3184,18 @@
2507	3184	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
2508	3185	struct vop2_video_port *vp = to_vop2_video_port(cstate->crtc);
2509	3186	struct drm_framebuffer *fb;
	3187	+ struct drm_gem_object obj, uv_obj;
	3188	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
2510	3189
	3190	+ /*
	3191	+ * No need for a full modested when the only connector changed is the
	3192	+ * writeback connector.
	3193	+ */
	3194	+ if (cstate->connectors_changed &&
	3195	+ vop2_wb_connector_changed_only(cstate, conn_state->connector)) {
	3196	+ cstate->connectors_changed = false;
	3197	+ DRM_DEBUG("VP%d force change connectors_changed to false when only wb changed\n", vp->id);
	3198	+ }
2511	3199	if (!conn_state->writeback_job \|\| !conn_state->writeback_job->fb)
2512	3200	return 0;
2513	3201
..	..	@@ -2520,7 +3208,7 @@
2520	3208	}
2521	3209
2522	3210	if ((fb->width > cstate->mode.hdisplay) \|\|
2523		- ((fb->height != cstate->mode.vdisplay) &&
	3211	+ ((fb->height < cstate->mode.vdisplay) &&
2524	3212	(fb->height != (cstate->mode.vdisplay >> 1)))) {
2525	3213	DRM_DEBUG_KMS("Invalid framebuffer size %ux%u, Only support x scale down and 1/2 y scale down\n",
2526	3214	fb->width, fb->height);
..	..	@@ -2528,7 +3216,7 @@
2528	3216	}
2529	3217
2530	3218	wb_state->scale_x_factor = vop2_scale_factor(SCALE_DOWN, VOP2_SCALE_DOWN_BIL,
2531		- cstate->mode.hdisplay, fb->width);
	3219	+ cstate->mode.hdisplay, fb->width);
2532	3220	wb_state->scale_x_en = (fb->width < cstate->mode.hdisplay) ? 1 : 0;
2533	3221	wb_state->scale_y_en = (fb->height < cstate->mode.vdisplay) ? 1 : 0;
2534	3222
..	..	@@ -2543,22 +3231,35 @@
2543	3231	}
2544	3232
2545	3233	wb_state->vp_id = vp->id;
2546		- wb_state->yrgb_addr = rockchip_fb_get_dma_addr(fb, 0);
2547		- /*
2548		- * uv address must follow yrgb address without gap.
2549		- * the fb->offsets is include stride, so we should
2550		- * not use it.
2551		- */
	3234	+ obj = fb->obj[0];
	3235	+ rk_obj = to_rockchip_obj(obj);
	3236	+ wb_state->yrgb_addr = rk_obj->dma_addr + fb->offsets[0];
	3237	+
2552	3238	if (fb->format->is_yuv) {
2553		- wb_state->uv_addr = wb_state->yrgb_addr;
2554		- wb_state->uv_addr += DIV_ROUND_UP(fb->width * fb->format->bpp[0], 8) * fb->height;
	3239	+ uv_obj = fb->obj[1];
	3240	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	3241	+
	3242	+ wb_state->uv_addr = rk_uv_obj->dma_addr + fb->offsets[1];
2555	3243	}
2556	3244
2557	3245	return 0;
2558	3246	}
2559	3247
	3248	+static void vop2_wb_encoder_atomic_disable(struct drm_encoder *encoder,
	3249	+ struct drm_atomic_state *state)
	3250	+{
	3251	+ struct drm_crtc *crtc = encoder->crtc;
	3252	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	3253	+
	3254	+ if (!crtc->state->active_changed && !crtc->state->mode_changed) {
	3255	+ crtc->state->connectors_changed = false;
	3256	+ DRM_DEBUG("VP%d force change connectors_changed to false when disable wb\n", vp->id);
	3257	+ }
	3258	+}
	3259	+
2560	3260	static const struct drm_encoder_helper_funcs vop2_wb_encoder_helper_funcs = {
2561	3261	.atomic_check = vop2_wb_encoder_atomic_check,
	3262	+ .atomic_disable = vop2_wb_encoder_atomic_disable,
2562	3263	};
2563	3264
2564	3265	static const struct drm_connector_helper_funcs vop2_wb_connector_helper_funcs = {
..	..	@@ -2641,10 +3342,12 @@
2641	3342	if (conn_state->writeback_job && conn_state->writeback_job->fb) {
2642	3343	struct drm_framebuffer *fb = conn_state->writeback_job->fb;
2643	3344
2644		- DRM_DEV_DEBUG(vop2->dev, "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
2645		- fb->width, fb->height, wb_state->format, fb->pitches[0], &wb_state->yrgb_addr);
	3345	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_WB,
	3346	+ "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
	3347	+ fb->width, fb->height, wb_state->format,
	3348	+ fb->pitches[0], &wb_state->yrgb_addr);
2646	3349
2647		- drm_writeback_queue_job(wb_conn, conn_state->writeback_job);
	3350	+ drm_writeback_queue_job(wb_conn, conn_state);
2648	3351	conn_state->writeback_job = NULL;
2649	3352
2650	3353	spin_lock_irqsave(&wb->job_lock, flags);
..	..	@@ -2657,7 +3360,7 @@
2657	3360	fifo_throd = fb->pitches[0] >> 4;
2658	3361	if (fifo_throd >= vop2->data->wb->fifo_depth)
2659	3362	fifo_throd = vop2->data->wb->fifo_depth;
2660		- r2y = fb->format->is_yuv && (!is_yuv_output(vcstate->bus_format));
	3363	+ r2y = !vcstate->yuv_overlay && fb->format->is_yuv;
2661	3364
2662	3365	/*
2663	3366	* the vp_id register config done immediately
..	..	@@ -2673,6 +3376,7 @@
2673	3376	VOP_MODULE_SET(vop2, wb, r2y_en, r2y);
2674	3377	VOP_MODULE_SET(vop2, wb, enable, 1);
2675	3378	vop2_wb_irqs_enable(vop2);
	3379	+ VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 1);
2676	3380	}
2677	3381	}
2678	3382
..	..	@@ -2697,6 +3401,7 @@
2697	3401
2698	3402	return;
2699	3403	}
	3404	+
2700	3405	spin_lock(&vop2->reg_lock);
2701	3406	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 0);
2702	3407	vop2_cfg_done(crtc);
..	..	@@ -2712,8 +3417,7 @@
2712	3417	spin_lock(&vop2->reg_lock);
2713	3418
2714	3419	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
2715		- VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
2716		- vop2_cfg_done(crtc);
	3420	+ vop2_write_reg_uncached(vop2, &vp->regs->gamma_update_en, 1);
2717	3421	vp->gamma_lut_active = true;
2718	3422
2719	3423	spin_unlock(&vop2->reg_lock);
..	..	@@ -2733,7 +3437,7 @@
2733	3437	vop2_write_lut(vop2, i << 2, lut[i]);
2734	3438
2735	3439	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
2736		- VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
	3440	+ vop2_write_reg_uncached(vop2, &vp->regs->gamma_update_en, 1);
2737	3441	vp->gamma_lut_active = true;
2738	3442
2739	3443	spin_unlock(&vop2->reg_lock);
..	..	@@ -2753,27 +3457,14 @@
2753	3457	if (vop2->version == VOP_VERSION_RK3568) {
2754	3458	rk3568_crtc_load_lut(crtc);
2755	3459	} else {
2756		- rk3588_crtc_load_lut(crtc, vp->lut);
2757		- vop2_cfg_done(crtc);
	3460	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	3461	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	3462	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	3463	+
	3464	+ rk3588_crtc_load_lut(&vp->rockchip_crtc.crtc, vp->lut);
	3465	+ if (vcstate->splice_mode)
	3466	+ rk3588_crtc_load_lut(&splice_vp->rockchip_crtc.crtc, vp->lut);
2758	3467	}
2759		- /*
2760		- * maybe appear the following case:
2761		- * -> set gamma
2762		- * -> config done
2763		- * -> atomic commit
2764		- * --> update win format
2765		- * --> update win address
2766		- * ---> here maybe meet vop hardware frame start, and triggle some config take affect.
2767		- * ---> as only some config take affect, this maybe lead to iommu pagefault.
2768		- * --> update win size
2769		- * --> update win other parameters
2770		- * -> config done
2771		- *
2772		- * so we add vop2_wait_for_fs_by_done_bit_status() to make sure the first config done take
2773		- * effect and then to do next frame config.
2774		- */
2775		- if (VOP_MODULE_GET(vop2, vp, standby) == 0)
2776		- vop2_wait_for_fs_by_done_bit_status(vp);
2777	3468	}
2778	3469
2779	3470	static void rockchip_vop2_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red,
..	..	@@ -2815,6 +3506,7 @@
2815	3506	struct drm_modeset_acquire_ctx *ctx)
2816	3507	{
2817	3508	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	3509	+ struct vop2 *vop2 = vp->vop2;
2818	3510	int i;
2819	3511
2820	3512	if (!vp->lut)
..	..	@@ -2829,6 +3521,25 @@
2829	3521	rockchip_vop2_crtc_fb_gamma_set(crtc, red[i], green[i],
2830	3522	blue[i], i);
2831	3523	vop2_crtc_load_lut(crtc);
	3524	+ vop2_cfg_done(crtc);
	3525	+ /*
	3526	+ * maybe appear the following case:
	3527	+ * -> set gamma
	3528	+ * -> config done
	3529	+ * -> atomic commit
	3530	+ * --> update win format
	3531	+ * --> update win address
	3532	+ * ---> here maybe meet vop hardware frame start, and triggle some config take affect.
	3533	+ * ---> as only some config take affect, this maybe lead to iommu pagefault.
	3534	+ * --> update win size
	3535	+ * --> update win other parameters
	3536	+ * -> config done
	3537	+ *
	3538	+ * so we add vop2_wait_for_fs_by_done_bit_status() to make sure the first config done take
	3539	+ * effect and then to do next frame config.
	3540	+ */
	3541	+ if (VOP_MODULE_GET(vop2, vp, standby) == 0)
	3542	+ vop2_wait_for_fs_by_done_bit_status(vp);
2832	3543
2833	3544	return 0;
2834	3545	}
..	..	@@ -2851,6 +3562,7 @@
2851	3562	static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
2852	3563	struct drm_crtc_state *old_state)
2853	3564	{
	3565	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
2854	3566	struct vop2_video_port *vp = to_vop2_video_port(crtc);
2855	3567	struct rockchip_drm_private *private = crtc->dev->dev_private;
2856	3568	struct drm_color_lut *lut = vp->cubic_lut;
..	..	@@ -2901,12 +3613,51 @@
2901	3613	*cubic_lut_kvaddr = 0;
2902	3614	}
2903	3615
	3616	+ VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid);
2904	3617	VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
2905	3618	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 1);
2906	3619	VOP_MODULE_SET(vop2, vp, cubic_lut_en, 1);
2907	3620	VOP_CTRL_SET(vop2, lut_dma_en, 1);
2908	3621
	3622	+ if (vcstate->splice_mode) {
	3623	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	3624	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	3625	+
	3626	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_mst, cubic_lut_mst);
	3627	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_update_en, 1);
	3628	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_en, 1);
	3629	+ }
	3630	+
2909	3631	return 0;
	3632	+}
	3633	+
	3634	+static void vop2_attach_cubic_lut_prop(struct drm_crtc *crtc, unsigned int cubic_lut_size)
	3635	+{
	3636	+ struct rockchip_drm_private *private = crtc->dev->dev_private;
	3637	+
	3638	+ drm_object_attach_property(&crtc->base, private->cubic_lut_prop, 0);
	3639	+ drm_object_attach_property(&crtc->base, private->cubic_lut_size_prop, cubic_lut_size);
	3640	+}
	3641	+
	3642	+static void vop2_cubic_lut_init(struct vop2 *vop2)
	3643	+{
	3644	+ const struct vop2_data *vop2_data = vop2->data;
	3645	+ const struct vop2_video_port_data *vp_data;
	3646	+ struct vop2_video_port *vp;
	3647	+ struct drm_crtc *crtc;
	3648	+ int i;
	3649	+
	3650	+ for (i = 0; i < vop2_data->nr_vps; i++) {
	3651	+ vp = &vop2->vps[i];
	3652	+ crtc = &vp->rockchip_crtc.crtc;
	3653	+ if (!crtc->dev)
	3654	+ continue;
	3655	+ vp_data = &vop2_data->vp[vp->id];
	3656	+ vp->cubic_lut_len = vp_data->cubic_lut_len;
	3657	+
	3658	+ if (vp->cubic_lut_len)
	3659	+ vop2_attach_cubic_lut_prop(crtc, vp->cubic_lut_len);
	3660	+ }
2910	3661	}
2911	3662
2912	3663	static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
..	..	@@ -2925,7 +3676,15 @@
2925	3676	goto err;
2926	3677	}
2927	3678
	3679	+ ret = clk_prepare_enable(vop2->pclk);
	3680	+ if (ret < 0) {
	3681	+ dev_err(vop2->dev, "failed to enable pclk - %d\n", ret);
	3682	+ goto err1;
	3683	+ }
	3684	+
2928	3685	return 0;
	3686	+err1:
	3687	+ clk_disable_unprepare(vop2->aclk);
2929	3688	err:
2930	3689	clk_disable_unprepare(vop2->hclk);
2931	3690
..	..	@@ -2963,25 +3722,16 @@
2963	3722	*/
2964	3723	static void vop3_layer_map_initial(struct vop2 *vop2, uint32_t current_vp_id)
2965	3724	{
2966		- struct vop2_video_port *vp;
2967		- struct vop2_win *win;
2968		- unsigned long win_mask;
2969	3725	uint16_t vp_id;
2970		- int phys_id;
2971		- int i;
	3726	+ struct drm_plane *plane = NULL;
2972	3727
2973		- for (i = 0; i < vop2->data->nr_vps; i++) {
2974		- vp_id = i;
2975		- vp = &vop2->vps[vp_id];
2976		- vp->win_mask = vp->plane_mask;
2977		- win_mask = vp->win_mask;
2978		- for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
2979		- win = vop2_find_win_by_phys_id(vop2, phys_id);
2980		- VOP_CTRL_SET(vop2, win_vp_id[phys_id], vp_id);
2981		- win->vp_mask = BIT(vp_id);
2982		- win->old_vp_mask = win->vp_mask;
2983		- DRM_DEV_DEBUG(vop2->dev, "%s attach to vp%d\n", win->name, vp_id);
2984		- }
	3728	+ drm_for_each_plane(plane, vop2->drm_dev) {
	3729	+ struct vop2_win *win = to_vop2_win(plane);
	3730	+
	3731	+ vp_id = VOP_CTRL_GET(vop2, win_vp_id[win->phys_id]);
	3732	+ win->vp_mask = BIT(vp_id);
	3733	+ win->old_vp_mask = win->vp_mask;
	3734	+ vop2->vps[vp_id].win_mask \|= BIT(win->phys_id);
2985	3735	}
2986	3736	}
2987	3737
..	..	@@ -3051,6 +3801,18 @@
3051	3801
3052	3802	}
3053	3803
	3804	+static void rk3588_vop2_regsbak(struct vop2 *vop2)
	3805	+{
	3806	+ uint32_t *base = vop2->regs;
	3807	+ int i;
	3808	+
	3809	+ /*
	3810	+ * No need to backup DSC/GAMMA_LUT/BPP_LUT/MMU
	3811	+ */
	3812	+ for (i = 0; i < (0x2000 >> 2); i++)
	3813	+ vop2->regsbak[i] = base[i];
	3814	+}
	3815	+
3054	3816	static void vop2_initial(struct drm_crtc *crtc)
3055	3817	{
3056	3818	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -3075,14 +3837,29 @@
3075	3837	if (vop2_soc_is_rk3566())
3076	3838	VOP_CTRL_SET(vop2, otp_en, 1);
3077	3839
3078		- memcpy(vop2->regsbak, vop2->regs, vop2->len);
	3840	+ /*
	3841	+ * rk3588 don't support access mmio by memcpy
	3842	+ */
	3843	+ if (vop2->version == VOP_VERSION_RK3588)
	3844	+ rk3588_vop2_regsbak(vop2);
	3845	+ else
	3846	+ memcpy(vop2->regsbak, vop2->regs, vop2->len);
3079	3847
3080	3848	VOP_MODULE_SET(vop2, wb, axi_yrgb_id, 0xd);
3081	3849	VOP_MODULE_SET(vop2, wb, axi_uv_id, 0xe);
3082	3850	vop2_wb_cfg_done(vp);
3083	3851
3084		- if (is_vop3(vop2))
3085		- VOP_CTRL_SET(vop2, esmart_lb_mode, vop2->data->esmart_lb_mode);
	3852	+ if (is_vop3(vop2)) {
	3853	+ VOP_CTRL_SET(vop2, dsp_vs_t_sel, 0);
	3854	+ VOP_CTRL_SET(vop2, esmart_lb_mode, vop2->esmart_lb_mode);
	3855	+ }
	3856	+
	3857	+ /*
	3858	+ * This is unused and error init value for rk3528/rk3562 vp1, if less of this config,
	3859	+ * vp1 can't display normally.
	3860	+ */
	3861	+ if (vop2->version == VOP_VERSION_RK3528 \|\| vop2->version == VOP_VERSION_RK3562)
	3862	+ vop2_mask_write(vop2, 0x700, 0x3, 4, 0, 0, true);
3086	3863
3087	3864	VOP_CTRL_SET(vop2, cfg_done_en, 1);
3088	3865	/*
..	..	@@ -3092,6 +3869,7 @@
3092	3869	VOP_CTRL_SET(vop2, auto_gating_en, 0);
3093	3870
3094	3871	VOP_CTRL_SET(vop2, aclk_pre_auto_gating_en, 0);
	3872	+
3095	3873	/*
3096	3874	* Register OVERLAY_LAYER_SEL and OVERLAY_PORT_SEL should take effect immediately,
3097	3875	* than windows configuration(CLUSTER/ESMART/SMART) can take effect according the
..	..	@@ -3104,9 +3882,17 @@
3104	3882	*/
3105	3883	VOP_CTRL_SET(vop2, if_ctrl_cfg_done_imd, 1);
3106	3884
	3885	+ /* Close dynamic turn on/off rk3588 PD_ESMART and keep esmart pd on when enable */
	3886	+ if (vop2->version == VOP_VERSION_RK3588) {
	3887	+ struct vop2_power_domain *esmart_pd = vop2_find_pd_by_id(vop2, VOP2_PD_ESMART);
	3888	+
	3889	+ if (vop2_power_domain_status(esmart_pd))
	3890	+ esmart_pd->on = true;
	3891	+ else
	3892	+ vop2_power_domain_on(esmart_pd);
	3893	+ }
3107	3894	vop2_layer_map_initial(vop2, current_vp_id);
3108	3895	vop2_axi_irqs_enable(vop2);
3109		-
3110	3896	vop2->is_enabled = true;
3111	3897	}
3112	3898
..	..	@@ -3120,6 +3906,93 @@
3120	3906	vp->id, ret);
3121	3907	}
3122	3908
	3909	+/*
	3910	+ * The internal PD of VOP2 on rk3588 take effect immediately
	3911	+ * for power up and take effect by vsync for power down.
	3912	+ *
	3913	+ * And the PD_CLUSTER0 is a parent PD of PD_CLUSTER1/2/3,
	3914	+ * we may have this use case:
	3915	+ * Cluster0 is attached to VP0 for HDMI output,
	3916	+ * Cluster1 is attached to VP1 for MIPI DSI,
	3917	+
	3918	+ * When we enable Cluster1 on VP1, we should enable PD_CLUSTER0 as
	3919	+ * it is the parent PD, event though HDMI is plugout, VP1 is disabled,
	3920	+ * the PD of Cluster0 should keep power on.
	3921	+
	3922	+ * When system go to suspend:
	3923	+ * (1) Power down PD of Cluster1 before VP1 standby(the power down is take
	3924	+ * effect by vsync)
	3925	+ * (2) Power down PD of Cluster0
	3926	+ *
	3927	+ * But we have problem at step (2), Cluster0 is attached to VP0. but VP0
	3928	+ * is in standby mode, as it is never used or hdmi plugout. So there is
	3929	+ * no vsync, the power down will never take effect.
	3930	+
	3931	+ * According to IC designer: We must power down all internal PD of VOP
	3932	+ * before we power down the global PD_VOP.
	3933	+
	3934	+ * So we get this workaround:
	3935	+ * If we found a VP is in standby mode when we want power down a PD is
	3936	+ * attached to it, we release the VP from standby mode, than it will
	3937	+ * run a default timing and generate vsync. Than we can power down the
	3938	+ * PD by this vsync. After all this is done, we standby the VP at last.
	3939	+ */
	3940	+static void vop2_power_domain_off_by_disabled_vp(struct vop2_power_domain *pd)
	3941	+{
	3942	+ struct vop2_video_port *vp = NULL;
	3943	+ struct vop2 *vop2 = pd->vop2;
	3944	+ struct vop2_win *win;
	3945	+ struct drm_crtc *crtc;
	3946	+ uint32_t vp_id;
	3947	+ uint8_t phys_id;
	3948	+ int ret;
	3949	+
	3950	+ if (pd->data->id == VOP2_PD_CLUSTER0 \|\| pd->data->id == VOP2_PD_CLUSTER1 \|\|
	3951	+ pd->data->id == VOP2_PD_CLUSTER2 \|\| pd->data->id == VOP2_PD_CLUSTER3 \|\|
	3952	+ pd->data->id == VOP2_PD_ESMART) {
	3953	+ phys_id = ffs(pd->data->module_id_mask) - 1;
	3954	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	3955	+ vp_id = ffs(win->vp_mask) - 1;
	3956	+ vp = &vop2->vps[vp_id];
	3957	+ } else {
	3958	+ DRM_DEV_ERROR(vop2->dev, "unexpected power on pd%d\n", ffs(pd->data->id) - 1);
	3959	+ }
	3960	+
	3961	+ if (vp) {
	3962	+ ret = clk_prepare_enable(vp->dclk);
	3963	+ if (ret < 0)
	3964	+ DRM_DEV_ERROR(vop2->dev, "failed to enable dclk for video port%d - %d\n",
	3965	+ vp->id, ret);
	3966	+ crtc = &vp->rockchip_crtc.crtc;
	3967	+ VOP_MODULE_SET(vop2, vp, standby, 0);
	3968	+ vop2_power_domain_off(pd);
	3969	+ vop2_cfg_done(crtc);
	3970	+ vop2_wait_power_domain_off(pd);
	3971	+
	3972	+ reinit_completion(&vp->dsp_hold_completion);
	3973	+ vop2_dsp_hold_valid_irq_enable(crtc);
	3974	+ VOP_MODULE_SET(vop2, vp, standby, 1);
	3975	+ ret = wait_for_completion_timeout(&vp->dsp_hold_completion, msecs_to_jiffies(50));
	3976	+ if (!ret)
	3977	+ DRM_DEV_INFO(vop2->dev, "wait for vp%d dsp_hold timeout\n", vp->id);
	3978	+
	3979	+ vop2_dsp_hold_valid_irq_disable(crtc);
	3980	+ clk_disable_unprepare(vp->dclk);
	3981	+ }
	3982	+}
	3983	+
	3984	+static void vop2_power_off_all_pd(struct vop2 *vop2)
	3985	+{
	3986	+ struct vop2_power_domain pd, n;
	3987	+
	3988	+ list_for_each_entry_safe_reverse(pd, n, &vop2->pd_list_head, list) {
	3989	+ if (vop2_power_domain_status(pd))
	3990	+ vop2_power_domain_off_by_disabled_vp(pd);
	3991	+ pd->on = false;
	3992	+ pd->vp_mask = 0;
	3993	+ }
	3994	+}
	3995	+
3123	3996	static void vop2_disable(struct drm_crtc *crtc)
3124	3997	{
3125	3998	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -3130,7 +4003,6 @@
3130	4003	if (--vop2->enable_count > 0)
3131	4004	return;
3132	4005
3133		- vop2->is_enabled = false;
3134	4006	if (vop2->is_iommu_enabled) {
3135	4007	/*
3136	4008	* vop2 standby complete, so iommu detach is safe.
..	..	@@ -3139,32 +4011,455 @@
3139	4011	rockchip_drm_dma_detach_device(vop2->drm_dev, vop2->dev);
3140	4012	vop2->is_iommu_enabled = false;
3141	4013	}
	4014	+ if (vop2->version == VOP_VERSION_RK3588)
	4015	+ vop2_power_off_all_pd(vop2);
3142	4016
	4017	+ vop2->is_enabled = false;
3143	4018	pm_runtime_put_sync(vop2->dev);
3144	4019
	4020	+ clk_disable_unprepare(vop2->pclk);
3145	4021	clk_disable_unprepare(vop2->aclk);
3146	4022	clk_disable_unprepare(vop2->hclk);
	4023	+}
	4024	+
	4025	+static void vop2_crtc_disable_dsc(struct vop2 *vop2, u8 dsc_id)
	4026	+{
	4027	+ struct vop2_dsc *dsc = &vop2->dscs[dsc_id];
	4028	+
	4029	+ VOP_MODULE_SET(vop2, dsc, dsc_mer, 1);
	4030	+ VOP_MODULE_SET(vop2, dsc, dsc_interface_mode, 0);
	4031	+ VOP_MODULE_SET(vop2, dsc, dsc_en, 0);
	4032	+ VOP_MODULE_SET(vop2, dsc, rst_deassert, 0);
	4033	+}
	4034	+
	4035	+static struct vop2_clk vop2_clk_get(struct vop2 vop2, const char *name)
	4036	+{
	4037	+ struct vop2_clk clk, n;
	4038	+
	4039	+ if (!name)
	4040	+ return NULL;
	4041	+
	4042	+ list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
	4043	+ if (!strcmp(clk_hw_get_name(&clk->hw), name))
	4044	+ return clk;
	4045	+ }
	4046	+
	4047	+ return NULL;
	4048	+}
	4049	+
	4050	+static void vop2_clk_set_parent(struct clk clk, struct clk parent)
	4051	+{
	4052	+ int ret = 0;
	4053	+
	4054	+ if (parent)
	4055	+ ret = clk_set_parent(clk, parent);
	4056	+ if (ret < 0)
	4057	+ DRM_WARN("failed to set %s as parent for %s\n",
	4058	+ __clk_get_name(parent), __clk_get_name(clk));
	4059	+}
	4060	+
	4061	+static int vop2_extend_clk_init(struct vop2 *vop2)
	4062	+{
	4063	+ const char * const extend_clk_name[] = {
	4064	+ "hdmi0_phy_pll", "hdmi1_phy_pll"};
	4065	+ struct drm_device *drm_dev = vop2->drm_dev;
	4066	+ struct clk *clk;
	4067	+ struct vop2_extend_pll *extend_pll;
	4068	+ int i;
	4069	+
	4070	+ INIT_LIST_HEAD(&vop2->extend_clk_list_head);
	4071	+
	4072	+ if (vop2->version != VOP_VERSION_RK3588)
	4073	+ return 0;
	4074	+
	4075	+ for (i = 0; i < ARRAY_SIZE(extend_clk_name); i++) {
	4076	+ clk = devm_clk_get_optional(drm_dev->dev, extend_clk_name[i]);
	4077	+ if (IS_ERR(clk)) {
	4078	+ dev_warn(drm_dev->dev, "failed to get %s: %ld\n",
	4079	+ extend_clk_name[i], PTR_ERR(clk));
	4080	+ continue;
	4081	+ }
	4082	+
	4083	+ if (!clk)
	4084	+ continue;
	4085	+
	4086	+ extend_pll = devm_kzalloc(drm_dev->dev, sizeof(*extend_pll), GFP_KERNEL);
	4087	+ if (!extend_pll)
	4088	+ return -ENOMEM;
	4089	+
	4090	+ extend_pll->clk = clk;
	4091	+ extend_pll->vp_mask = 0;
	4092	+ strncpy(extend_pll->clk_name, extend_clk_name[i], sizeof(extend_pll->clk_name));
	4093	+ list_add_tail(&extend_pll->list, &vop2->extend_clk_list_head);
	4094	+ }
	4095	+
	4096	+ return 0;
	4097	+}
	4098	+
	4099	+static struct vop2_extend_pll vop2_extend_clk_find_by_name(struct vop2 vop2, char *clk_name)
	4100	+{
	4101	+ struct vop2_extend_pll *extend_pll;
	4102	+
	4103	+ list_for_each_entry(extend_pll, &vop2->extend_clk_list_head, list) {
	4104	+ if (!strcmp(extend_pll->clk_name, clk_name))
	4105	+ return extend_pll;
	4106	+ }
	4107	+
	4108	+ return NULL;
	4109	+}
	4110	+
	4111	+static int vop2_extend_clk_switch_pll(struct vop2 vop2, struct vop2_extend_pll src,
	4112	+ struct vop2_extend_pll *dst)
	4113	+{
	4114	+ struct vop2_clk *dclk;
	4115	+ u32 vp_mask;
	4116	+ int i = 0;
	4117	+ char clk_name[32];
	4118	+
	4119	+ if (!src->vp_mask)
	4120	+ return -EINVAL;
	4121	+
	4122	+ if (dst->vp_mask)
	4123	+ return -EBUSY;
	4124	+
	4125	+ vp_mask = src->vp_mask;
	4126	+
	4127	+ while (vp_mask) {
	4128	+ if ((BIT(i) & src->vp_mask)) {
	4129	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", i);
	4130	+ dclk = vop2_clk_get(vop2, clk_name);
	4131	+ clk_set_rate(dst->clk, dclk->rate);
	4132	+ vop2_clk_set_parent(vop2->vps[i].dclk, dst->clk);
	4133	+ src->vp_mask &= ~BIT(i);
	4134	+ dst->vp_mask \|= BIT(i);
	4135	+ }
	4136	+ i++;
	4137	+ vp_mask = vp_mask >> 1;
	4138	+ }
	4139	+
	4140	+ return 0;
	4141	+}
	4142	+
	4143	+static inline int vop2_extend_clk_get_vp_id(struct vop2_extend_pll *ext_pll)
	4144	+{
	4145	+ return ffs(ext_pll->vp_mask) - 1;
	4146	+}
	4147	+
	4148	+/*
	4149	+ * Here are 2 hdmi phy pll can use for video port dclk. The strategies of how to use hdmi phy pll
	4150	+ * as follow:
	4151	+ *
	4152	+ * 1. hdmi phy pll can be used for video port0/1/2 when output format under 4K@60Hz;
	4153	+ *
	4154	+ * 2. When a video port connect both hdmi0 and hdmi1(may also connect other output interface),
	4155	+ * it must hold the hdmi0 and hdmi1 phy pll, and other video port can't use it. if request dclk
	4156	+ * is under 4K@60Hz, set the video port dlk parent as hdmi0 phy pll.if hdmi0 or hdmi1 phy pll
	4157	+ * is used by other video port, report a error.
	4158	+ *
	4159	+ * 3. When a video port(A) connect hdmi0(may also connect other output interface but not hdmi1),
	4160	+ * it must hold the hdmi0 phy pll, and other video port can't use it. If both hdmi0 and hdmi1
	4161	+ * phy pll is used by other video port, report a error. If hdmi0 phy pll is used by another
	4162	+ * video port(B) and hdmi1 phy pll is free, set hdmi1 phy pll as video port(B) dclk parent and
	4163	+ * video port(A) hold hdmi0 phy pll. If hdmi0 phy pll is free, video port(A) hold hdmi0 pll.If
	4164	+ * video port(A) hold hdmi0 phy pll and request dclk is under 4k@60Hz, set hdmi0 phy pll as
	4165	+ * video port(A) dclk parent.
	4166	+ *
	4167	+ * 4. When a video port(A) connect hdmi1(may also connect other output interface but not hdmi0),
	4168	+ * it must hold the hdmi1 phy pll, and other video port can't use it. If both hdmi0 and hdmi1
	4169	+ * phy pll is used by other video port, report a error. If hdmi1 phy pll is used by another
	4170	+ * video port(B) and hdmi0 phy pll is free, set hdmi0 phy pll as video port(B) dclk parent and
	4171	+ * video port(A) hold hdmi1 phy pll. If hdmi1 phy pll is free, video port(A) hold hdmi1 pll. If
	4172	+ * video port(A) hold hdmi1 phy pll and request dclk is under 4k@60Hz, set hdmi1 phy pll as
	4173	+ * video port(A) dclk parent.
	4174	+ *
	4175	+ * 5. When a video port connect dp(0, 1, or both, may also connect other output type but not hdmi0
	4176	+ * and hdmi1). If the request dclk is higher than 4K@60Hz or video port id is 2, do nothing.
	4177	+ * Otherwise get a free hdmi phy pll as video port dclk parent. If no free hdmi phy pll can be
	4178	+ * get, report a error.
	4179	+ */
	4180	+
	4181	+static int vop2_clk_set_parent_extend(struct vop2_video_port *vp,
	4182	+ struct rockchip_crtc_state *vcstate, bool enable)
	4183	+{
	4184	+ struct vop2 *vop2 = vp->vop2;
	4185	+ struct vop2_extend_pll hdmi0_phy_pll, hdmi1_phy_pll;
	4186	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	4187	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	4188	+
	4189	+ hdmi0_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
	4190	+ hdmi1_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
	4191	+
	4192	+ if (hdmi0_phy_pll)
	4193	+ clk_get_rate(hdmi0_phy_pll->clk);
	4194	+ if (hdmi1_phy_pll)
	4195	+ clk_get_rate(hdmi1_phy_pll->clk);
	4196	+
	4197	+ if ((!hdmi0_phy_pll && !hdmi1_phy_pll) \|\|
	4198	+ ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) && !hdmi0_phy_pll) \|\|
	4199	+ ((vcstate->output_if & VOP_OUTPUT_IF_HDMI1) && !hdmi1_phy_pll))
	4200	+ return 0;
	4201	+
	4202	+ if (enable) {
	4203	+ if ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4204	+ (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4205	+ if (hdmi0_phy_pll->vp_mask) {
	4206	+ DRM_ERROR("hdmi0 phy pll is used by vp%d\n",
	4207	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll));
	4208	+ return -EBUSY;
	4209	+ }
	4210	+
	4211	+ if (hdmi1_phy_pll->vp_mask) {
	4212	+ DRM_ERROR("hdmi1 phy pll is used by vp%d\n",
	4213	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4214	+ return -EBUSY;
	4215	+ }
	4216	+
	4217	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4218	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4219	+ else
	4220	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4221	+
	4222	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4223	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4224	+ } else if ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4225	+ !(vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4226	+ if (hdmi0_phy_pll->vp_mask) {
	4227	+ if (hdmi1_phy_pll) {
	4228	+ if (hdmi1_phy_pll->vp_mask) {
	4229	+ DRM_ERROR("hdmi0: phy pll is used by vp%d:vp%d\n",
	4230	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll),
	4231	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4232	+ return -EBUSY;
	4233	+ }
	4234	+
	4235	+ vop2_extend_clk_switch_pll(vop2, hdmi0_phy_pll,
	4236	+ hdmi1_phy_pll);
	4237	+ } else {
	4238	+ DRM_ERROR("hdmi0: phy pll is used by vp%d\n",
	4239	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll));
	4240	+ return -EBUSY;
	4241	+ }
	4242	+ }
	4243	+
	4244	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4245	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4246	+ else
	4247	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4248	+
	4249	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4250	+ } else if (!(vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4251	+ (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4252	+ if (hdmi1_phy_pll->vp_mask) {
	4253	+ if (hdmi0_phy_pll) {
	4254	+ if (hdmi0_phy_pll->vp_mask) {
	4255	+ DRM_ERROR("hdmi1: phy pll is used by vp%d:vp%d\n",
	4256	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll),
	4257	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4258	+ return -EBUSY;
	4259	+ }
	4260	+
	4261	+ vop2_extend_clk_switch_pll(vop2, hdmi1_phy_pll,
	4262	+ hdmi0_phy_pll);
	4263	+ } else {
	4264	+ DRM_ERROR("hdmi1: phy pll is used by vp%d\n",
	4265	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4266	+ return -EBUSY;
	4267	+ }
	4268	+ }
	4269	+
	4270	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4271	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4272	+ else
	4273	+ vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
	4274	+
	4275	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4276	+ } else if (output_if_is_dp(vcstate->output_if)) {
	4277	+ if (vp->id == 2) {
	4278	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4279	+ return 0;
	4280	+ }
	4281	+
	4282	+ if (hdmi0_phy_pll && !hdmi0_phy_pll->vp_mask) {
	4283	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4284	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4285	+ } else if (hdmi1_phy_pll && !hdmi1_phy_pll->vp_mask) {
	4286	+ vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
	4287	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4288	+ } else {
	4289	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4290	+ DRM_INFO("No free hdmi phy pll for DP, use default parent\n");
	4291	+ }
	4292	+ }
	4293	+ } else {
	4294	+ if (hdmi0_phy_pll && (BIT(vp->id) & hdmi0_phy_pll->vp_mask))
	4295	+ hdmi0_phy_pll->vp_mask &= ~BIT(vp->id);
	4296	+
	4297	+ if (hdmi1_phy_pll && (BIT(vp->id) & hdmi1_phy_pll->vp_mask))
	4298	+ hdmi1_phy_pll->vp_mask &= ~BIT(vp->id);
	4299	+ }
	4300	+
	4301	+ return 0;
	4302	+}
	4303	+
	4304	+static void vop2_crtc_atomic_enter_psr(struct drm_crtc crtc, struct drm_crtc_state old_state)
	4305	+{
	4306	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4307	+ struct vop2 *vop2 = vp->vop2;
	4308	+ struct vop2_win *win;
	4309	+ unsigned long win_mask = vp->enabled_win_mask;
	4310	+ int phys_id;
	4311	+
	4312	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	4313	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	4314	+ VOP_WIN_SET(vop2, win, enable, 0);
	4315	+
	4316	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN)
	4317	+ VOP_CLUSTER_SET(vop2, win, enable, 0);
	4318	+ }
	4319	+
	4320	+ vop2_cfg_done(crtc);
	4321	+ vop2_wait_for_fs_by_done_bit_status(vp);
	4322	+ drm_crtc_vblank_off(crtc);
	4323	+ if (hweight8(vop2->active_vp_mask) == 1) {
	4324	+ u32 adjust_aclk_rate = 0;
	4325	+ u32 htotal = (VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16) & 0xffff;
	4326	+ u32 pre_scan_dly = VOP_MODULE_GET(vop2, vp, pre_scan_htiming);
	4327	+ u32 pre_scan_hblank = pre_scan_dly & 0x1fff;
	4328	+ u32 pre_scan_hactive = (pre_scan_dly >> 16) & 0x1fff;
	4329	+ u32 dclk_rate = crtc->state->adjusted_mode.crtc_clock / 1000;
	4330	+ /**
	4331	+ * (pre_scan_hblank + pre_scan_hactive) x aclk_margin / adjust_aclk_rate = hotal / dclk_rate
	4332	+ * aclk_margin = 1.2, so
	4333	+ * adjust_aclk_rate = (pre_scan_hblank + pre_scan_hactive) x 1.2 * aclk_margin / htotal
	4334	+ */
	4335	+
	4336	+ adjust_aclk_rate = (pre_scan_hblank + pre_scan_hactive) * dclk_rate * 12 / 10 / htotal;
	4337	+
	4338	+ vop2->aclk_rate = clk_get_rate(vop2->aclk);
	4339	+ clk_set_rate(vop2->aclk, adjust_aclk_rate * 1000000L);
	4340	+ vop2->aclk_rate_reset = true;
	4341	+ }
	4342	+}
	4343	+
	4344	+static void vop2_crtc_atomic_exit_psr(struct drm_crtc crtc, struct drm_crtc_state old_state)
	4345	+{
	4346	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4347	+ struct vop2 *vop2 = vp->vop2;
	4348	+ u32 phys_id;
	4349	+ struct vop2_win *win;
	4350	+ unsigned long enabled_win_mask = vp->enabled_win_mask;
	4351	+
	4352	+ drm_crtc_vblank_on(crtc);
	4353	+ if (vop2->aclk_rate_reset)
	4354	+ clk_set_rate(vop2->aclk, vop2->aclk_rate);
	4355	+ vop2->aclk_rate_reset = false;
	4356	+
	4357	+ for_each_set_bit(phys_id, &enabled_win_mask, ROCKCHIP_MAX_LAYER) {
	4358	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	4359	+ VOP_WIN_SET(vop2, win, enable, 1);
	4360	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN)
	4361	+ VOP_CLUSTER_SET(vop2, win, enable, 1);
	4362	+ }
	4363	+
	4364	+ vop2_cfg_done(crtc);
	4365	+ vop2_wait_for_fs_by_done_bit_status(vp);
3147	4366	}
3148	4367
3149	4368	static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
3150	4369	struct drm_crtc_state *old_state)
3151	4370	{
3152	4371	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4372	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
3153	4373	struct vop2 *vop2 = vp->vop2;
	4374	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	4375	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	4376	+ bool dual_channel = !!(vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE);
3154	4377	int ret;
3155	4378
3156	4379	WARN_ON(vp->event);
	4380	+
	4381	+ if (crtc->state->self_refresh_active) {
	4382	+ vop2_crtc_atomic_enter_psr(crtc, old_state);
	4383	+ goto out;
	4384	+ }
	4385	+
3157	4386	vop2_lock(vop2);
3158	4387	DRM_DEV_INFO(vop2->dev, "Crtc atomic disable vp%d\n", vp->id);
	4388	+ VOP_MODULE_SET(vop2, vp, almost_full_or_en, 0);
	4389	+ VOP_MODULE_SET(vop2, vp, line_flag_or_en, 0);
3159	4390	drm_crtc_vblank_off(crtc);
	4391	+ if (vop2->dscs[vcstate->dsc_id].enabled &&
	4392	+ vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
	4393	+ vop2->data->nr_dscs) {
	4394	+ if (dual_channel) {
	4395	+ vop2_crtc_disable_dsc(vop2, 0);
	4396	+ vop2_crtc_disable_dsc(vop2, 1);
	4397	+ } else {
	4398	+ vop2_crtc_disable_dsc(vop2, vcstate->dsc_id);
	4399	+ }
	4400	+ }
3160	4401
3161	4402	if (vp->cubic_lut) {
3162	4403	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0);
3163	4404	VOP_MODULE_SET(vop2, vp, cubic_lut_en, 0);
3164	4405	}
3165	4406
	4407	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	4408	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 0);
3166	4409	vop2_disable_all_planes_for_crtc(crtc);
3167	4410
	4411	+ if (vop2->dscs[vcstate->dsc_id].enabled &&
	4412	+ vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
	4413	+ vop2->data->nr_dscs && vop2->dscs[vcstate->dsc_id].pd) {
	4414	+ if (dual_channel) {
	4415	+ vop2_power_domain_put(vop2->dscs[0].pd);
	4416	+ vop2_power_domain_put(vop2->dscs[1].pd);
	4417	+ vop2->dscs[0].pd->vp_mask = 0;
	4418	+ vop2->dscs[1].pd->vp_mask = 0;
	4419	+ vop2->dscs[0].attach_vp_id = -1;
	4420	+ vop2->dscs[1].attach_vp_id = -1;
	4421	+ } else {
	4422	+ vop2_power_domain_put(vop2->dscs[vcstate->dsc_id].pd);
	4423	+ vop2->dscs[vcstate->dsc_id].pd->vp_mask = 0;
	4424	+ vop2->dscs[vcstate->dsc_id].attach_vp_id = -1;
	4425	+ }
	4426	+ vop2->dscs[vcstate->dsc_id].enabled = false;
	4427	+ vcstate->dsc_enable = false;
	4428	+ }
	4429	+
	4430	+ if (vp->output_if & VOP_OUTPUT_IF_eDP0)
	4431	+ VOP_GRF_SET(vop2, grf, grf_edp0_en, 0);
	4432	+
	4433	+ if (vp->output_if & VOP_OUTPUT_IF_eDP1) {
	4434	+ VOP_GRF_SET(vop2, grf, grf_edp1_en, 0);
	4435	+ if (dual_channel)
	4436	+ VOP_CTRL_SET(vop2, edp_dual_en, 0);
	4437	+ }
	4438	+
	4439	+ if (vp->output_if & VOP_OUTPUT_IF_HDMI0) {
	4440	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 0);
	4441	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 0);
	4442	+ }
	4443	+
	4444	+ if (vp->output_if & VOP_OUTPUT_IF_HDMI1) {
	4445	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 0);
	4446	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 0);
	4447	+ if (dual_channel)
	4448	+ VOP_CTRL_SET(vop2, hdmi_dual_en, 0);
	4449	+ }
	4450	+
	4451	+ if ((vcstate->output_if & VOP_OUTPUT_IF_DP1) && dual_channel)
	4452	+ VOP_CTRL_SET(vop2, dp_dual_en, 0);
	4453	+
	4454	+ if ((vcstate->output_if & VOP_OUTPUT_IF_MIPI1) && dual_channel)
	4455	+ VOP_CTRL_SET(vop2, mipi_dual_en, 0);
	4456	+
	4457	+ VOP_MODULE_SET(vop2, vp, dual_channel_en, 0);
	4458	+ VOP_MODULE_SET(vop2, vp, dual_channel_swap, 0);
	4459	+
	4460	+ vp->output_if = 0;
	4461	+
	4462	+ vop2_clk_set_parent_extend(vp, vcstate, false);
3168	4463	/*
3169	4464	* Vop standby will take effect at end of current frame,
3170	4465	* if dsp hold valid irq happen, it means standby complete.
..	..	@@ -3177,6 +4472,8 @@
3177	4472
3178	4473	spin_lock(&vop2->reg_lock);
3179	4474
	4475	+ VOP_MODULE_SET(vop2, vp, splice_en, 0);
	4476	+
3180	4477	VOP_MODULE_SET(vop2, vp, standby, 1);
3181	4478
3182	4479	spin_unlock(&vop2->reg_lock);
..	..	@@ -3188,11 +4485,21 @@
3188	4485	vop2_dsp_hold_valid_irq_disable(crtc);
3189	4486
3190	4487	vop2_disable(crtc);
3191		- vop2_unlock(vop2);
3192	4488
3193	4489	vop2->active_vp_mask &= ~BIT(vp->id);
	4490	+ if (vcstate->splice_mode)
	4491	+ vop2->active_vp_mask &= ~BIT(splice_vp->id);
	4492	+ vcstate->splice_mode = false;
	4493	+ vcstate->output_flags = 0;
	4494	+ vp->splice_mode_right = false;
	4495	+ vp->loader_protect = false;
	4496	+ splice_vp->splice_mode_right = false;
	4497	+ memset(&vp->active_tv_state, 0, sizeof(vp->active_tv_state));
	4498	+ vop2_unlock(vop2);
	4499	+
3194	4500	vop2_set_system_status(vop2);
3195	4501
	4502	+out:
3196	4503	if (crtc->state->event && !crtc->state->active) {
3197	4504	spin_lock_irq(&crtc->dev->event_lock);
3198	4505	drm_crtc_send_vblank_event(crtc, crtc->state->event);
..	..	@@ -3202,23 +4509,241 @@
3202	4509	}
3203	4510	}
3204	4511
	4512	+static int vop2_cluster_two_win_mode_check(struct drm_plane_state *pstate)
	4513	+{
	4514	+ struct drm_atomic_state *state = pstate->state;
	4515	+ struct drm_plane *plane = pstate->plane;
	4516	+ struct vop2_win *win = to_vop2_win(plane);
	4517	+ struct vop2 *vop2 = win->vop2;
	4518	+ struct vop2_win *main_win = vop2_find_win_by_phys_id(vop2, win->phys_id);
	4519	+ struct drm_plane_state *main_pstate;
	4520	+ int actual_w = drm_rect_width(&pstate->src) >> 16;
	4521	+ int xoffset;
	4522	+
	4523	+ if (pstate->fb->modifier == DRM_FORMAT_MOD_LINEAR)
	4524	+ xoffset = 0;
	4525	+ else
	4526	+ xoffset = pstate->src.x1 >> 16;
	4527	+
	4528	+ if ((actual_w + xoffset % 16) > 2048) {
	4529	+ DRM_ERROR("%s act_w(%d) + xoffset(%d) / 16 << 2048 in two win mode\n",
	4530	+ win->name, actual_w, xoffset);
	4531	+ return -EINVAL;
	4532	+ }
	4533	+
	4534	+ main_pstate = drm_atomic_get_new_plane_state(state, &main_win->base);
	4535	+
	4536	+ if (pstate->fb->modifier != main_pstate->fb->modifier) {
	4537	+ DRM_ERROR("%s(fb->modifier: 0x%llx) must use same data layout as %s(fb->modifier: 0x%llx)\n",
	4538	+ win->name, pstate->fb->modifier, main_win->name, main_pstate->fb->modifier);
	4539	+ return -EINVAL;
	4540	+ }
	4541	+
	4542	+ if (main_pstate->fb->modifier == DRM_FORMAT_MOD_LINEAR)
	4543	+ xoffset = 0;
	4544	+ else
	4545	+ xoffset = main_pstate->src.x1 >> 16;
	4546	+ actual_w = drm_rect_width(&main_pstate->src) >> 16;
	4547	+
	4548	+ if ((actual_w + xoffset % 16) > 2048) {
	4549	+ DRM_ERROR("%s act_w(%d) + xoffset(%d) / 16 << 2048 in two win mode\n",
	4550	+ main_win->name, actual_w, xoffset);
	4551	+ return -EINVAL;
	4552	+ }
	4553	+
	4554	+ return 0;
	4555	+}
	4556	+
	4557	+static int vop2_cluter_splice_scale_check(struct vop2_win win, struct drm_plane_state pstate,
	4558	+ u16 hdisplay)
	4559	+{
	4560	+ struct drm_rect src = drm_plane_state_src(pstate);
	4561	+ struct drm_rect dst = drm_plane_state_dest(pstate);
	4562	+ u16 half_hdisplay = hdisplay >> 1;
	4563	+
	4564	+ /* scale up is ok */
	4565	+ if ((drm_rect_width(&src) >> 16) <= drm_rect_width(&dst))
	4566	+ return 0;
	4567	+
	4568	+ if ((drm_rect_width(&src) >> 16) <= VOP2_MAX_VP_OUTPUT_WIDTH)
	4569	+ return 0;
	4570	+ /*
	4571	+ * Cluster scale down limitation in splice mode:
	4572	+ * If scale down, must display at horizontal center
	4573	+ */
	4574	+ if ((dst.x1 < half_hdisplay) && (dst.x2 > half_hdisplay)) {
	4575	+ if ((dst.x2 + dst.x1) != hdisplay) {
	4576	+ DRM_ERROR("%s src_w: %d dst_w %d dst(%d %d) must scale down at center in splice mode\n",
	4577	+ win->name, drm_rect_width(&src) >> 16,
	4578	+ drm_rect_width(&dst), dst.x1, dst.x2);
	4579	+ return -EINVAL;
	4580	+ }
	4581	+
	4582	+ if (drm_rect_calc_hscale(&src, &dst, 1, FRAC_16_16(6, 5)) < 0) {
	4583	+ DRM_ERROR("%s %d --> %d scale down factor should < 1.2 in splice mode\n",
	4584	+ win->name, drm_rect_width(&src) >> 16, drm_rect_width(&dst));
	4585	+ return -EINVAL;
	4586	+ }
	4587	+ }
	4588	+
	4589	+ return 0;
	4590	+}
	4591	+
	4592	+static int vop2_plane_splice_check(struct drm_plane plane, struct drm_plane_state pstate,
	4593	+ struct drm_display_mode *mode)
	4594	+{
	4595	+ struct vop2_win *win = to_vop2_win(plane);
	4596	+ int ret = 0;
	4597	+
	4598	+ if (!(win->feature & WIN_FEATURE_SPLICE_LEFT)) {
	4599	+ DRM_ERROR("%s can't be left win in splice mode\n", win->name);
	4600	+ return -EINVAL;
	4601	+ }
	4602	+
	4603	+ if (win->feature & WIN_FEATURE_CLUSTER_SUB) {
	4604	+ DRM_ERROR("%s can't use two win mode in splice mode\n", win->name);
	4605	+ return -EINVAL;
	4606	+ }
	4607	+
	4608	+ if ((pstate->rotation & DRM_MODE_ROTATE_270) \|\|
	4609	+ (pstate->rotation & DRM_MODE_ROTATE_90) \|\|
	4610	+ (pstate->rotation & DRM_MODE_REFLECT_X)) {
	4611	+ DRM_ERROR("%s can't rotate 270/90 and xmirror in splice mode\n", win->name);
	4612	+ return -EINVAL;
	4613	+ }
	4614	+
	4615	+ /* check for cluster splice scale down */
	4616	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN)
	4617	+ ret = vop2_cluter_splice_scale_check(win, pstate, mode->hdisplay);
	4618	+
	4619	+ return ret;
	4620	+}
	4621	+
	4622	+/*
	4623	+ * 1. NV12/NV16/YUYV xoffset must aligned as 2 pixel;
	4624	+ * 2. NV12/NV15 yoffset must aligned as 2 pixel;
	4625	+ * 3. NV30 xoffset must aligned as 4 pixel;
	4626	+ * 4. NV15/NV20 xoffset must aligend as 8 pixel at rk3568/rk3588/rk3528/rk3562,
	4627	+ * others must aligned as 4 pixel;
	4628	+ */
	4629	+static int vop2_linear_yuv_format_check(struct drm_plane plane, struct drm_plane_state state)
	4630	+{
	4631	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(state);
	4632	+ struct drm_crtc *crtc = state->crtc;
	4633	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4634	+ struct vop2_win *win = to_vop2_win(plane);
	4635	+ struct drm_framebuffer *fb = state->fb;
	4636	+ struct drm_rect *src = &vpstate->src;
	4637	+ u32 val = 0;
	4638	+
	4639	+ if (vpstate->afbc_en \|\| vpstate->tiled_en \|\| !fb->format->is_yuv)
	4640	+ return 0;
	4641	+
	4642	+ switch (fb->format->format) {
	4643	+ case DRM_FORMAT_NV12:
	4644	+ case DRM_FORMAT_NV21:
	4645	+ val = src->x1 >> 16;
	4646	+ if (val % 2) {
	4647	+ src->x1 = ALIGN(val, 2) << 16;
	4648	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 2 pixel at NV12 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4649	+ }
	4650	+ val = src->y1 >> 16;
	4651	+ if (val % 2) {
	4652	+ src->y1 = ALIGN(val, 2) << 16;
	4653	+ DRM_WARN("VP%d %s src y offset[%d] must aligned as 2 pixel at NV12 fmt, and adjust to: %d\n", vp->id, win->name, val, src->y1 >> 16);
	4654	+ }
	4655	+ break;
	4656	+ case DRM_FORMAT_NV15:
	4657	+ val = src->y1 >> 16;
	4658	+ if (val % 2) {
	4659	+ src->y1 = ALIGN(val, 2) << 16;
	4660	+ DRM_WARN("VP%d %s src y offset[%d] must aligned as 2 pixel at NV15 fmt, and adjust to: %d\n", vp->id, win->name, val, src->y1 >> 16);
	4661	+ }
	4662	+ if (vp->vop2->version == VOP_VERSION_RK3568 \|\|
	4663	+ vp->vop2->version == VOP_VERSION_RK3588 \|\|
	4664	+ vp->vop2->version == VOP_VERSION_RK3528 \|\|
	4665	+ vp->vop2->version == VOP_VERSION_RK3562) {
	4666	+ val = src->x1 >> 16;
	4667	+ if (val % 8) {
	4668	+ src->x1 = ALIGN(val, 8) << 16;
	4669	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 8 pixel at NV15 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4670	+ }
	4671	+ } else {
	4672	+ val = src->x1 >> 16;
	4673	+ if (val % 4) {
	4674	+ src->x1 = ALIGN(val, 4) << 16;
	4675	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 4 pixel at NV15 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4676	+ }
	4677	+ }
	4678	+ break;
	4679	+ case DRM_FORMAT_NV16:
	4680	+ case DRM_FORMAT_NV61:
	4681	+ case DRM_FORMAT_YUYV:
	4682	+ case DRM_FORMAT_YVYU:
	4683	+ case DRM_FORMAT_VYUY:
	4684	+ case DRM_FORMAT_UYVY:
	4685	+ val = src->x1 >> 16;
	4686	+ if (val % 2) {
	4687	+ src->x1 = ALIGN(val, 2) << 16;
	4688	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 2 pixel at YUYV fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4689	+ }
	4690	+ break;
	4691	+ case DRM_FORMAT_NV20:
	4692	+ if (vp->vop2->version == VOP_VERSION_RK3568 \|\|
	4693	+ vp->vop2->version == VOP_VERSION_RK3588 \|\|
	4694	+ vp->vop2->version == VOP_VERSION_RK3528 \|\|
	4695	+ vp->vop2->version == VOP_VERSION_RK3562) {
	4696	+ val = src->x1 >> 16;
	4697	+ if (val % 8) {
	4698	+ src->x1 = ALIGN(val, 8) << 16;
	4699	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 8 pixel at NV20 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4700	+ }
	4701	+ } else {
	4702	+ val = src->x1 >> 16;
	4703	+ if (val % 4) {
	4704	+ src->x1 = ALIGN(val, 4) << 16;
	4705	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 4 pixel at NV20 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4706	+ }
	4707	+ }
	4708	+ break;
	4709	+ case DRM_FORMAT_NV30:
	4710	+ val = src->x1 >> 16;
	4711	+ if (val % 4) {
	4712	+ src->x1 = ALIGN(val, 4) << 16;
	4713	+ DRM_WARN("VP%d %s src x offset[%d] must aligned as 4 pixel at NV30 fmt, and adjust to: %d\n", vp->id, win->name, val, src->x1 >> 16);
	4714	+ }
	4715	+ break;
	4716	+ default:
	4717	+ return 0;
	4718	+ }
	4719	+
	4720	+ return 0;
	4721	+}
	4722	+
3205	4723	static int vop2_plane_atomic_check(struct drm_plane plane, struct drm_plane_state state)
3206	4724	{
3207	4725	struct vop2_plane_state *vpstate = to_vop2_plane_state(state);
3208	4726	struct vop2_win *win = to_vop2_win(plane);
	4727	+ struct vop2_win *splice_win;
	4728	+ struct vop2 *vop2 = win->vop2;
3209	4729	struct drm_framebuffer *fb = state->fb;
	4730	+ struct drm_display_mode *mode;
3210	4731	struct drm_crtc *crtc = state->crtc;
3211	4732	struct drm_crtc_state *cstate;
	4733	+ struct rockchip_crtc_state *vcstate;
3212	4734	struct vop2_video_port *vp;
3213	4735	const struct vop2_data *vop2_data;
3214	4736	struct drm_rect *dest = &vpstate->dest;
3215	4737	struct drm_rect *src = &vpstate->src;
	4738	+ struct drm_gem_object obj, uv_obj;
	4739	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
3216	4740	int min_scale = win->regs->scl ? FRAC_16_16(1, 8) : DRM_PLANE_HELPER_NO_SCALING;
3217	4741	int max_scale = win->regs->scl ? FRAC_16_16(8, 1) : DRM_PLANE_HELPER_NO_SCALING;
3218	4742	uint32_t tile_size = 1;
	4743	+ int max_input_w;
	4744	+ int max_input_h;
3219	4745	unsigned long offset;
3220	4746	dma_addr_t dma_addr;
3221		- void *kvaddr;
3222	4747	int ret;
3223	4748
3224	4749	crtc = crtc ? crtc : plane->state->crtc;
..	..	@@ -3234,6 +4759,26 @@
3234	4759	if (WARN_ON(!cstate))
3235	4760	return -EINVAL;
3236	4761
	4762	+ mode = &cstate->mode;
	4763	+ vcstate = to_rockchip_crtc_state(cstate);
	4764	+
	4765	+ max_input_w = vop2_data->max_input.width;
	4766	+ max_input_h = vop2_data->max_input.height;
	4767	+
	4768	+ if (vop2_has_feature(win->vop2, VOP_FEATURE_SPLICE)) {
	4769	+ if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	4770	+ vcstate->splice_mode = true;
	4771	+ ret = vop2_plane_splice_check(plane, state, mode);
	4772	+ if (ret < 0)
	4773	+ return ret;
	4774	+ splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
	4775	+ splice_win->splice_mode_right = true;
	4776	+ splice_win->left_win = win;
	4777	+ win->splice_win = splice_win;
	4778	+ max_input_w <<= 1;
	4779	+ }
	4780	+ }
	4781	+
3237	4782	vpstate->xmirror_en = (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0;
3238	4783	vpstate->ymirror_en = (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0;
3239	4784	vpstate->rotate_270_en = (state->rotation & DRM_MODE_ROTATE_270) ? 1 : 0;
..	..	@@ -3243,7 +4788,6 @@
3243	4788	DRM_ERROR("Can't rotate 90 and 270 at the same time\n");
3244	4789	return -EINVAL;
3245	4790	}
3246		-
3247	4791
3248	4792	ret = drm_atomic_helper_check_plane_state(state, cstate,
3249	4793	min_scale, max_scale,
..	..	@@ -3284,13 +4828,13 @@
3284	4828	return 0;
3285	4829	}
3286	4830
3287		- if (drm_rect_width(src) >> 16 > vop2_data->max_input.width \|\|
3288		- drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
	4831	+ if (drm_rect_width(src) >> 16 > max_input_w \|\|
	4832	+ drm_rect_height(src) >> 16 > max_input_h) {
3289	4833	DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
3290	4834	drm_rect_width(src) >> 16,
3291	4835	drm_rect_height(src) >> 16,
3292		- vop2_data->max_input.width,
3293		- vop2_data->max_input.height);
	4836	+ max_input_w,
	4837	+ max_input_h);
3294	4838	return -EINVAL;
3295	4839	}
3296	4840
..	..	@@ -3313,23 +4857,40 @@
3313	4857	* This is special feature at rk356x, the cluster layer only can support
3314	4858	* afbc format and can't support linear format;
3315	4859	*/
3316		- if (VOP_MAJOR(vop2_data->version) == 0x40 && VOP_MINOR(vop2_data->version) == 0x15) {
	4860	+ if (vp->vop2->version == VOP_VERSION_RK3568) {
3317	4861	if (vop2_cluster_window(win) && !vpstate->afbc_en) {
3318	4862	DRM_ERROR("Unsupported linear format at %s\n", win->name);
3319	4863	return -EINVAL;
3320	4864	}
3321	4865	}
3322	4866
3323		- /*
3324		- * Src.x1 can be odd when do clip, but yuv plane start point
3325		- * need align with 2 pixel.
3326		- */
3327		- if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
3328		- DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
3329		- return -EINVAL;
	4867	+ if (vp->vop2->version > VOP_VERSION_RK3568) {
	4868	+ if (vop2_cluster_window(win) && !vpstate->afbc_en && fb->format->is_yuv && !is_vop3(vop2)) {
	4869	+ DRM_ERROR("Unsupported linear yuv format at %s\n", win->name);
	4870	+ return -EINVAL;
	4871	+ }
	4872	+
	4873	+ if (vop2_cluster_window(win) && !vpstate->afbc_en &&
	4874	+ (win->supported_rotations & state->rotation)) {
	4875	+ DRM_ERROR("Unsupported linear rotation(%d) format at %s\n",
	4876	+ state->rotation, win->name);
	4877	+ return -EINVAL;
	4878	+ }
3330	4879	}
3331	4880
3332		- offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->bpp[0] / 8 * tile_size;
	4881	+ if (win->feature & WIN_FEATURE_CLUSTER_SUB) {
	4882	+ ret = vop2_cluster_two_win_mode_check(state);
	4883	+ if (ret < 0)
	4884	+ return ret;
	4885	+ }
	4886	+
	4887	+ if (vop2_linear_yuv_format_check(plane, state))
	4888	+ return -EINVAL;
	4889	+
	4890	+ if (fb->format->char_per_block[0] == 0)
	4891	+ offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->cpp[0] * tile_size;
	4892	+ else
	4893	+ offset = drm_format_info_min_pitch(fb->format, 0, ALIGN_DOWN(src->x1 >> 16, tile_size)) * tile_size;
3333	4894	vpstate->offset = offset + fb->offsets[0];
3334	4895
3335	4896	/*
..	..	@@ -3342,30 +4903,33 @@
3342	4903	else
3343	4904	offset += ALIGN_DOWN(src->y1 >> 16, tile_size) * fb->pitches[0];
3344	4905
3345		- dma_addr = rockchip_fb_get_dma_addr(fb, 0);
3346		- kvaddr = rockchip_fb_get_kvaddr(fb, 0);
	4906	+ obj = fb->obj[0];
	4907	+ rk_obj = to_rockchip_obj(obj);
3347	4908
3348		- vpstate->yrgb_mst = dma_addr + offset + fb->offsets[0];
3349		- vpstate->yrgb_kvaddr = kvaddr + offset + fb->offsets[0];
3350		- if (fb->format->is_yuv) {
3351		- int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
3352		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
	4909	+ vpstate->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
	4910	+ if (fb->format->is_yuv && fb->format->num_planes > 1) {
	4911	+ int hsub = fb->format->hsub;
	4912	+ int vsub = fb->format->vsub;
3353	4913
3354		- offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->bpp[1] / hsub / 8 * tile_size;
	4914	+ if (fb->format->char_per_block[0] == 0)
	4915	+ offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->cpp[1] / hsub * tile_size;
	4916	+ else
	4917	+ offset = drm_format_info_min_pitch(fb->format, 1, ALIGN_DOWN(src->x1 >> 16, tile_size)) * tile_size / hsub;
	4918	+
3355	4919	if (vpstate->tiled_en)
3356	4920	offset /= vsub;
3357	4921	offset += ALIGN_DOWN(src->y1 >> 16, tile_size) * fb->pitches[1] / vsub;
	4922	+
	4923	+ uv_obj = fb->obj[1];
	4924	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	4925	+
3358	4926	if (vpstate->ymirror_en && !vpstate->afbc_en)
3359	4927	offset += fb->pitches[1] * ((state->src_h >> 16) - 2) / vsub;
3360		- dma_addr = rockchip_fb_get_dma_addr(fb, 1);
3361		- dma_addr += offset + fb->offsets[1];
	4928	+ dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
3362	4929	vpstate->uv_mst = dma_addr;
3363		-
3364	4930	/* tile 4x4 m0 format, y and uv is packed together */
3365		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0) {
	4931	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0)
3366	4932	vpstate->yrgb_mst += offset;
3367		- vpstate->yrgb_kvaddr += offset;
3368		- }
3369	4933	}
3370	4934
3371	4935	return 0;
..	..	@@ -3375,19 +4939,30 @@
3375	4939	{
3376	4940	struct vop2_win *win = to_vop2_win(plane);
3377	4941	struct vop2 *vop2 = win->vop2;
	4942	+ struct drm_crtc *crtc;
	4943	+ struct vop2_video_port *vp;
	4944	+
3378	4945	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
3379	4946	struct vop2_plane_state *vpstate = to_vop2_plane_state(plane->state);
3380	4947	#endif
3381	4948
3382		- DRM_DEV_DEBUG(vop2->dev, "%s disable\n", win->name);
	4949	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE, "%s disable %s\n",
	4950	+ win->name, current->comm);
3383	4951
3384	4952	if (!old_state->crtc)
3385	4953	return;
3386	4954
3387	4955	spin_lock(&vop2->reg_lock);
3388	4956
3389		- vop2_win_disable(win);
3390		- VOP_WIN_SET(vop2, win, yuv_clip, 0);
	4957	+ crtc = old_state->crtc;
	4958	+ vp = to_vop2_video_port(crtc);
	4959	+
	4960	+ vop2_win_disable(win, false);
	4961	+ vp->enabled_win_mask &= ~BIT(win->phys_id);
	4962	+ if (win->splice_win) {
	4963	+ vop2_win_disable(win->splice_win, false);
	4964	+ vp->enabled_win_mask &= ~BIT(win->splice_win->phys_id);
	4965	+ }
3391	4966
3392	4967	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
3393	4968	kfree(vpstate->planlist);
..	..	@@ -3451,6 +5026,64 @@
3451	5026	VOP_WIN_SET(vop2, win, color_key, color_key);
3452	5027	}
3453	5028
	5029	+static void vop2_calc_drm_rect_for_splice(struct vop2_plane_state *vpstate,
	5030	+ struct drm_rect left_src, struct drm_rect left_dst,
	5031	+ struct drm_rect right_src, struct drm_rect right_dst)
	5032	+{
	5033	+ struct drm_crtc *crtc = vpstate->base.crtc;
	5034	+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	5035	+ struct drm_rect *dst = &vpstate->dest;
	5036	+ struct drm_rect *src = &vpstate->src;
	5037	+ u16 half_hdisplay = mode->crtc_hdisplay >> 1;
	5038	+ int hscale = drm_rect_calc_hscale(src, dst, 0, INT_MAX);
	5039	+ int dst_w = drm_rect_width(dst);
	5040	+ int src_w = drm_rect_width(src) >> 16;
	5041	+ int left_src_w, left_dst_w, right_dst_w;
	5042	+ struct drm_plane_state *pstate = &vpstate->base;
	5043	+ struct drm_framebuffer *fb = pstate->fb;
	5044	+
	5045	+ left_dst_w = min_t(u16, half_hdisplay, dst->x2) - dst->x1;
	5046	+ if (left_dst_w < 0)
	5047	+ left_dst_w = 0;
	5048	+ right_dst_w = dst_w - left_dst_w;
	5049	+
	5050	+ if (!right_dst_w)
	5051	+ left_src_w = src_w;
	5052	+ else
	5053	+ left_src_w = (left_dst_w * hscale) >> 16;
	5054	+
	5055	+ /*
	5056	+ * Make sure the yrgb/uv mst of right win are byte aligned
	5057	+ * with full pixel.
	5058	+ */
	5059	+ if (right_dst_w) {
	5060	+ if (fb->format->format == DRM_FORMAT_NV15)
	5061	+ left_src_w &= ~0x7;
	5062	+ else if (fb->format->format == DRM_FORMAT_NV12)
	5063	+ left_src_w &= ~0x1;
	5064	+ }
	5065	+ left_src->x1 = src->x1;
	5066	+ left_src->x2 = src->x1 + (left_src_w << 16);
	5067	+ left_dst->x1 = dst->x1;
	5068	+ left_dst->x2 = dst->x1 + left_dst_w;
	5069	+ right_src->x1 = left_src->x2;
	5070	+ right_src->x2 = src->x2;
	5071	+ right_dst->x1 = dst->x1 + left_dst_w - half_hdisplay;
	5072	+ if (right_dst->x1 < 0)
	5073	+ right_dst->x1 = 0;
	5074	+
	5075	+ right_dst->x2 = right_dst->x1 + right_dst_w;
	5076	+
	5077	+ left_src->y1 = src->y1;
	5078	+ left_src->y2 = src->y2;
	5079	+ left_dst->y1 = dst->y1;
	5080	+ left_dst->y2 = dst->y2;
	5081	+ right_src->y1 = src->y1;
	5082	+ right_src->y2 = src->y2;
	5083	+ right_dst->y1 = dst->y1;
	5084	+ right_dst->y2 = dst->y2;
	5085	+}
	5086	+
3454	5087	static void rk3588_vop2_win_cfg_axi(struct vop2_win *win)
3455	5088	{
3456	5089	struct vop2 *vop2 = win->vop2;
..	..	@@ -3485,49 +5118,312 @@
3485	5118	}
3486	5119	}
3487	5120
	5121	+static void vop2_win_atomic_update(struct vop2_win win, struct drm_rect src, struct drm_rect *dst,
	5122	+ struct drm_plane_state *pstate)
	5123	+{
	5124	+ struct drm_crtc *crtc = pstate->crtc;
	5125	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5126	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	5127	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	5128	+ struct vop2 *vop2 = win->vop2;
	5129	+ struct drm_framebuffer *fb = pstate->fb;
	5130	+ struct drm_rect *left_src = &vpstate->src;
	5131	+ uint32_t bpp = rockchip_drm_get_bpp(fb->format);
	5132	+ uint32_t actual_w, actual_h, dsp_w, dsp_h;
	5133	+ uint32_t dsp_stx, dsp_sty;
	5134	+ uint32_t act_info, dsp_info, dsp_st;
	5135	+ uint32_t format, check_size;
	5136	+ uint32_t afbc_format;
	5137	+ uint32_t rb_swap;
	5138	+ uint32_t uv_swap;
	5139	+ uint32_t afbc_half_block_en;
	5140	+ uint32_t afbc_tile_num;
	5141	+ uint32_t lb_mode;
	5142	+ uint32_t stride, uv_stride = 0;
	5143	+ uint32_t transform_offset;
	5144	+ /* offset of the right window in splice mode */
	5145	+ uint32_t splice_pixel_offset = 0;
	5146	+ uint32_t splice_yrgb_offset = 0;
	5147	+ uint32_t splice_uv_offset = 0;
	5148	+ uint32_t afbc_xoffset;
	5149	+ uint32_t hsub;
	5150	+ dma_addr_t yrgb_mst;
	5151	+ dma_addr_t uv_mst;
	5152	+
	5153	+ struct drm_format_name_buf format_name;
	5154	+ bool dither_up;
	5155	+ bool tile_4x4_m0 = vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 ? true : false;
	5156	+
	5157	+ actual_w = drm_rect_width(src) >> 16;
	5158	+ actual_h = drm_rect_height(src) >> 16;
	5159	+
	5160	+ if (!actual_w \|\| !actual_h \|\| !bpp) {
	5161	+ vop2_win_disable(win, true);
	5162	+ return;
	5163	+ }
	5164	+
	5165	+ dsp_w = drm_rect_width(dst);
	5166	+ /*
	5167	+ * This win is for the right part of the plane,
	5168	+ * we need calculate the fb offset for it.
	5169	+ */
	5170	+ if (win->splice_mode_right) {
	5171	+ splice_pixel_offset = (src->x1 - left_src->x1) >> 16;
	5172	+ splice_yrgb_offset = drm_format_info_min_pitch(fb->format, 0, splice_pixel_offset);
	5173	+ if (fb->format->is_yuv && fb->format->num_planes > 1) {
	5174	+ hsub = fb->format->hsub;
	5175	+ splice_uv_offset = drm_format_info_min_pitch(fb->format, 1, splice_pixel_offset / hsub);
	5176	+ }
	5177	+ }
	5178	+
	5179	+ if (dst->x1 + dsp_w > adjusted_mode->crtc_hdisplay) {
	5180	+ DRM_ERROR("vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
	5181	+ vp->id, win->name, dst->x1, dsp_w, adjusted_mode->crtc_hdisplay);
	5182	+ dsp_w = adjusted_mode->crtc_hdisplay - dst->x1;
	5183	+ if (dsp_w < 4)
	5184	+ dsp_w = 4;
	5185	+ actual_w = dsp_w * actual_w / drm_rect_width(dst);
	5186	+ }
	5187	+ dsp_h = drm_rect_height(dst);
	5188	+ check_size = adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE ? adjusted_mode->vdisplay : adjusted_mode->crtc_vdisplay;
	5189	+ if (dst->y1 + dsp_h > check_size) {
	5190	+ DRM_ERROR("vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
	5191	+ vp->id, win->name, dst->y1, dsp_h, adjusted_mode->crtc_vdisplay);
	5192	+ dsp_h = adjusted_mode->crtc_vdisplay - dst->y1;
	5193	+ if (dsp_h < 4)
	5194	+ dsp_h = 4;
	5195	+ actual_h = dsp_h * actual_h / drm_rect_height(dst);
	5196	+ }
	5197	+
	5198	+ /*
	5199	+ * Workaround only for rk3568 vop
	5200	+ */
	5201	+ if (vop2->version == VOP_VERSION_RK3568) {
	5202	+ /*
	5203	+ * This is workaround solution for IC design:
	5204	+ * esmart can't support scale down when actual_w % 16 == 1;
	5205	+ * esmart can't support scale down when dsp_w % 2 == 1;
	5206	+ * esmart actual_w should align as 4 pixel when is linear 10 bit yuv format;
	5207	+ *
	5208	+ * cluster actual_w should align as 4 pixel when enable afbc;
	5209	+ */
	5210	+ if (!vop2_cluster_window(win)) {
	5211	+ if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
	5212	+ DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1 at scale down mode\n", vp->id, win->name, actual_w);
	5213	+ actual_w -= 1;
	5214	+ }
	5215	+ if (actual_w > dsp_w && (dsp_w & 0x1) == 1) {
	5216	+ DRM_WARN("vp%d %s dsp_w[%d] MODE 2 == 1 at scale down mode\n", vp->id, win->name, dsp_w);
	5217	+ dsp_w -= 1;
	5218	+ }
	5219	+ }
	5220	+
	5221	+ if (vop2_cluster_window(win) && actual_w % 4) {
	5222	+ DRM_WARN("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
	5223	+ vp->id, win->name, actual_w);
	5224	+ actual_w = ALIGN_DOWN(actual_w, 4);
	5225	+ }
	5226	+ }
	5227	+
	5228	+ if (is_linear_10bit_yuv(fb->format->format) && actual_w & 0x3) {
	5229	+ DRM_WARN("vp%d %s actual_w[%d] should align as 4 pixel when is linear 10 bit yuv format\n", vp->id, win->name, actual_w);
	5230	+ actual_w = ALIGN_DOWN(actual_w, 4);
	5231	+ }
	5232	+
	5233	+ act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
	5234	+ dsp_info = (dsp_h - 1) << 16 \| ((dsp_w - 1) & 0xffff);
	5235	+ stride = DIV_ROUND_UP(fb->pitches[0], 4);
	5236	+ dsp_stx = dst->x1;
	5237	+ dsp_sty = dst->y1;
	5238	+ dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
	5239	+
	5240	+ if (vpstate->tiled_en) {
	5241	+ if (is_vop3(vop2))
	5242	+ format = vop3_convert_tiled_format(fb->format->format, vpstate->tiled_en);
	5243	+ else
	5244	+ format = vop2_convert_tiled_format(fb->format->format);
	5245	+ } else {
	5246	+ format = vop2_convert_format(fb->format->format);
	5247	+ }
	5248	+
	5249	+ vop2_setup_csc_mode(vp, vpstate);
	5250	+
	5251	+ afbc_half_block_en = vop2_afbc_half_block_enable(vpstate);
	5252	+
	5253	+ vop2_win_enable(win);
	5254	+ spin_lock(&vop2->reg_lock);
	5255	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE,
	5256	+ "vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%.4s%s] addr[%pad] by %s\n",
	5257	+ vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
	5258	+ dsp_stx, dsp_sty,
	5259	+ drm_get_format_name(fb->format->format, &format_name),
	5260	+ modifier_to_string(fb->modifier), &vpstate->yrgb_mst, current->comm);
	5261	+
	5262	+ if (vop2->version != VOP_VERSION_RK3568)
	5263	+ rk3588_vop2_win_cfg_axi(win);
	5264	+
	5265	+ if (!win->parent && !vop2_cluster_window(win) && is_vop3(vop2))
	5266	+ VOP_WIN_SET(vop2, win, scale_engine_num, win->scale_engine_num);
	5267	+
	5268	+ if (vpstate->afbc_en) {
	5269	+ /* the afbc superblock is 16 x 16 */
	5270	+ afbc_format = vop2_convert_afbc_format(fb->format->format);
	5271	+ /* Enable color transform for YTR */
	5272	+ if (fb->modifier & AFBC_FORMAT_MOD_YTR)
	5273	+ afbc_format \|= (1 << 4);
	5274	+ afbc_tile_num = ALIGN(actual_w, 16) >> 4;
	5275	+
	5276	+ /* The right win should have a src offset in splice mode */
	5277	+ afbc_xoffset = (src->x1 >> 16);
	5278	+ /* AFBC pic_vir_width is count by pixel, this is different
	5279	+ * with WIN_VIR_STRIDE.
	5280	+ */
	5281	+ stride = (fb->pitches[0] << 3) / bpp;
	5282	+ if ((stride & 0x3f) &&
	5283	+ (vpstate->xmirror_en \|\| vpstate->rotate_90_en \|\| vpstate->rotate_270_en))
	5284	+ DRM_ERROR("vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n",
	5285	+ vp->id, win->name, stride, pstate->rotation);
	5286	+
	5287	+ rb_swap = vop2_afbc_rb_swap(fb->format->format);
	5288	+ uv_swap = vop2_afbc_uv_swap(fb->format->format);
	5289	+ vpstate->afbc_half_block_en = afbc_half_block_en;
	5290	+
	5291	+ transform_offset = vop2_afbc_transform_offset(vpstate, splice_pixel_offset);
	5292	+ VOP_CLUSTER_SET(vop2, win, afbc_enable, 1);
	5293	+ VOP_AFBC_SET(vop2, win, format, afbc_format);
	5294	+ VOP_AFBC_SET(vop2, win, rb_swap, rb_swap);
	5295	+ VOP_AFBC_SET(vop2, win, uv_swap, uv_swap);
	5296	+
	5297	+ if (vop2->version == VOP_VERSION_RK3568)
	5298	+ VOP_AFBC_SET(vop2, win, auto_gating_en, 0);
	5299	+ else
	5300	+ VOP_AFBC_SET(vop2, win, auto_gating_en, 1);
	5301	+ VOP_AFBC_SET(vop2, win, block_split_en, 0);
	5302	+ VOP_AFBC_SET(vop2, win, hdr_ptr, vpstate->yrgb_mst);
	5303	+ VOP_AFBC_SET(vop2, win, pic_size, act_info);
	5304	+ VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
	5305	+ VOP_AFBC_SET(vop2, win, pic_offset, (afbc_xoffset \| src->y1));
	5306	+ VOP_AFBC_SET(vop2, win, dsp_offset, (dst->x1 \| (dst->y1 << 16)));
	5307	+ VOP_AFBC_SET(vop2, win, pic_vir_width, stride);
	5308	+ VOP_AFBC_SET(vop2, win, tile_num, afbc_tile_num);
	5309	+ VOP_AFBC_SET(vop2, win, xmirror, vpstate->xmirror_en);
	5310	+ VOP_AFBC_SET(vop2, win, ymirror, vpstate->ymirror_en);
	5311	+ VOP_AFBC_SET(vop2, win, rotate_270, vpstate->rotate_270_en);
	5312	+ VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
	5313	+ } else {
	5314	+ VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
	5315	+ transform_offset = vop2_tile_transform_offset(vpstate, vpstate->tiled_en);
	5316	+ VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
	5317	+ VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
	5318	+ VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
	5319	+ }
	5320	+
	5321	+ if (vpstate->rotate_90_en \|\| vpstate->rotate_270_en) {
	5322	+ act_info = swahw32(act_info);
	5323	+ actual_w = drm_rect_height(src) >> 16;
	5324	+ actual_h = drm_rect_width(src) >> 16;
	5325	+ }
	5326	+
	5327	+ yrgb_mst = vpstate->yrgb_mst + splice_yrgb_offset;
	5328	+ uv_mst = vpstate->uv_mst + splice_uv_offset;
	5329	+ /* rk3588 should set half_blocK_en to 1 in line and tile mode */
	5330	+ VOP_AFBC_SET(vop2, win, half_block_en, afbc_half_block_en);
	5331	+
	5332	+ VOP_WIN_SET(vop2, win, format, format);
	5333	+ VOP_WIN_SET(vop2, win, yrgb_mst, yrgb_mst);
	5334	+
	5335	+ rb_swap = vop2_win_rb_swap(fb->format->format);
	5336	+ uv_swap = vop2_win_uv_swap(fb->format->format);
	5337	+ if (vpstate->tiled_en) {
	5338	+ uv_swap = 1;
	5339	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
	5340	+ stride <<= 3;
	5341	+ else
	5342	+ stride <<= 2;
	5343	+ }
	5344	+ VOP_WIN_SET(vop2, win, rb_swap, rb_swap);
	5345	+ VOP_WIN_SET(vop2, win, uv_swap, uv_swap);
	5346	+
	5347	+ if (fb->format->is_yuv) {
	5348	+ uv_stride = DIV_ROUND_UP(fb->pitches[1], 4);
	5349	+ if (vpstate->tiled_en) {
	5350	+ int vsub = fb->format->vsub;
	5351	+
	5352	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
	5353	+ uv_stride = uv_stride * 8 / vsub;
	5354	+ else
	5355	+ uv_stride = uv_stride * 4 / vsub;
	5356	+ VOP_WIN_SET(vop2, win, tile_mode, tile_4x4_m0);
	5357	+ }
	5358	+
	5359	+ VOP_WIN_SET(vop2, win, uv_vir, uv_stride);
	5360	+ VOP_WIN_SET(vop2, win, uv_mst, uv_mst);
	5361	+ }
	5362	+
	5363	+ /* tile 4x4 m0 format, y and uv is packed together */
	5364	+ if (tile_4x4_m0)
	5365	+ VOP_WIN_SET(vop2, win, yrgb_vir, stride + uv_stride);
	5366	+ else
	5367	+ VOP_WIN_SET(vop2, win, yrgb_vir, stride);
	5368	+
	5369	+ vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, pstate);
	5370	+ vop2_plane_setup_color_key(&win->base);
	5371	+ VOP_WIN_SET(vop2, win, act_info, act_info);
	5372	+ VOP_WIN_SET(vop2, win, dsp_info, dsp_info);
	5373	+ VOP_WIN_SET(vop2, win, dsp_st, dsp_st);
	5374	+
	5375	+ VOP_WIN_SET(vop2, win, y2r_en, vpstate->y2r_en);
	5376	+ VOP_WIN_SET(vop2, win, r2y_en, vpstate->r2y_en);
	5377	+ VOP_WIN_SET(vop2, win, csc_mode, vpstate->csc_mode);
	5378	+
	5379	+ if (win->feature & WIN_FEATURE_Y2R_13BIT_DEPTH && !vop2_cluster_window(win))
	5380	+ VOP_WIN_SET(vop2, win, csc_13bit_en, !!(vpstate->csc_mode & CSC_BT709L_13BIT));
	5381	+
	5382	+ dither_up = vop2_win_dither_up(fb->format->format);
	5383	+ VOP_WIN_SET(vop2, win, dither_up, dither_up);
	5384	+
	5385	+ VOP_WIN_SET(vop2, win, enable, 1);
	5386	+ vp->enabled_win_mask \|= BIT(win->phys_id);
	5387	+ if (vop2_cluster_window(win)) {
	5388	+ lb_mode = vop2_get_cluster_lb_mode(win, vpstate);
	5389	+ VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode);
	5390	+ VOP_CLUSTER_SET(vop2, win, scl_lb_mode, lb_mode == 1 ? 3 : 0);
	5391	+ VOP_CLUSTER_SET(vop2, win, enable, 1);
	5392	+ VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1);
	5393	+ }
	5394	+ spin_unlock(&vop2->reg_lock);
	5395	+}
	5396	+
3488	5397	static void vop2_plane_atomic_update(struct drm_plane plane, struct drm_plane_state old_state)
3489	5398	{
3490	5399	struct drm_plane_state *pstate = plane->state;
3491	5400	struct drm_crtc *crtc = pstate->crtc;
3492	5401	struct vop2_win *win = to_vop2_win(plane);
	5402	+ struct vop2_win *splice_win;
3493	5403	struct vop2_video_port *vp = to_vop2_video_port(crtc);
3494	5404	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
3495		- struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
3496	5405	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
3497		- struct vop2 *vop2 = win->vop2;
3498	5406	struct drm_framebuffer *fb = pstate->fb;
3499		- uint32_t bpp = fb->format->bpp[0];
3500		- uint32_t actual_w, actual_h, dsp_w, dsp_h;
3501		- uint32_t dsp_stx, dsp_sty;
3502		- uint32_t act_info, dsp_info, dsp_st;
3503		- uint32_t format;
3504		- uint32_t afbc_format;
3505		- uint32_t rb_swap;
3506		- uint32_t uv_swap;
3507		- struct drm_rect *src = &vpstate->src;
3508		- struct drm_rect *dest = &vpstate->dest;
3509		- uint32_t afbc_tile_num;
3510		- uint32_t afbc_half_block_en;
3511		- uint32_t lb_mode;
3512		- uint32_t stride, uv_stride = 0;
3513		- uint32_t transform_offset;
3514	5407	struct drm_format_name_buf format_name;
3515		- bool dither_up;
3516		- bool tile_4x4_m0 = vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 ? true : false;
	5408	+ struct vop2 *vop2 = win->vop2;
	5409	+ struct drm_rect wsrc;
	5410	+ struct drm_rect wdst;
	5411	+ /* right part in splice mode */
	5412	+ struct drm_rect right_wsrc;
	5413	+ struct drm_rect right_wdst;
3517	5414
3518	5415	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
	5416	+ struct drm_rect *psrc = &vpstate->src;
3519	5417	bool AFBC_flag = false;
3520	5418	struct vop_dump_list *planlist;
3521	5419	unsigned long num_pages;
3522	5420	struct page **pages;
3523		- struct rockchip_drm_fb *rk_fb;
3524	5421	struct drm_gem_object *obj;
3525	5422	struct rockchip_gem_object *rk_obj;
3526	5423
3527	5424	num_pages = 0;
3528	5425	pages = NULL;
3529		- rk_fb = to_rockchip_fb(fb);
3530		- obj = rk_fb->obj[0];
	5426	+ obj = fb->obj[0];
3531	5427	rk_obj = to_rockchip_obj(obj);
3532	5428	if (rk_obj) {
3533	5429	num_pages = rk_obj->num_pages;
..	..	@@ -3566,211 +5462,24 @@
3566	5462	vp->skip_vsync = false;
3567	5463	}
3568	5464
3569		- actual_w = drm_rect_width(src) >> 16;
3570		- actual_h = drm_rect_height(src) >> 16;
3571		- dsp_w = drm_rect_width(dest);
3572		- if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
3573		- DRM_ERROR("vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
3574		- vp->id, win->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
3575		- dsp_w = adjusted_mode->hdisplay - dest->x1;
3576		- if (dsp_w < 4)
3577		- dsp_w = 4;
3578		- actual_w = dsp_w * actual_w / drm_rect_width(dest);
3579		- }
3580		- dsp_h = drm_rect_height(dest);
3581		- if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
3582		- DRM_ERROR("vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
3583		- vp->id, win->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
3584		- dsp_h = adjusted_mode->vdisplay - dest->y1;
3585		- if (dsp_h < 4)
3586		- dsp_h = 4;
3587		- actual_h = dsp_h * actual_h / drm_rect_height(dest);
3588		- }
	5465	+ if (vcstate->splice_mode) {
	5466	+ DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@(%d,%d)] fmt[%.4s%s] addr[%pad]\n",
	5467	+ vp->id, win->name, drm_rect_width(&vpstate->src) >> 16,
	5468	+ drm_rect_height(&vpstate->src) >> 16,
	5469	+ drm_rect_width(&vpstate->dest), drm_rect_height(&vpstate->dest),
	5470	+ vpstate->dest.x1, vpstate->dest.y1,
	5471	+ drm_get_format_name(fb->format->format, &format_name),
	5472	+ modifier_to_string(fb->modifier), &vpstate->yrgb_mst);
3589	5473
3590		- /*
3591		- * This is workaround solution for IC design:
3592		- * esmart can't support scale down when actual_w % 16 == 1.
3593		- */
3594		- if (!(win->feature & WIN_FEATURE_AFBDC)) {
3595		- if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
3596		- DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->name, actual_w);
3597		- actual_w -= 1;
3598		- }
3599		- }
3600		-
3601		- if (vpstate->afbc_en && actual_w % 4) {
3602		- DRM_ERROR("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
3603		- vp->id, win->name, actual_w);
3604		- actual_w = ALIGN_DOWN(actual_w, 4);
3605		- }
3606		-
3607		- act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
3608		- dsp_info = (dsp_h - 1) << 16 \| ((dsp_w - 1) & 0xffff);
3609		- stride = DIV_ROUND_UP(fb->pitches[0], 4);
3610		- dsp_stx = dest->x1;
3611		- dsp_sty = dest->y1;
3612		- dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
3613		-
3614		- if (vpstate->tiled_en) {
3615		- if (is_vop3(vop2))
3616		- format = vop3_convert_tiled_format(fb->format->format, vpstate->tiled_en);
3617		- else
3618		- format = vop2_convert_tiled_format(fb->format->format);
	5474	+ vop2_calc_drm_rect_for_splice(vpstate, &wsrc, &wdst, &right_wsrc, &right_wdst);
	5475	+ splice_win = win->splice_win;
	5476	+ vop2_win_atomic_update(splice_win, &right_wsrc, &right_wdst, pstate);
3619	5477	} else {
3620		- format = vop2_convert_format(fb->format->format);
	5478	+ memcpy(&wsrc, &vpstate->src, sizeof(struct drm_rect));
	5479	+ memcpy(&wdst, &vpstate->dest, sizeof(struct drm_rect));
3621	5480	}
3622	5481
3623		- vop2_setup_csc_mode(vp, vpstate);
3624		- afbc_half_block_en = vop2_afbc_half_block_enable(vpstate);
3625		-
3626		- spin_lock(&vop2->reg_lock);
3627		- DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%.4s%s] addr[%pad] zpos[%d]\n",
3628		- vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
3629		- dsp_stx, dsp_sty,
3630		- drm_get_format_name(fb->format->format, &format_name),
3631		- modifier_to_string(fb->modifier), &vpstate->yrgb_mst, vpstate->zpos);
3632		-
3633		- if (vop2->version != VOP_VERSION_RK3568)
3634		- rk3588_vop2_win_cfg_axi(win);
3635		-
3636		- if (is_vop3(vop2) && !vop2_cluster_window(win))
3637		- VOP_WIN_SET(vop2, win, scale_engine_num, win->scale_engine_num);
3638		-
3639		- if (vpstate->afbc_en) {
3640		- /* the afbc superblock is 16 x 16 */
3641		- afbc_format = vop2_convert_afbc_format(fb->format->format);
3642		- /* Enable color transform for YTR */
3643		- if (fb->modifier & AFBC_FORMAT_MOD_YTR)
3644		- afbc_format \|= (1 << 4);
3645		- afbc_tile_num = ALIGN(actual_w, 16) >> 4;
3646		- /* AFBC pic_vir_width is count by pixel, this is different
3647		- * with WIN_VIR_STRIDE.
3648		- */
3649		- if (!bpp) {
3650		- WARN(1, "bpp is zero\n");
3651		- bpp = 1;
3652		- }
3653		- stride = (fb->pitches[0] << 3) / bpp;
3654		- if ((stride & 0x3f) &&
3655		- (vpstate->xmirror_en \|\| vpstate->rotate_90_en \|\| vpstate->rotate_270_en))
3656		- DRM_ERROR("vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n",
3657		- vp->id, win->name, stride, pstate->rotation);
3658		-
3659		- rb_swap = vop2_afbc_rb_swap(fb->format->format);
3660		- uv_swap = vop2_afbc_uv_swap(fb->format->format);
3661		- /*
3662		- * This is a workaround for crazy IC design, Cluster
3663		- * and Esmart/Smart use different format configuration map:
3664		- * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
3665		- *
3666		- * This is one thing we can make the convert simple:
3667		- * AFBCD decode all the YUV data to YUV444. So we just
3668		- * set all the yuv 10 bit to YUV444_10.
3669		- */
3670		- if (fb->format->is_yuv && (bpp == 10) && (vop2->version == VOP_VERSION_RK3568))
3671		- format = VOP2_CLUSTER_YUV444_10;
3672		-
3673		- vpstate->afbc_half_block_en = afbc_half_block_en;
3674		- transform_offset = vop2_afbc_transform_offset(vpstate);
3675		- VOP_CLUSTER_SET(vop2, win, afbc_enable, 1);
3676		- VOP_AFBC_SET(vop2, win, format, afbc_format);
3677		- VOP_AFBC_SET(vop2, win, rb_swap, rb_swap);
3678		- VOP_AFBC_SET(vop2, win, uv_swap, uv_swap);
3679		- if (vop2->version == VOP_VERSION_RK3568)
3680		- VOP_AFBC_SET(vop2, win, auto_gating_en, 0);
3681		- else
3682		- VOP_AFBC_SET(vop2, win, auto_gating_en, 1);
3683		- VOP_AFBC_SET(vop2, win, block_split_en, 0);
3684		- VOP_AFBC_SET(vop2, win, hdr_ptr, vpstate->yrgb_mst);
3685		- VOP_AFBC_SET(vop2, win, pic_size, act_info);
3686		- VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
3687		- VOP_AFBC_SET(vop2, win, pic_offset, ((src->x1 >> 16) \| src->y1));
3688		- VOP_AFBC_SET(vop2, win, dsp_offset, (dest->x1 \| (dest->y1 << 16)));
3689		- VOP_AFBC_SET(vop2, win, pic_vir_width, stride);
3690		- VOP_AFBC_SET(vop2, win, tile_num, afbc_tile_num);
3691		- VOP_AFBC_SET(vop2, win, xmirror, vpstate->xmirror_en);
3692		- VOP_AFBC_SET(vop2, win, ymirror, vpstate->ymirror_en);
3693		- VOP_AFBC_SET(vop2, win, rotate_270, vpstate->rotate_270_en);
3694		- VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
3695		- } else {
3696		- VOP_AFBC_SET(vop2, win, enable, 0);
3697		- VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
3698		- transform_offset = vop2_tile_transform_offset(vpstate, vpstate->tiled_en);
3699		- VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
3700		- VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
3701		- VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
3702		- }
3703		-
3704		- if (vpstate->rotate_90_en \|\| vpstate->rotate_270_en) {
3705		- act_info = swahw32(act_info);
3706		- actual_w = drm_rect_height(src) >> 16;
3707		- actual_h = drm_rect_width(src) >> 16;
3708		- }
3709		- VOP_AFBC_SET(vop2, win, half_block_en, afbc_half_block_en);
3710		-
3711		- VOP_WIN_SET(vop2, win, format, format);
3712		- VOP_WIN_SET(vop2, win, yrgb_mst, vpstate->yrgb_mst);
3713		-
3714		- rb_swap = vop2_win_rb_swap(fb->format->format);
3715		- uv_swap = vop2_win_uv_swap(fb->format->format);
3716		- if (vpstate->tiled_en) {
3717		- uv_swap = 1;
3718		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
3719		- stride <<= 3;
3720		- else
3721		- stride <<= 2;
3722		- }
3723		- VOP_WIN_SET(vop2, win, rb_swap, rb_swap);
3724		- VOP_WIN_SET(vop2, win, uv_swap, uv_swap);
3725		-
3726		- if (fb->format->is_yuv) {
3727		- uv_stride = DIV_ROUND_UP(fb->pitches[1], 4);
3728		- if (vpstate->tiled_en) {
3729		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
3730		-
3731		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
3732		- uv_stride = uv_stride * 8 / vsub;
3733		- else
3734		- uv_stride = uv_stride * 4 / vsub;
3735		- VOP_WIN_SET(vop2, win, tile_mode, tile_4x4_m0);
3736		- }
3737		-
3738		- VOP_WIN_SET(vop2, win, uv_vir, uv_stride);
3739		- VOP_WIN_SET(vop2, win, uv_mst, vpstate->uv_mst);
3740		- }
3741		-
3742		- /* tile 4x4 m0 format, y and uv is packed together */
3743		- if (tile_4x4_m0)
3744		- VOP_WIN_SET(vop2, win, yrgb_vir, stride + uv_stride);
3745		- else
3746		- VOP_WIN_SET(vop2, win, yrgb_vir, stride);
3747		-
3748		- vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, pstate);
3749		- vop2_plane_setup_color_key(plane);
3750		- VOP_WIN_SET(vop2, win, act_info, act_info);
3751		- VOP_WIN_SET(vop2, win, dsp_info, dsp_info);
3752		- VOP_WIN_SET(vop2, win, dsp_st, dsp_st);
3753		-
3754		- VOP_WIN_SET(vop2, win, y2r_en, vpstate->y2r_en);
3755		- VOP_WIN_SET(vop2, win, r2y_en, vpstate->r2y_en);
3756		- VOP_WIN_SET(vop2, win, csc_mode, vpstate->csc_mode);
3757		-
3758		- if (win->feature & WIN_FEATURE_Y2R_13BIT_DEPTH && !vop2_cluster_window(win))
3759		- VOP_WIN_SET(vop2, win, csc_13bit_en, !!(vpstate->csc_mode & CSC_BT709L_13BIT));
3760		-
3761		- dither_up = vop2_win_dither_up(fb->format->format);
3762		- VOP_WIN_SET(vop2, win, dither_up, dither_up);
3763		-
3764		- VOP_WIN_SET(vop2, win, enable, 1);
3765		- if (vop2_cluster_window(win)) {
3766		- lb_mode = vop2_get_cluster_lb_mode(win, vpstate);
3767		- VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode);
3768		- VOP_CLUSTER_SET(vop2, win, enable, 1);
3769		- }
3770		- if (vcstate->output_if & VOP_OUTPUT_IF_BT1120 \|\|
3771		- vcstate->output_if & VOP_OUTPUT_IF_BT656)
3772		- VOP_WIN_SET(vop2, win, yuv_clip, 1);
3773		- spin_unlock(&vop2->reg_lock);
	5482	+ vop2_win_atomic_update(win, &wsrc, &wdst, pstate);
3774	5483
3775	5484	vop2->is_iommu_needed = true;
3776	5485	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
..	..	@@ -3787,18 +5496,18 @@
3787	5496	planlist->dump_info.pages = pages;
3788	5497	planlist->dump_info.offset = vpstate->offset;
3789	5498	planlist->dump_info.pitches = fb->pitches[0];
3790		- planlist->dump_info.height = actual_h;
3791		- planlist->dump_info.pixel_format = fb->format->format;
3792		- list_add_tail(&planlist->entry, &crtc->vop_dump_list_head);
	5499	+ planlist->dump_info.height = drm_rect_height(psrc) >> 16;
	5500	+ planlist->dump_info.format = fb->format;
	5501	+ list_add_tail(&planlist->entry, &vp->rockchip_crtc.vop_dump_list_head);
3793	5502	vpstate->planlist = planlist;
3794	5503	} else {
3795	5504	DRM_ERROR("can't alloc a node of planlist %p\n", planlist);
3796	5505	return;
3797	5506	}
3798		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
3799		- crtc->vop_dump_times > 0) {
3800		- vop_plane_dump(&planlist->dump_info, crtc->frame_count);
3801		- crtc->vop_dump_times--;
	5507	+ if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	5508	+ vp->rockchip_crtc.vop_dump_times > 0) {
	5509	+ rockchip_drm_dump_plane_buffer(&planlist->dump_info, vp->rockchip_crtc.frame_count);
	5510	+ vp->rockchip_crtc.vop_dump_times--;
3802	5511	}
3803	5512	#endif
3804	5513	}
..	..	@@ -3944,11 +5653,8 @@
3944	5653	if (!vpstate)
3945	5654	return;
3946	5655
3947		- plane->state = &vpstate->base;
3948		- plane->state->plane = plane;
3949		- plane->state->zpos = win->zpos;
3950		- plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE;
3951		- plane->state->rotation = DRM_MODE_ROTATE_0;
	5656	+ __drm_atomic_helper_plane_reset(plane, &vpstate->base);
	5657	+ vpstate->base.zpos = win->zpos;
3952	5658	}
3953	5659
3954	5660	static struct drm_plane_state vop2_atomic_plane_duplicate_state(struct drm_plane plane)
..	..	@@ -4136,6 +5842,192 @@
4136	5842	spin_unlock_irqrestore(&drm->event_lock, flags);
4137	5843	}
4138	5844
	5845	+static bool vop2_crtc_line_flag_irq_is_enabled(struct vop2_video_port *vp)
	5846	+{
	5847	+ struct vop2 *vop2 = vp->vop2;
	5848	+ const struct vop2_data *vop2_data = vop2->data;
	5849	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5850	+ const struct vop_intr *intr = vp_data->intr;
	5851	+ uint32_t line_flag_irq;
	5852	+ unsigned long flags;
	5853	+
	5854	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5855	+ line_flag_irq = VOP_INTR_GET_TYPE(vop2, intr, enable, LINE_FLAG_INTR);
	5856	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5857	+
	5858	+ return !!line_flag_irq;
	5859	+}
	5860	+
	5861	+static void vop2_crtc_line_flag_irq_enable(struct vop2_video_port *vp)
	5862	+{
	5863	+ struct vop2 *vop2 = vp->vop2;
	5864	+ const struct vop2_data *vop2_data = vop2->data;
	5865	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5866	+ const struct vop_intr *intr = vp_data->intr;
	5867	+ unsigned long flags;
	5868	+
	5869	+ if (!vop2->is_enabled)
	5870	+ return;
	5871	+
	5872	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5873	+ VOP_INTR_SET_TYPE(vop2, intr, clear, LINE_FLAG_INTR, 1);
	5874	+ VOP_INTR_SET_TYPE(vop2, intr, enable, LINE_FLAG_INTR, 1);
	5875	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5876	+}
	5877	+
	5878	+static void vop2_crtc_line_flag_irq_disable(struct vop2_video_port *vp)
	5879	+{
	5880	+ struct vop2 *vop2 = vp->vop2;
	5881	+ const struct vop2_data *vop2_data = vop2->data;
	5882	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5883	+ const struct vop_intr *intr = vp_data->intr;
	5884	+ unsigned long flags;
	5885	+
	5886	+ if (!vop2->is_enabled)
	5887	+ return;
	5888	+
	5889	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5890	+ VOP_INTR_SET_TYPE(vop2, intr, enable, LINE_FLAG_INTR, 0);
	5891	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5892	+}
	5893	+
	5894	+static void vop3_mcu_mode_setup(struct drm_crtc *crtc)
	5895	+{
	5896	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5897	+ struct vop2 *vop2 = vp->vop2;
	5898	+
	5899	+ VOP_MODULE_SET(vop2, vp, mcu_type, 1);
	5900	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1);
	5901	+ VOP_MODULE_SET(vop2, vp, mcu_pix_total, vp->mcu_timing.mcu_pix_total);
	5902	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pst, vp->mcu_timing.mcu_cs_pst);
	5903	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pend, vp->mcu_timing.mcu_cs_pend);
	5904	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pst, vp->mcu_timing.mcu_rw_pst);
	5905	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pend, vp->mcu_timing.mcu_rw_pend);
	5906	+}
	5907	+
	5908	+static void vop3_mcu_bypass_mode_setup(struct drm_crtc *crtc)
	5909	+{
	5910	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5911	+ struct vop2 *vop2 = vp->vop2;
	5912	+
	5913	+ VOP_MODULE_SET(vop2, vp, mcu_type, 1);
	5914	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1);
	5915	+ VOP_MODULE_SET(vop2, vp, mcu_pix_total, 53);
	5916	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pst, 6);
	5917	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pend, 48);
	5918	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pst, 12);
	5919	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pend, 30);
	5920	+}
	5921	+
	5922	+static u32 vop3_mode_done(struct vop2_video_port *vp)
	5923	+{
	5924	+ return VOP_MODULE_GET(vp->vop2, vp, out_mode);
	5925	+}
	5926	+
	5927	+static void vop3_set_out_mode(struct drm_crtc *crtc, u32 out_mode)
	5928	+{
	5929	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5930	+ struct vop2 *vop2 = vp->vop2;
	5931	+ int ret;
	5932	+ u32 val;
	5933	+
	5934	+ VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
	5935	+ vop2_cfg_done(crtc);
	5936	+ ret = readx_poll_timeout(vop3_mode_done, vp, val, val == out_mode,
	5937	+ 1000, 500 * 1000);
	5938	+ if (ret)
	5939	+ dev_err(vop2->dev, "wait mode 0x%x timeout\n", out_mode);
	5940	+}
	5941	+
	5942	+static void vop3_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value)
	5943	+{
	5944	+ struct drm_crtc_state *crtc_state;
	5945	+ struct drm_display_mode *adjusted_mode;
	5946	+ struct vop2_video_port *vp;
	5947	+ struct vop2 *vop2;
	5948	+
	5949	+ if (!crtc)
	5950	+ return;
	5951	+
	5952	+ crtc_state = crtc->state;
	5953	+ adjusted_mode = &crtc_state->adjusted_mode;
	5954	+ vp = to_vop2_video_port(crtc);
	5955	+ vop2 = vp->vop2;
	5956	+
	5957	+ /*
	5958	+ * 1.set mcu bypass mode timing.
	5959	+ * 2.set dclk rate to 150M.
	5960	+ */
	5961	+ if ((type == MCU_SETBYPASS) && value) {
	5962	+ vop3_mcu_bypass_mode_setup(crtc);
	5963	+ clk_set_rate(vp->dclk, 150000000);
	5964	+ }
	5965	+
	5966	+ mutex_lock(&vop2->vop2_lock);
	5967	+ if (vop2 && vop2->is_enabled) {
	5968	+ switch (type) {
	5969	+ case MCU_WRCMD:
	5970	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 0);
	5971	+ VOP_MODULE_SET(vop2, vp, mcu_rw_bypass_port, value);
	5972	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 1);
	5973	+ break;
	5974	+ case MCU_WRDATA:
	5975	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 1);
	5976	+ VOP_MODULE_SET(vop2, vp, mcu_rw_bypass_port, value);
	5977	+ break;
	5978	+ case MCU_SETBYPASS:
	5979	+ VOP_MODULE_SET(vop2, vp, mcu_bypass, value ? 1 : 0);
	5980	+ break;
	5981	+ default:
	5982	+ break;
	5983	+ }
	5984	+ }
	5985	+ mutex_unlock(&vop2->vop2_lock);
	5986	+
	5987	+ /*
	5988	+ * 1.restore mcu data mode timing.
	5989	+ * 2.restore dclk rate to crtc_clock.
	5990	+ */
	5991	+ if ((type == MCU_SETBYPASS) && !value) {
	5992	+ vop3_mcu_mode_setup(crtc);
	5993	+ clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	5994	+ }
	5995	+}
	5996	+
	5997	+static int vop2_crtc_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
	5998	+{
	5999	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6000	+ struct vop2 *vop2 = vp->vop2;
	6001	+ unsigned long jiffies_left;
	6002	+ int ret = 0;
	6003	+
	6004	+ if (!vop2->is_enabled)
	6005	+ return -ENODEV;
	6006	+
	6007	+ mutex_lock(&vop2->vop2_lock);
	6008	+
	6009	+ if (vop2_crtc_line_flag_irq_is_enabled(vp)) {
	6010	+ ret = -EBUSY;
	6011	+ goto out;
	6012	+ }
	6013	+
	6014	+ reinit_completion(&vp->line_flag_completion);
	6015	+ vop2_crtc_line_flag_irq_enable(vp);
	6016	+ jiffies_left = wait_for_completion_timeout(&vp->line_flag_completion,
	6017	+ msecs_to_jiffies(mstimeout));
	6018	+ vop2_crtc_line_flag_irq_disable(vp);
	6019	+
	6020	+ if (jiffies_left == 0) {
	6021	+ DRM_DEV_ERROR(vop2->dev, "timeout waiting for lineflag IRQ\n");
	6022	+ ret = -ETIMEDOUT;
	6023	+ goto out;
	6024	+ }
	6025	+
	6026	+out:
	6027	+ mutex_unlock(&vop2->vop2_lock);
	6028	+ return ret;
	6029	+}
	6030	+
4139	6031	static int vop2_crtc_enable_line_flag_event(struct drm_crtc *crtc, uint32_t line)
4140	6032	{
4141	6033	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -4179,21 +6071,150 @@
4179	6071	spin_unlock_irqrestore(&vop2->irq_lock, flags);
4180	6072	}
4181	6073
4182		-
4183		-static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on)
	6074	+static int vop2_crtc_get_inital_acm_info(struct drm_crtc *crtc)
4184	6075	{
4185	6076	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4186	6077	struct vop2 *vop2 = vp->vop2;
	6078	+ struct post_acm *acm = &vp->acm_info;
	6079	+ s16 *lut_y;
	6080	+ s16 *lut_h;
	6081	+ s16 *lut_s;
	6082	+ u32 value;
	6083	+ int i;
	6084	+
	6085	+ value = readl(vop2->acm_regs + RK3528_ACM_CTRL);
	6086	+ acm->acm_enable = value & 0x1;
	6087	+ value = readl(vop2->acm_regs + RK3528_ACM_DELTA_RANGE);
	6088	+ acm->y_gain = value & 0x3ff;
	6089	+ acm->h_gain = (value >> 10) & 0x3ff;
	6090	+ acm->s_gain = (value >> 20) & 0x3ff;
	6091	+
	6092	+ lut_y = &acm->gain_lut_hy[0];
	6093	+ lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
	6094	+ lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
	6095	+ for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
	6096	+ value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
	6097	+ lut_y[i] = value & 0xff;
	6098	+ lut_h[i] = (value >> 8) & 0xff;
	6099	+ lut_s[i] = (value >> 16) & 0xff;
	6100	+ }
	6101	+
	6102	+ lut_y = &acm->gain_lut_hs[0];
	6103	+ lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
	6104	+ lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
	6105	+ for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
	6106	+ value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
	6107	+ lut_y[i] = value & 0xff;
	6108	+ lut_h[i] = (value >> 8) & 0xff;
	6109	+ lut_s[i] = (value >> 16) & 0xff;
	6110	+ }
	6111	+
	6112	+ lut_y = &acm->delta_lut_h[0];
	6113	+ lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
	6114	+ lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
	6115	+ for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
	6116	+ value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
	6117	+ lut_y[i] = value & 0x3ff;
	6118	+ lut_h[i] = (value >> 12) & 0xff;
	6119	+ lut_s[i] = (value >> 20) & 0x3ff;
	6120	+ }
	6121	+
	6122	+ return 0;
	6123	+}
	6124	+
	6125	+static void vop2_crtc_csu_set_rate(struct drm_crtc *crtc)
	6126	+{
	6127	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6128	+ struct vop2 *vop2 = vp->vop2;
	6129	+ unsigned long aclk_rate = 0, dclk_rate = 0;
	6130	+ u32 csu_div = 0;
	6131	+
	6132	+ if (!vop2->csu_aclk)
	6133	+ return;
	6134	+
	6135	+ aclk_rate = clk_get_rate(vop2->aclk);
	6136	+ dclk_rate = clk_get_rate(vp->dclk);
	6137	+ if (!dclk_rate)
	6138	+ return;
	6139	+
	6140	+ /* aclk >= 1/2 * dclk */
	6141	+ csu_div = aclk_rate * 2 / dclk_rate;
	6142	+
	6143	+ rockchip_csu_set_div(vop2->csu_aclk, csu_div);
	6144	+}
	6145	+
	6146	+static int vop2_crtc_loader_protect(struct drm_crtc crtc, bool on, void data)
	6147	+{
	6148	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6149	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	6150	+ struct vop2 *vop2 = vp->vop2;
4187	6151	struct rockchip_drm_private *private = crtc->dev->dev_private;
	6152	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	6153	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	6154	+ struct drm_crtc_state *crtc_state;
	6155	+ struct drm_display_mode *mode;
	6156	+ struct vop2_win win, splice_win;
	6157	+ struct vop2_extend_pll *ext_pll;
	6158	+ struct clk *parent_clk;
	6159	+ const char *clk_name;
4188	6160
4189	6161	if (on == vp->loader_protect)
4190	6162	return 0;
4191	6163
4192	6164	if (on) {
	6165	+ vp->loader_protect = true;
4193	6166	vop2->active_vp_mask \|= BIT(vp->id);
4194	6167	vop2_set_system_status(vop2);
4195	6168	vop2_initial(crtc);
	6169	+ if (crtc->primary) {
	6170	+ win = to_vop2_win(crtc->primary);
	6171	+ if (VOP_WIN_GET(vop2, win, enable)) {
	6172	+ if (win->pd) {
	6173	+ win->pd->ref_count++;
	6174	+ win->pd->vp_mask \|= BIT(vp->id);
	6175	+ }
	6176	+
	6177	+ vp->enabled_win_mask \|= BIT(win->phys_id);
	6178	+ crtc_state = drm_atomic_get_crtc_state(crtc->state->state, crtc);
	6179	+ mode = &crtc_state->adjusted_mode;
	6180	+ if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	6181	+ vcstate->splice_mode = true;
	6182	+ splice_win = vop2_find_win_by_phys_id(vop2,
	6183	+ win->splice_win_id);
	6184	+ splice_win->splice_mode_right = true;
	6185	+ splice_win->left_win = win;
	6186	+ win->splice_win = splice_win;
	6187	+ splice_vp->win_mask \|= BIT(splice_win->phys_id);
	6188	+ splice_win->vp_mask = BIT(splice_vp->id);
	6189	+ vop2->active_vp_mask \|= BIT(splice_vp->id);
	6190	+ vp->enabled_win_mask \|= BIT(splice_win->phys_id);
	6191	+
	6192	+ if (splice_win->pd &&
	6193	+ VOP_WIN_GET(vop2, splice_win, enable)) {
	6194	+ splice_win->pd->ref_count++;
	6195	+ splice_win->pd->vp_mask \|= BIT(splice_vp->id);
	6196	+ }
	6197	+ }
	6198	+ }
	6199	+ }
	6200	+ parent_clk = clk_get_parent(vp->dclk);
	6201	+ clk_name = __clk_get_name(parent_clk);
	6202	+ if (!strcmp(clk_name, "clk_hdmiphy_pixel0")) {
	6203	+ ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
	6204	+ if (ext_pll)
	6205	+ ext_pll->vp_mask \|= BIT(vp->id);
	6206	+ } else if (!strcmp(clk_name, "clk_hdmiphy_pixel1")) {
	6207	+ ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
	6208	+ if (ext_pll)
	6209	+ ext_pll->vp_mask \|= BIT(vp->id);
	6210	+ }
4196	6211	drm_crtc_vblank_on(crtc);
	6212	+ if (is_vop3(vop2)) {
	6213	+ if (vp_data->feature & (VOP_FEATURE_POST_ACM))
	6214	+ vop2_crtc_get_inital_acm_info(crtc);
	6215	+ if (data && (vp_data->feature & VOP_FEATURE_POST_CSC))
	6216	+ memcpy(&vp->csc_info, data, sizeof(struct post_csc));
	6217	+ }
4197	6218	if (private->cubic_lut[vp->id].enable) {
4198	6219	dma_addr_t cubic_lut_mst;
4199	6220	struct loader_cubic_lut *cubic_lut = &private->cubic_lut[vp->id];
..	..	@@ -4201,10 +6222,10 @@
4201	6222	cubic_lut_mst = cubic_lut->offset + private->cubic_lut_dma_addr;
4202	6223	VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
4203	6224	}
4204		- vp->loader_protect = true;
	6225	+
	6226	+ vop2_crtc_csu_set_rate(crtc);
4205	6227	} else {
4206	6228	vop2_crtc_atomic_disable(crtc, NULL);
4207		- vp->loader_protect = false;
4208	6229	}
4209	6230
4210	6231	return 0;
..	..	@@ -4226,6 +6247,10 @@
4226	6247	struct drm_rect src, dest;
4227	6248	struct drm_framebuffer *fb = pstate->fb;
4228	6249	struct drm_format_name_buf format_name;
	6250	+ struct drm_gem_object *obj;
	6251	+ struct rockchip_gem_object *rk_obj;
	6252	+ dma_addr_t fb_addr;
	6253	+
4229	6254	int i;
4230	6255
4231	6256	DEBUG_PRINT(" %s: %s\n", win->name, pstate->crtc ? "ACTIVE" : "DISABLED");
..	..	@@ -4256,8 +6281,10 @@
4256	6281	DEBUG_PRINT("\tdst: pos[%d, %d] rect[%d x %d]\n", dest->x1, dest->y1,
4257	6282	drm_rect_width(dest), drm_rect_height(dest));
4258	6283
4259		- for (i = 0; i < drm_format_num_planes(fb->format->format); i++) {
4260		- dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
	6284	+ for (i = 0; i < fb->format->num_planes; i++) {
	6285	+ obj = fb->obj[0];
	6286	+ rk_obj = to_rockchip_obj(obj);
	6287	+ fb_addr = rk_obj->dma_addr + fb->offsets[0];
4261	6288
4262	6289	DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
4263	6290	i, &fb_addr, fb->pitches[i], fb->offsets[i]);
..	..	@@ -4337,8 +6364,9 @@
4337	6364
4338	6365	/* only need to dump once at first active crtc for vop2 */
4339	6366	for (i = 0; i < vop2_data->nr_vps; i++) {
4340		- if (vop2->vps[i].crtc.state->active) {
4341		- first_active_crtc = &vop2->vps[i].crtc;
	6367	+ if (vop2->vps[i].rockchip_crtc.crtc.state &&
	6368	+ vop2->vps[i].rockchip_crtc.crtc.state->active) {
	6369	+ first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc;
4342	6370	break;
4343	6371	}
4344	6372	}
..	..	@@ -4380,8 +6408,9 @@
4380	6408
4381	6409	/* only need to dump once at first active crtc for vop2 */
4382	6410	for (i = 0; i < vop2_data->nr_vps; i++) {
4383		- if (vop2->vps[i].crtc.state->active) {
4384		- first_active_crtc = &vop2->vps[i].crtc;
	6411	+ if (vop2->vps[i].rockchip_crtc.crtc.state &&
	6412	+ vop2->vps[i].rockchip_crtc.crtc.state->active) {
	6413	+ first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc;
4385	6414	break;
4386	6415	}
4387	6416	}
..	..	@@ -4417,7 +6446,7 @@
4417	6446	struct vop2_video_port *vp = &vop2->vps[i];
4418	6447
4419	6448	if (!vp->lut \|\| !vp->gamma_lut_active \|\|
4420		- !vop2->lut_regs \|\| !vp->crtc.state->enable) {
	6449	+ !vop2->lut_regs \|\| !vp->rockchip_crtc.crtc.state->enable) {
4421	6450	DEBUG_PRINT("Video port%d gamma disabled\n", vp->id);
4422	6451	continue;
4423	6452	}
..	..	@@ -4444,7 +6473,7 @@
4444	6473	struct vop2_video_port *vp = &vop2->vps[i];
4445	6474
4446	6475	if ((!vp->cubic_lut_gem_obj && !private->cubic_lut[vp->id].enable) \|\|
4447		- !vp->cubic_lut \|\| !vp->crtc.state->enable) {
	6476	+ !vp->cubic_lut \|\| !vp->rockchip_crtc.crtc.state->enable) {
4448	6477	DEBUG_PRINT("Video port%d cubic lut disabled\n", vp->id);
4449	6478	continue;
4450	6479	}
..	..	@@ -4487,24 +6516,17 @@
4487	6516	goto remove;
4488	6517	}
4489	6518	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4490		- drm_debugfs_vop_add(crtc, vop2->debugfs);
	6519	+ rockchip_drm_add_dump_buffer(crtc, vop2->debugfs);
	6520	+ rockchip_drm_debugfs_add_color_bar(crtc, vop2->debugfs);
4491	6521	#endif
4492	6522	for (i = 0; i < ARRAY_SIZE(vop2_debugfs_files); i++)
4493	6523	vop2->debugfs_files[i].data = vop2;
4494	6524
4495		- ret = drm_debugfs_create_files(vop2->debugfs_files,
4496		- ARRAY_SIZE(vop2_debugfs_files),
4497		- vop2->debugfs,
4498		- minor);
4499		- if (ret) {
4500		- dev_err(vop2->dev, "could not install rockchip_debugfs_list\n");
4501		- goto free;
4502		- }
4503		-
	6525	+ drm_debugfs_create_files(vop2->debugfs_files,
	6526	+ ARRAY_SIZE(vop2_debugfs_files),
	6527	+ vop2->debugfs,
	6528	+ minor);
4504	6529	return 0;
4505		-free:
4506		- kfree(vop2->debugfs_files);
4507		- vop2->debugfs_files = NULL;
4508	6530	remove:
4509	6531	debugfs_remove(vop2->debugfs);
4510	6532	vop2->debugfs = NULL;
..	..	@@ -4512,29 +6534,60 @@
4512	6534	}
4513	6535
4514	6536	static enum drm_mode_status
4515		-vop2_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode,
4516		- int output_type)
	6537	+vop2_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode)
4517	6538	{
	6539	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4518	6540	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4519	6541	struct vop2 *vop2 = vp->vop2;
4520	6542	const struct vop2_data *vop2_data = vop2->data;
4521	6543	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4522	6544	int request_clock = mode->clock;
4523	6545	int clock;
	6546	+ unsigned long aclk_rate;
	6547	+ uint8_t active_vp_mask = vop2->active_vp_mask;
	6548	+
	6549	+ /*
	6550	+ * For RK3588, VP0 and VP1 will be both used in splice mode. All display
	6551	+ * modes of the right VP should be set as invalid when vop2 is working in
	6552	+ * splice mode.
	6553	+ */
	6554	+ if (vp->splice_mode_right)
	6555	+ return MODE_BAD;
	6556	+
	6557	+ if ((active_vp_mask & BIT(ROCKCHIP_VOP_VP1)) && !vcstate->splice_mode &&
	6558	+ mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	6559	+ DRM_DEV_DEBUG(vop2->dev, "can not support resolution %dx%d, vp1 is busy\n",
	6560	+ mode->hdisplay, mode->vdisplay);
	6561	+ return MODE_BAD;
	6562	+ }
4524	6563
4525	6564	if (mode->hdisplay > vp_data->max_output.width)
4526	6565	return MODE_BAD_HVALUE;
4527	6566
4528		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	6567	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| vcstate->output_if & VOP_OUTPUT_IF_BT656)
4529	6568	request_clock *= 2;
4530	6569
4531		- clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
	6570	+ aclk_rate = clk_get_rate(vop2->aclk) / 1000;
	6571	+
	6572	+ if (request_clock > VOP2_MAX_DCLK_RATE && aclk_rate <= VOP2_COMMON_ACLK_RATE)
	6573	+ return MODE_BAD;
	6574	+
	6575	+ if ((request_clock <= VOP2_MAX_DCLK_RATE) &&
	6576	+ (vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") \|\|
	6577	+ vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"))) {
	6578	+ clock = request_clock;
	6579	+ } else {
	6580	+ if (request_clock > VOP2_MAX_DCLK_RATE)
	6581	+ request_clock = request_clock >> 2;
	6582	+ clock = rockchip_drm_dclk_round_rate(vop2->version, vp->dclk,
	6583	+ request_clock * 1000) / 1000;
	6584	+ }
4532	6585
4533	6586	/*
4534	6587	* Hdmi or DisplayPort request a Accurate clock.
4535	6588	*/
4536		- if (output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
4537		- output_type == DRM_MODE_CONNECTOR_DisplayPort)
	6589	+ if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
	6590	+ vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort)
4538	6591	if (clock != request_clock)
4539	6592	return MODE_CLOCK_RANGE;
4540	6593
..	..	@@ -4561,7 +6614,7 @@
4561	6614	struct drm_framebuffer *fb = pstate->fb;
4562	6615	struct drm_rect *dst = &vpstate->dest;
4563	6616	struct drm_rect *src = &vpstate->src;
4564		- int bpp = fb->format->bpp[0];
	6617	+ int bpp = rockchip_drm_get_bpp(fb->format);
4565	6618	int src_width = drm_rect_width(src) >> 16;
4566	6619	int src_height = drm_rect_height(src) >> 16;
4567	6620	int dst_width = drm_rect_width(dst);
..	..	@@ -4570,16 +6623,16 @@
4570	6623	size_t bandwidth;
4571	6624
4572	6625	if (src_width <= 0 \|\| src_height <= 0 \|\| dst_width <= 0 \|\|
4573		- dst_height <= 0)
	6626	+ dst_height <= 0 \|\| !bpp)
4574	6627	return 0;
4575	6628
4576	6629	bandwidth = src_width * bpp / 8;
4577	6630
4578	6631	bandwidth = bandwidth * src_width / dst_width;
4579	6632	bandwidth = bandwidth * src_height / dst_height;
4580		- if (vskiplines == 2)
	6633	+ if (vskiplines == 2 && vpstate->afbc_en == 0)
4581	6634	bandwidth /= 2;
4582		- else if (vskiplines == 4)
	6635	+ else if (vskiplines == 4 && vpstate->afbc_en == 0)
4583	6636	bandwidth /= 4;
4584	6637
4585	6638	return bandwidth;
..	..	@@ -4609,10 +6662,9 @@
4609	6662
4610	6663	static size_t vop2_crtc_bandwidth(struct drm_crtc *crtc,
4611	6664	struct drm_crtc_state *crtc_state,
4612		- size_t *frame_bw_mbyte,
4613		- unsigned int *plane_num_total)
	6665	+ struct dmcfreq_vop_info *vop_bw_info)
4614	6666	{
4615		- struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
	6667	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
4616	6668	uint16_t htotal = adjusted_mode->crtc_htotal;
4617	6669	uint16_t vdisplay = adjusted_mode->crtc_vdisplay;
4618	6670	int clock = adjusted_mode->crtc_clock;
..	..	@@ -4621,44 +6673,49 @@
4621	6673	struct drm_plane_state *pstate;
4622	6674	struct vop2_bandwidth *pbandwidth;
4623	6675	struct drm_plane *plane;
4624		- uint64_t line_bandwidth;
	6676	+ u64 line_bw_mbyte = 0;
4625	6677	int8_t cnt = 0, plane_num = 0;
	6678	+ int i = 0;
4626	6679	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4627	6680	struct vop_dump_list pos, n;
	6681	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
4628	6682	#endif
4629	6683
4630	6684	if (!htotal \|\| !vdisplay)
4631	6685	return 0;
4632	6686
4633	6687	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4634		- if (!crtc->vop_dump_list_init_flag) {
4635		- INIT_LIST_HEAD(&crtc->vop_dump_list_head);
4636		- crtc->vop_dump_list_init_flag = true;
	6688	+ if (!vp->rockchip_crtc.vop_dump_list_init_flag) {
	6689	+ INIT_LIST_HEAD(&vp->rockchip_crtc.vop_dump_list_head);
	6690	+ vp->rockchip_crtc.vop_dump_list_init_flag = true;
4637	6691	}
4638		- list_for_each_entry_safe(pos, n, &crtc->vop_dump_list_head, entry) {
	6692	+ list_for_each_entry_safe(pos, n, &vp->rockchip_crtc.vop_dump_list_head, entry) {
4639	6693	list_del(&pos->entry);
4640	6694	}
4641		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
4642		- crtc->vop_dump_times > 0) {
4643		- crtc->frame_count++;
	6695	+ if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	6696	+ vp->rockchip_crtc.vop_dump_times > 0) {
	6697	+ vp->rockchip_crtc.frame_count++;
4644	6698	}
4645	6699	#endif
4646	6700
4647		- drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
4648		- plane_num++;
	6701	+ for_each_new_plane_in_state(state, plane, pstate, i) {
	6702	+ if (pstate->crtc == crtc)
	6703	+ plane_num++;
	6704	+ }
4649	6705
4650		- if (plane_num_total)
4651		- *plane_num_total += plane_num;
	6706	+ vop_bw_info->plane_num += plane_num;
4652	6707	pbandwidth = kmalloc_array(plane_num, sizeof(*pbandwidth),
4653	6708	GFP_KERNEL);
4654	6709	if (!pbandwidth)
4655	6710	return -ENOMEM;
4656		- drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
4657		- int act_w, act_h, bpp, afbc_fac;
4658	6711
4659		- pstate = drm_atomic_get_new_plane_state(state, plane);
	6712	+ for_each_new_plane_in_state(state, plane, pstate, i) {
	6713	+ int act_w, act_h, bpp, afbc_fac;
	6714	+ int fps = drm_mode_vrefresh(adjusted_mode);
	6715	+
4660	6716	if (!pstate \|\| pstate->crtc != crtc \|\| !pstate->fb)
4661	6717	continue;
	6718	+
4662	6719	/* This is an empirical value, if it's afbc format, the frame buffer size div 2 */
4663	6720	afbc_fac = rockchip_afbc(plane, pstate->fb->modifier) ? 2 : 1;
4664	6721
..	..	@@ -4669,24 +6726,28 @@
4669	6726
4670	6727	act_w = drm_rect_width(&pstate->src) >> 16;
4671	6728	act_h = drm_rect_height(&pstate->src) >> 16;
4672		- bpp = pstate->fb->format->bpp[0];
	6729	+ if (pstate->fb->format->is_yuv && (act_w >= 3840 \|\| act_h >= 3840))
	6730	+ vop_bw_info->plane_num_4k++;
4673	6731
4674		- frame_bw_mbyte += act_w act_h / 1000 * bpp / 8 * adjusted_mode->vrefresh / afbc_fac / 1000;
	6732	+ bpp = rockchip_drm_get_bpp(pstate->fb->format);
	6733	+
	6734	+ vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * bpp / 8 * fps / 1000 / afbc_fac;
4675	6735	}
4676	6736
4677	6737	sort(pbandwidth, cnt, sizeof(pbandwidth[0]), vop2_bandwidth_cmp, NULL);
4678	6738
4679		- line_bandwidth = vop2_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
	6739	+ line_bw_mbyte = vop2_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
4680	6740	kfree(pbandwidth);
4681	6741	/*
4682	6742	* line_bandwidth(MB/s)
4683		- * = line_bandwidth(Byte) / line_time(s)
	6743	+ * = line_bandwidth / line_time
4684	6744	* = line_bandwidth(Byte) * clock(KHZ) / 1000 / htotal
4685	6745	*/
4686		- line_bandwidth *= clock;
4687		- do_div(line_bandwidth, htotal * 1000);
	6746	+ line_bw_mbyte *= clock;
	6747	+ do_div(line_bw_mbyte, htotal * 1000);
	6748	+ vop_bw_info->line_bw_mbyte = line_bw_mbyte;
4688	6749
4689		- return line_bandwidth;
	6750	+ return 0;
4690	6751	}
4691	6752
4692	6753	static void vop2_crtc_close(struct drm_crtc *crtc)
..	..	@@ -4718,6 +6779,44 @@
4718	6779	VOP_MODULE_SET(vop2, vp, edpi_wms_fs, 1);
4719	6780	}
4720	6781
	6782	+static int vop2_crtc_set_color_bar(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode)
	6783	+{
	6784	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6785	+ struct vop2 *vop2 = vp->vop2;
	6786	+ int ret = 0;
	6787	+
	6788	+ if (!crtc->state->active) {
	6789	+ DRM_INFO("Video port%d disabled\n", vp->id);
	6790	+ return -EINVAL;
	6791	+ }
	6792	+
	6793	+ switch (mode) {
	6794	+ case ROCKCHIP_COLOR_BAR_OFF:
	6795	+ DRM_INFO("disable color bar in VP%d\n", vp->id);
	6796	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 0);
	6797	+ vop2_cfg_done(crtc);
	6798	+ break;
	6799	+ case ROCKCHIP_COLOR_BAR_HORIZONTAL:
	6800	+ DRM_INFO("enable horizontal color bar in VP%d\n", vp->id);
	6801	+ VOP_MODULE_SET(vop2, vp, color_bar_mode, 0);
	6802	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 1);
	6803	+ vop2_cfg_done(crtc);
	6804	+ break;
	6805	+ case ROCKCHIP_COLOR_BAR_VERTICAL:
	6806	+ DRM_INFO("enable vertical color bar in VP%d\n", vp->id);
	6807	+ VOP_MODULE_SET(vop2, vp, color_bar_mode, 1);
	6808	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 1);
	6809	+ vop2_cfg_done(crtc);
	6810	+ break;
	6811	+ default:
	6812	+ DRM_INFO("Unsupported color bar mode\n");
	6813	+ ret = -EINVAL;
	6814	+ break;
	6815	+ }
	6816	+
	6817	+ return ret;
	6818	+}
	6819	+
4721	6820	static const struct rockchip_crtc_funcs private_crtc_funcs = {
4722	6821	.loader_protect = vop2_crtc_loader_protect,
4723	6822	.cancel_pending_vblank = vop2_crtc_cancel_pending_vblank,
..	..	@@ -4725,10 +6824,13 @@
4725	6824	.debugfs_dump = vop2_crtc_debugfs_dump,
4726	6825	.regs_dump = vop2_crtc_regs_dump,
4727	6826	.active_regs_dump = vop2_crtc_active_regs_dump,
4728		- .mode_valid = vop2_crtc_mode_valid,
4729	6827	.bandwidth = vop2_crtc_bandwidth,
4730	6828	.crtc_close = vop2_crtc_close,
4731	6829	.te_handler = vop2_crtc_te_handler,
	6830	+ .crtc_send_mcu_cmd = vop3_crtc_send_mcu_cmd,
	6831	+ .wait_vact_end = vop2_crtc_wait_vact_end,
	6832	+ .crtc_standby = vop2_crtc_standby,
	6833	+ .crtc_set_color_bar = vop2_crtc_set_color_bar,
4732	6834	};
4733	6835
4734	6836	static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
..	..	@@ -4736,60 +6838,115 @@
4736	6838	struct drm_display_mode *adj_mode)
4737	6839	{
4738	6840	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6841	+ struct vop2 *vop2 = vp->vop2;
	6842	+ struct drm_connector *connector;
	6843	+ struct drm_connector_list_iter conn_iter;
	6844	+ struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
	6845	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(new_crtc_state);
	6846	+
	6847	+ /*
	6848	+ * For RK3568 and RK3588, the hactive of video timing must
	6849	+ * be 4-pixel aligned.
	6850	+ */
	6851	+ if (vop2->version == VOP_VERSION_RK3568 \|\| vop2->version == VOP_VERSION_RK3588) {
	6852	+ if (adj_mode->hdisplay % 4) {
	6853	+ u16 old_hdisplay = adj_mode->hdisplay;
	6854	+ u16 align;
	6855	+
	6856	+ align = 4 - (adj_mode->hdisplay % 4);
	6857	+ adj_mode->hdisplay += align;
	6858	+ adj_mode->hsync_start += align;
	6859	+ adj_mode->hsync_end += align;
	6860	+ adj_mode->htotal += align;
	6861	+
	6862	+ DRM_WARN("VP%d: hactive need to be aligned with 4-pixel, %d -> %d\n",
	6863	+ vp->id, old_hdisplay, adj_mode->hdisplay);
	6864	+ }
	6865	+ }
4739	6866
4740	6867	drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V \| CRTC_STEREO_DOUBLE);
4741	6868
4742		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	6869	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| vcstate->output_if & VOP_OUTPUT_IF_BT656)
4743	6870	adj_mode->crtc_clock *= 2;
4744	6871
4745		- adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
4746		- adj_mode->crtc_clock * 1000), 1000);
	6872	+ /*
	6873	+ * For RK3528, the path of CVBS output is like:
	6874	+ * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
	6875	+ * The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs.
	6876	+ */
	6877	+ if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656)
	6878	+ adj_mode->crtc_clock *= 4;
4747	6879
	6880	+ if (vp->mcu_timing.mcu_pix_total)
	6881	+ adj_mode->crtc_clock = rockchip_drm_get_cycles_per_pixel(vcstate->bus_format)
	6882	+ (vp->mcu_timing.mcu_pix_total + 1);
	6883	+
	6884	+ drm_connector_list_iter_begin(crtc->dev, &conn_iter);
	6885	+ drm_for_each_connector_iter(connector, &conn_iter) {
	6886	+ if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) &&
	6887	+ ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) \|\|
	6888	+ (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))) {
	6889	+ drm_connector_list_iter_end(&conn_iter);
	6890	+ return true;
	6891	+ }
	6892	+ }
	6893	+ drm_connector_list_iter_end(&conn_iter);
	6894	+
	6895	+ if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) {
	6896	+ adj_mode->crtc_clock = rockchip_drm_dclk_round_rate(vop2->version, vp->dclk,
	6897	+ adj_mode->crtc_clock * 1000);
	6898	+ adj_mode->crtc_clock = DIV_ROUND_UP(adj_mode->crtc_clock, 1000);
	6899	+ }
4748	6900	return true;
4749	6901	}
4750	6902
4751		-static void vop2_dither_setup(struct drm_crtc *crtc)
	6903	+static void vop2_dither_setup(struct rockchip_crtc_state vcstate, struct drm_crtc crtc)
4752	6904	{
4753		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4754	6905	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4755	6906	struct vop2 *vop2 = vp->vop2;
	6907	+ bool pre_dither_down_en = false;
4756	6908
4757	6909	switch (vcstate->bus_format) {
4758	6910	case MEDIA_BUS_FMT_RGB565_1X16:
4759	6911	VOP_MODULE_SET(vop2, vp, dither_down_en, 1);
4760	6912	VOP_MODULE_SET(vop2, vp, dither_down_mode, RGB888_TO_RGB565);
4761		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
	6913	+ pre_dither_down_en = true;
4762	6914	break;
4763	6915	case MEDIA_BUS_FMT_RGB666_1X18:
4764	6916	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
4765	6917	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
4766		- case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
4767	6918	VOP_MODULE_SET(vop2, vp, dither_down_en, 1);
4768	6919	VOP_MODULE_SET(vop2, vp, dither_down_mode, RGB888_TO_RGB666);
4769		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
	6920	+ pre_dither_down_en = true;
4770	6921	break;
	6922	+ case MEDIA_BUS_FMT_YUYV8_1X16:
4771	6923	case MEDIA_BUS_FMT_YUV8_1X24:
4772	6924	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
4773	6925	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4774		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
	6926	+ pre_dither_down_en = true;
4775	6927	break;
	6928	+ case MEDIA_BUS_FMT_YUYV10_1X20:
4776	6929	case MEDIA_BUS_FMT_YUV10_1X30:
4777	6930	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
4778	6931	case MEDIA_BUS_FMT_RGB101010_1X30:
4779	6932	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4780		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 0);
	6933	+ pre_dither_down_en = false;
4781	6934	break;
4782		- case MEDIA_BUS_FMT_SRGB888_3X8:
4783		- case MEDIA_BUS_FMT_SRGB888_DUMMY_4X8:
	6935	+ case MEDIA_BUS_FMT_RGB888_3X8:
	6936	+ case MEDIA_BUS_FMT_RGB888_DUMMY_4X8:
4784	6937	case MEDIA_BUS_FMT_RGB888_1X24:
4785	6938	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
4786	6939	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
4787	6940	default:
4788	6941	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4789		- VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
	6942	+ pre_dither_down_en = true;
4790	6943	break;
4791	6944	}
4792	6945
	6946	+ if (is_yuv_output(vcstate->bus_format))
	6947	+ pre_dither_down_en = false;
	6948	+
	6949	+ VOP_MODULE_SET(vop2, vp, pre_dither_down_en, pre_dither_down_en);
4793	6950	VOP_MODULE_SET(vop2, vp, dither_down_sel, DITHER_DOWN_ALLEGRO);
4794	6951	}
4795	6952
..	..	@@ -4799,6 +6956,8 @@
4799	6956	to_rockchip_crtc_state(crtc->state);
4800	6957	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4801	6958	struct vop2 *vop2 = vp->vop2;
	6959	+ const struct vop2_data *vop2_data = vop2->data;
	6960	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4802	6961	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
4803	6962	u16 vtotal = mode->crtc_vtotal;
4804	6963	u16 hdisplay = mode->crtc_hdisplay;
..	..	@@ -4838,8 +6997,16 @@
4838	6997	val = vact_st_f1 << 16 \| vact_end_f1;
4839	6998	VOP_MODULE_SET(vop2, vp, vpost_st_end_f1, val);
4840	6999	}
4841		- VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y,
4842		- is_yuv_output(vcstate->bus_format));
	7000	+
	7001	+ /*
	7002	+ * BCSH[R2Y] -> POST Linebuffer[post scale] -> the background R2Y will be deal by post_dsp_out_r2y
	7003	+ *
	7004	+ * POST Linebuffer[post scale] -> ACM[R2Y] -> the background R2Y will be deal by ACM[R2Y]
	7005	+ */
	7006	+ if (vp_data->feature & VOP_FEATURE_POST_ACM)
	7007	+ VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y, vcstate->yuv_overlay);
	7008	+ else
	7009	+ VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y, is_yuv_output(vcstate->bus_format));
4843	7010	}
4844	7011
4845	7012	/*
..	..	@@ -4866,13 +7033,13 @@
4866	7033	u16 vact_end = vact_st + vdisplay;
4867	7034	u32 htotal_sync = htotal << 16 \| hsync_len;
4868	7035	u32 hactive_st_end = hact_st << 16 \| hact_end;
4869		- u32 vtotal_sync = vtotal << 16 \| vsync_len;
4870	7036	u32 vactive_st_end = vact_st << 16 \| vact_end;
4871	7037	u32 crtc_clock = adjusted_mode->crtc_clock * 100;
4872	7038
4873	7039	if (htotal_sync != VOP_MODULE_GET(vop2, vp, htotal_pw) \|\|
4874	7040	hactive_st_end != VOP_MODULE_GET(vop2, vp, hact_st_end) \|\|
4875		- vtotal_sync != VOP_MODULE_GET(vop2, vp, vtotal_pw) \|\|
	7041	+ vtotal != VOP_MODULE_GET(vop2, vp, dsp_vtotal) \|\|
	7042	+ vsync_len != VOP_MODULE_GET(vop2, vp, dsp_vs_end) \|\|
4876	7043	vactive_st_end != VOP_MODULE_GET(vop2, vp, vact_st_end) \|\|
4877	7044	crtc_clock != clk_get_rate(vp->dclk))
4878	7045	return true;
..	..	@@ -4880,15 +7047,719 @@
4880	7047	return false;
4881	7048	}
4882	7049
	7050	+static int vop2_cru_set_rate(struct vop2_clk if_pixclk, struct vop2_clk if_dclk)
	7051	+{
	7052	+ int ret = 0;
	7053	+
	7054	+ if (if_pixclk) {
	7055	+ ret = clk_set_rate(if_pixclk->hw.clk, if_pixclk->rate);
	7056	+ if (ret < 0) {
	7057	+ DRM_DEV_ERROR(if_pixclk->vop2->dev, "set %s to %ld failed: %d\n",
	7058	+ clk_hw_get_name(&if_pixclk->hw), if_pixclk->rate, ret);
	7059	+ return ret;
	7060	+ }
	7061	+ }
	7062	+
	7063	+ if (if_dclk) {
	7064	+ ret = clk_set_rate(if_dclk->hw.clk, if_dclk->rate);
	7065	+ if (ret < 0)
	7066	+ DRM_DEV_ERROR(if_dclk->vop2->dev, "set %s to %ld failed %d\n",
	7067	+ clk_hw_get_name(&if_dclk->hw), if_dclk->rate, ret);
	7068	+ }
	7069	+
	7070	+ return ret;
	7071	+}
	7072	+
	7073	+static int vop2_set_dsc_clk(struct drm_crtc *crtc, u8 dsc_id)
	7074	+{
	7075	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7076	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7077	+ struct vop2 *vop2 = vp->vop2;
	7078	+ const struct vop2_data *vop2_data = vop2->data;
	7079	+ const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id];
	7080	+ struct vop2_clk dsc_txp_clk, dsc_pxl_clk, dsc_cds_clk, dsc_txp_clk_parent;
	7081	+ char clk_name[32];
	7082	+ int ret = 0;
	7083	+
	7084	+ /* set clk parent */
	7085	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	7086	+ dsc_txp_clk = vop2_clk_get(vop2, dsc_data->dsc_txp_clk_src_name);
	7087	+ dsc_txp_clk_parent = vop2_clk_get(vop2, clk_name);
	7088	+ if (!dsc_txp_clk \|\| !dsc_txp_clk_parent) {
	7089	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc clk\n");
	7090	+ return -ENODEV;
	7091	+ }
	7092	+ ret = clk_set_parent(dsc_txp_clk->hw.clk, dsc_txp_clk_parent->hw.clk);
	7093	+ if (ret < 0) {
	7094	+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
	7095	+ __clk_get_name(dsc_txp_clk_parent->hw.clk),
	7096	+ __clk_get_name(dsc_txp_clk->hw.clk), ret);
	7097	+ return ret;
	7098	+ }
	7099	+
	7100	+ /* set dsc txp clk rate */
	7101	+ clk_set_rate(dsc_txp_clk->hw.clk, vcstate->dsc_txp_clk_rate);
	7102	+
	7103	+ /* set dsc pxl clk rate */
	7104	+ dsc_pxl_clk = vop2_clk_get(vop2, dsc_data->dsc_pxl_clk_name);
	7105	+ if (!dsc_pxl_clk) {
	7106	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc_pxl_clk\n");
	7107	+ return -ENODEV;
	7108	+ }
	7109	+ clk_set_rate(dsc_pxl_clk->hw.clk, vcstate->dsc_pxl_clk_rate);
	7110	+
	7111	+ /* set dsc cds clk rate */
	7112	+ dsc_cds_clk = vop2_clk_get(vop2, dsc_data->dsc_cds_clk_name);
	7113	+ if (!dsc_cds_clk) {
	7114	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc_cds_clk\n");
	7115	+ return -ENODEV;
	7116	+ }
	7117	+ clk_set_rate(dsc_cds_clk->hw.clk, vcstate->dsc_cds_clk_rate);
	7118	+
	7119	+ return 0;
	7120	+}
	7121	+
	7122	+static int vop2_calc_if_clk(struct drm_crtc crtc, const struct vop2_connector_if_data if_data,
	7123	+ struct vop2_clk if_pixclk, struct vop2_clk if_dclk, int conn_id)
	7124	+{
	7125	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7126	+ struct vop2 *vop2 = vp->vop2;
	7127	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7128	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7129	+ u64 v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
	7130	+ unsigned long dclk_core_rate, dclk_out_rate = 0;
	7131	+ /conn_dclk = conn_pixclk or conn_dclk = conn_pixclk / 2 /
	7132	+ u64 hdmi_edp_pixclk, hdmi_edp_dclk, mipi_pixclk;
	7133	+ char dclk_core_div_shift = 2;
	7134	+ char K = 1;
	7135	+ char clk_name[32];
	7136	+ struct vop2_clk dclk_core, dclk_out, *dclk;
	7137	+ int ret;
	7138	+ bool dsc_txp_clk_is_biggest = false;
	7139	+ u8 dsc_id = conn_id & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_HDMI0) ? 0 : 1;
	7140	+
	7141	+ dclk_core_div_shift = if_data->post_proc_div_shift;
	7142	+ dclk_core_rate = v_pixclk >> dclk_core_div_shift;
	7143	+
	7144	+ if (!if_dclk && (output_if_is_hdmi(conn_id) \|\| output_if_is_edp(conn_id)))
	7145	+ return -EINVAL;
	7146	+ if ((vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) &&
	7147	+ (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420)) {
	7148	+ DRM_DEV_ERROR(vop2->dev, "Dual channel and YUV420 can't work together\n");
	7149	+ return -EINVAL;
	7150	+ }
	7151	+
	7152	+ if ((vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) \|\|
	7153	+ (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420))
	7154	+ K = 2;
	7155	+
	7156	+ if (output_if_is_hdmi(conn_id)) {
	7157	+ if (vcstate->dsc_enable) {
	7158	+ hdmi_edp_pixclk = vcstate->dsc_cds_clk_rate << 1;
	7159	+ hdmi_edp_dclk = vcstate->dsc_cds_clk_rate;
	7160	+ } else {
	7161	+ hdmi_edp_pixclk = (dclk_core_rate << 1) / K;
	7162	+ hdmi_edp_dclk = dclk_core_rate / K;
	7163	+ }
	7164	+
	7165	+ if_pixclk->rate = hdmi_edp_pixclk;
	7166	+ if_dclk->rate = hdmi_edp_dclk;
	7167	+ } else if (output_if_is_edp(conn_id)) {
	7168	+ hdmi_edp_pixclk = v_pixclk;
	7169	+ do_div(hdmi_edp_pixclk, K);
	7170	+ hdmi_edp_dclk = hdmi_edp_pixclk;
	7171	+
	7172	+ if_pixclk->rate = hdmi_edp_pixclk;
	7173	+ if_dclk->rate = hdmi_edp_dclk;
	7174	+ } else if (output_if_is_dp(conn_id)) {
	7175	+ dclk_out_rate = v_pixclk >> 2;
	7176	+ dclk_out_rate = dclk_out_rate / K;
	7177	+ if_pixclk->rate = dclk_out_rate;
	7178	+ } else if (output_if_is_mipi(conn_id)) {
	7179	+ if (vcstate->dsc_enable)
	7180	+ /* dsc output is 96bit, dsi input is 192 bit */
	7181	+ mipi_pixclk = vcstate->dsc_cds_clk_rate >> 1;
	7182	+ else
	7183	+ mipi_pixclk = dclk_core_rate / K;
	7184	+
	7185	+ dclk_out_rate = dclk_core_rate / K;
	7186	+ if_pixclk->rate = mipi_pixclk;
	7187	+ } else if (output_if_is_dpi(conn_id)) {
	7188	+ if_pixclk->rate = v_pixclk;
	7189	+ }
	7190	+
	7191	+ /*
	7192	+ * RGB/eDP/HDMI: if_pixclk >= dclk_core
	7193	+ * DP: dp_pixclk = dclk_out <= dclk_core
	7194	+ * DSI: mipi_pixclk <= dclk_out <= dclk_core
	7195	+ *
	7196	+ */
	7197	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	7198	+ dclk_core = vop2_clk_get(vop2, clk_name);
	7199	+
	7200	+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
	7201	+ dclk_out = vop2_clk_get(vop2, clk_name);
	7202	+
	7203	+ /*
	7204	+ * HDMI use 1:1 dclk for rgb/yuv444, 1:2 for yuv420 when
	7205	+ * pixclk <= 600
	7206	+ * We want use HDMI PHY clk as dclk source for DP/HDMI.
	7207	+ * The max freq of HDMI PHY CLK is 600 MHZ.
	7208	+ * When used for HDMI, the input freq and v_pixclk must
	7209	+ * keep 1:1 for rgb/yuv444, 1:2 for yuv420
	7210	+ */
	7211	+ if (output_if_is_hdmi(conn_id) \|\| output_if_is_dp(conn_id) \|\| output_if_is_mipi(conn_id)) {
	7212	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	7213	+ dclk = vop2_clk_get(vop2, clk_name);
	7214	+ if (v_pixclk <= (VOP2_MAX_DCLK_RATE * 1000)) {
	7215	+ if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420 \|\|
	7216	+ (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE))
	7217	+ v_pixclk = v_pixclk >> 1;
	7218	+ } else {
	7219	+ v_pixclk = v_pixclk >> 2;
	7220	+ }
	7221	+ clk_set_rate(dclk->hw.clk, v_pixclk);
	7222	+ }
	7223	+
	7224	+ if (vcstate->dsc_enable) {
	7225	+ if ((vcstate->dsc_txp_clk_rate >= dclk_core_rate) &&
	7226	+ (vcstate->dsc_txp_clk_rate >= if_pixclk->rate)) {
	7227	+ dsc_txp_clk_is_biggest = true;
	7228	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	7229	+ vop2_set_dsc_clk(crtc, 0);
	7230	+ vop2_set_dsc_clk(crtc, 1);
	7231	+ } else {
	7232	+ vop2_set_dsc_clk(crtc, dsc_id);
	7233	+ }
	7234	+ }
	7235	+ }
	7236	+
	7237	+ if (dclk_core_rate > if_pixclk->rate) {
	7238	+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
	7239	+ if (output_if_is_mipi(conn_id))
	7240	+ clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
	7241	+ ret = vop2_cru_set_rate(if_pixclk, if_dclk);
	7242	+ } else {
	7243	+ if (output_if_is_mipi(conn_id))
	7244	+ clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
	7245	+ ret = vop2_cru_set_rate(if_pixclk, if_dclk);
	7246	+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
	7247	+ }
	7248	+
	7249	+ if (!dsc_txp_clk_is_biggest && vcstate->dsc_enable) {
	7250	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	7251	+ vop2_set_dsc_clk(crtc, 0);
	7252	+ vop2_set_dsc_clk(crtc, 1);
	7253	+ } else {
	7254	+ vop2_set_dsc_clk(crtc, dsc_id);
	7255	+ }
	7256	+ }
	7257	+
	7258	+ return ret;
	7259	+}
	7260	+
	7261	+static int vop2_calc_dsc_clk(struct drm_crtc *crtc)
	7262	+{
	7263	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7264	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7265	+ struct vop2 *vop2 = vp->vop2;
	7266	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7267	+ u64 v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
	7268	+ u8 k = 1;
	7269	+
	7270	+ if (!vop2->data->nr_dscs) {
	7271	+ DRM_WARN("Unsupported DSC\n");
	7272	+
	7273	+ return 0;
	7274	+ }
	7275	+
	7276	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7277	+ k = 2;
	7278	+
	7279	+ vcstate->dsc_txp_clk_rate = v_pixclk;
	7280	+ do_div(vcstate->dsc_txp_clk_rate, (vcstate->dsc_pixel_num * k));
	7281	+
	7282	+ vcstate->dsc_pxl_clk_rate = v_pixclk;
	7283	+ do_div(vcstate->dsc_pxl_clk_rate, (vcstate->dsc_slice_num * k));
	7284	+
	7285	+ /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel)
	7286	+ * cds_dat_width = 96;
	7287	+ * bits_per_pixel = [8-12];
	7288	+ * As cds clk is div from txp clk and only support 1/2/4 div,
	7289	+ * so when txp_clk is equal to v_pixclk, we set dsc_cds = crtc_clock / 4,
	7290	+ * otherwise dsc_cds = crtc_clock / 8;
	7291	+ */
	7292	+ vcstate->dsc_cds_clk_rate = v_pixclk / (vcstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8);
	7293	+
	7294	+ return 0;
	7295	+}
	7296	+
	7297	+static int vop2_calc_cru_cfg(struct drm_crtc *crtc, int conn_id,
	7298	+ struct vop2_clk if_pixclk, struct vop2_clk if_dclk)
	7299	+{
	7300	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7301	+ struct vop2 *vop2 = vp->vop2;
	7302	+ const struct vop2_connector_if_data *if_data;
	7303	+ struct vop2_clk if_clk_src, if_clk_parent;
	7304	+ char clk_name[32];
	7305	+ int ret;
	7306	+
	7307	+ if (vop2->version != VOP_VERSION_RK3588)
	7308	+ return 0;
	7309	+
	7310	+ if_data = vop2_find_connector_if_data(vop2, conn_id);
	7311	+ if_clk_src = vop2_clk_get(vop2, if_data->clk_src_name);
	7312	+ snprintf(clk_name, sizeof(clk_name), "%s%d", if_data->clk_parent_name, vp->id);
	7313	+ if_clk_parent = vop2_clk_get(vop2, clk_name);
	7314	+ *if_pixclk = vop2_clk_get(vop2, if_data->pixclk_name);
	7315	+ *if_dclk = vop2_clk_get(vop2, if_data->dclk_name);
	7316	+ if (!(*if_pixclk) \|\| !if_clk_parent) {
	7317	+ DRM_DEV_ERROR(vop2->dev, "failed to get connector interface clk\n");
	7318	+ return -ENODEV;
	7319	+ }
	7320	+
	7321	+ ret = clk_set_parent(if_clk_src->hw.clk, if_clk_parent->hw.clk);
	7322	+ if (ret < 0) {
	7323	+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
	7324	+ __clk_get_name(if_clk_parent->hw.clk),
	7325	+ __clk_get_name(if_clk_src->hw.clk), ret);
	7326	+ return ret;
	7327	+ }
	7328	+
	7329	+ /* HDMI and eDP use independent if_pixclk and if_dclk, and others if_pixclk = if_dclk */
	7330	+ if (output_if_is_hdmi(conn_id) \|\| output_if_is_edp(conn_id))
	7331	+ ret = vop2_calc_if_clk(crtc, if_data, if_pixclk, if_dclk, conn_id);
	7332	+ else
	7333	+ ret = vop2_calc_if_clk(crtc, if_data, *if_pixclk, NULL, conn_id);
	7334	+
	7335	+ return ret;
	7336	+}
	7337	+
	7338	+static void vop2_crtc_load_pps(struct drm_crtc *crtc, u8 dsc_id)
	7339	+{
	7340	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7341	+ struct vop2 *vop2 = vp->vop2;
	7342	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7343	+
	7344	+ struct drm_dsc_picture_parameter_set *pps = &vcstate->pps;
	7345	+ struct drm_dsc_picture_parameter_set config_pps;
	7346	+ int i = 0;
	7347	+ u32 pps_val = (u32 )&config_pps;
	7348	+ u32 offset;
	7349	+ struct vop2_dsc *dsc;
	7350	+
	7351	+ dsc = &vop2->dscs[dsc_id];
	7352	+ offset = dsc->regs->dsc_pps0_3.offset;
	7353	+
	7354	+ memcpy(&config_pps, pps, sizeof(config_pps));
	7355	+
	7356	+ if ((config_pps.pps_3 & 0xf) > dsc->max_linebuf_depth) {
	7357	+ config_pps.pps_3 &= 0xf0;
	7358	+ config_pps.pps_3 \|= dsc->max_linebuf_depth;
	7359	+ DRM_WARN("DSC%d max_linebuf_depth is: %d, current set value is: %d\n",
	7360	+ dsc_id, dsc->max_linebuf_depth, config_pps.pps_3 & 0xf);
	7361	+ }
	7362	+
	7363	+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
	7364	+ config_pps.rc_range_parameters[i] =
	7365	+ (pps->rc_range_parameters[i] >> 3 & 0x1f) \|
	7366	+ ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) \|
	7367	+ ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) \|
	7368	+ ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10);
	7369	+ }
	7370	+
	7371	+ for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++)
	7372	+ vop2_writel(vop2, offset + i * 4, *pps_val++);
	7373	+}
	7374	+
	7375	+static void vop2_crtc_enable_dsc(struct drm_crtc crtc, struct drm_crtc_state old_state, u8 dsc_id)
	7376	+{
	7377	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7378	+ struct vop2 *vop2 = vp->vop2;
	7379	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7380	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7381	+ struct rockchip_dsc_sink_cap *dsc_sink_cap = &vcstate->dsc_sink_cap;
	7382	+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	7383	+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
	7384	+ u16 htotal = adjusted_mode->crtc_htotal;
	7385	+ u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
	7386	+ u16 vdisplay = adjusted_mode->crtc_vdisplay;
	7387	+ u16 vtotal = adjusted_mode->crtc_vtotal;
	7388	+ u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
	7389	+ u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
	7390	+ u16 vact_end = vact_st + vdisplay;
	7391	+ u8 dsc_interface_mode = 0;
	7392	+ struct vop2_dsc *dsc;
	7393	+ struct vop2_clk dsc_cds_clk, dsc_pxl_clk, *dsc_txp_clk;
	7394	+ const struct vop2_data *vop2_data = vop2->data;
	7395	+ const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id];
	7396	+ bool mipi_ds_mode = false;
	7397	+ uint32_t *reg_base = vop2->regs;
	7398	+ u32 offset = 0;
	7399	+
	7400	+ if (!vop2->data->nr_dscs) {
	7401	+ DRM_WARN("Unsupported DSC\n");
	7402	+
	7403	+ return;
	7404	+ }
	7405	+
	7406	+ if (vcstate->dsc_slice_num > dsc_data->max_slice_num)
	7407	+ DRM_ERROR("DSC%d supported max slice is: %d, current is: %d\n",
	7408	+ dsc_data->id, dsc_data->max_slice_num, vcstate->dsc_slice_num);
	7409	+
	7410	+ dsc = &vop2->dscs[dsc_id];
	7411	+ if (dsc->pd) {
	7412	+ dsc->pd->vp_mask = BIT(vp->id);
	7413	+ vop2_power_domain_get(dsc->pd);
	7414	+ }
	7415	+
	7416	+ VOP_MODULE_SET(vop2, dsc, scan_timing_para_imd_en, 1);
	7417	+ VOP_MODULE_SET(vop2, dsc, dsc_port_sel, vp->id);
	7418	+ if (vcstate->output_if & (VOP_OUTPUT_IF_HDMI0 \| VOP_OUTPUT_IF_HDMI1)) {
	7419	+ dsc_interface_mode = VOP_DSC_IF_HDMI;
	7420	+ } else {
	7421	+ mipi_ds_mode = !!(vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE);
	7422	+ if (mipi_ds_mode)
	7423	+ dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE;
	7424	+ else
	7425	+ dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE;
	7426	+ }
	7427	+
	7428	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7429	+ VOP_MODULE_SET(vop2, dsc, dsc_man_mode, 0);
	7430	+ else
	7431	+ VOP_MODULE_SET(vop2, dsc, dsc_man_mode, 1);
	7432	+ dsc_cds_clk = vop2_clk_get(vop2, dsc_data->dsc_cds_clk_name);
	7433	+ dsc_pxl_clk = vop2_clk_get(vop2, dsc_data->dsc_pxl_clk_name);
	7434	+ dsc_txp_clk = vop2_clk_get(vop2, dsc_data->dsc_txp_clk_name);
	7435	+
	7436	+ VOP_MODULE_SET(vop2, dsc, dsc_interface_mode, dsc_interface_mode);
	7437	+ VOP_MODULE_SET(vop2, dsc, dsc_pixel_num, vcstate->dsc_pixel_num >> 1);
	7438	+ VOP_MODULE_SET(vop2, dsc, dsc_txp_clk_div, dsc_txp_clk->div_val);
	7439	+ VOP_MODULE_SET(vop2, dsc, dsc_pxl_clk_div, dsc_pxl_clk->div_val);
	7440	+ VOP_MODULE_SET(vop2, dsc, dsc_cds_clk_div, dsc_cds_clk->div_val);
	7441	+ VOP_MODULE_SET(vop2, dsc, dsc_scan_en, !mipi_ds_mode);
	7442	+ VOP_MODULE_SET(vop2, dsc, dsc_halt_en, mipi_ds_mode);
	7443	+
	7444	+ if (!mipi_ds_mode) {
	7445	+ u16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end;
	7446	+ u32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16;
	7447	+ u64 dsc_cds_rate = vcstate->dsc_cds_clk_rate;
	7448	+ u32 v_pixclk_mhz = adjusted_mode->crtc_clock / 1000; /* video timing pixclk */
	7449	+ u32 dly_num, dsc_cds_rate_mhz, val = 0;
	7450	+ struct vop2_clk *dclk_core;
	7451	+ char clk_name[32];
	7452	+ int k = 1;
	7453	+
	7454	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7455	+ k = 2;
	7456	+
	7457	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	7458	+ dclk_core = vop2_clk_get(vop2, clk_name);
	7459	+
	7460	+ if (target_bpp >> 4 < dsc->min_bits_per_pixel)
	7461	+ DRM_ERROR("Unsupported bpp less than: %d\n", dsc->min_bits_per_pixel);
	7462	+
	7463	+ /*
	7464	+ * dly_num = delay_line_num * T(one-line) / T (dsc_cds)
	7465	+ * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz
	7466	+ * T (dsc_cds) = 1 / dsc_cds_rate_mhz
	7467	+ *
	7468	+ * HDMI:
	7469	+ * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay
	7470	+ * delay_line_num = 4 - BPP / 8
	7471	+ * = (64 - target_bpp / 8) / 16
	7472	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	7473	+ *
	7474	+ * MIPI DSI[4320 and 9216 is buffer size for DSC]:
	7475	+ * DSC0:delay_line_num = 4320 * 8 / slince_num / chunk_size;
	7476	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7477	+ * DSC1:delay_line_num = 9216 * 2 / slince_num / chunk_size;
	7478	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7479	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num
	7480	+ */
	7481	+ do_div(dsc_cds_rate, 1000000); /* hz to Mhz */
	7482	+ dsc_cds_rate_mhz = dsc_cds_rate;
	7483	+ dsc_hsync = hsync_len / 2;
	7484	+ if (dsc_interface_mode == VOP_DSC_IF_HDMI) {
	7485	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	7486	+ } else {
	7487	+ int dsc_buf_size = dsc->id == 0 ? 4320 * 8 : 9216 * 2;
	7488	+ int delay_line_num = dsc_buf_size / vcstate->dsc_slice_num / be16_to_cpu(vcstate->pps.chunk_size);
	7489	+
	7490	+ delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7491	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num;
	7492	+
	7493	+ /* The dsc mipi video mode dsc_hsync minimum size is 8 pixels */
	7494	+ if (dsc_hsync < 8)
	7495	+ dsc_hsync = 8;
	7496	+ }
	7497	+ VOP_MODULE_SET(vop2, dsc, dsc_init_dly_mode, 0);
	7498	+ VOP_MODULE_SET(vop2, dsc, dsc_init_dly_num, dly_num);
	7499	+ /*
	7500	+ * htotal / dclk_core = dsc_htotal /cds_clk
	7501	+ *
	7502	+ * dclk_core = DCLK / (1 << dclk_core->div_val)
	7503	+ * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val)
	7504	+ * txp_clk = DCLK / (1 << dsc_txp_clk->div_val)
	7505	+ *
	7506	+ * dsc_htotal = htotal * (1 << dclk_core->div_val) /
	7507	+ ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val))
	7508	+ */
	7509	+ dsc_htotal = htotal * (1 << dclk_core->div_val) /
	7510	+ ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val));
	7511	+ val = dsc_htotal << 16 \| dsc_hsync;
	7512	+ VOP_MODULE_SET(vop2, dsc, dsc_htotal_pw, val);
	7513	+
	7514	+ dsc_hact_st = hact_st / 2;
	7515	+ dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st;
	7516	+ val = dsc_hact_end << 16 \| dsc_hact_st;
	7517	+ VOP_MODULE_SET(vop2, dsc, dsc_hact_st_end, val);
	7518	+
	7519	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, vtotal);
	7520	+ VOP_MODULE_SET(vop2, dsc, dsc_vs_end, vsync_len);
	7521	+ VOP_MODULE_SET(vop2, dsc, dsc_vact_st_end, vact_end << 16 \| vact_st);
	7522	+ }
	7523	+
	7524	+ VOP_MODULE_SET(vop2, dsc, rst_deassert, 1);
	7525	+ udelay(10);
	7526	+ /* read current dsc core register and backup to regsbak */
	7527	+ offset = dsc->regs->dsc_en.offset;
	7528	+ vop2->regsbak[offset >> 2] = reg_base[offset >> 2];
	7529	+
	7530	+ VOP_MODULE_SET(vop2, dsc, dsc_en, 1);
	7531	+ vop2_crtc_load_pps(crtc, dsc_id);
	7532	+
	7533	+ VOP_MODULE_SET(vop2, dsc, dsc_rbit, 1);
	7534	+ VOP_MODULE_SET(vop2, dsc, dsc_rbyt, 0);
	7535	+ VOP_MODULE_SET(vop2, dsc, dsc_flal, 1);
	7536	+ VOP_MODULE_SET(vop2, dsc, dsc_mer, 1);
	7537	+ VOP_MODULE_SET(vop2, dsc, dsc_epb, 0);
	7538	+ VOP_MODULE_SET(vop2, dsc, dsc_epl, 1);
	7539	+ VOP_MODULE_SET(vop2, dsc, dsc_nslc, ilog2(vcstate->dsc_slice_num));
	7540	+ VOP_MODULE_SET(vop2, dsc, dsc_sbo, 1);
	7541	+ VOP_MODULE_SET(vop2, dsc, dsc_ifep, dsc_sink_cap->version_minor == 2 ? 1 : 0);
	7542	+ VOP_MODULE_SET(vop2, dsc, dsc_pps_upd, 1);
	7543	+
	7544	+ DRM_DEV_INFO(vop2->dev, "DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n",
	7545	+ dsc->id,
	7546	+ vcstate->dsc_txp_clk_rate, dsc_txp_clk->div_val,
	7547	+ vcstate->dsc_pxl_clk_rate, dsc_pxl_clk->div_val,
	7548	+ vcstate->dsc_cds_clk_rate, dsc_cds_clk->div_val);
	7549	+
	7550	+ dsc->attach_vp_id = vp->id;
	7551	+ dsc->enabled = true;
	7552	+}
	7553	+
	7554	+static inline bool vop2_mark_as_left_panel(struct rockchip_crtc_state *vcstate, u32 output_if)
	7555	+{
	7556	+ return vcstate->output_if_left_panel & output_if;
	7557	+}
	7558	+
	7559	+static void vop2_setup_dual_channel_if(struct drm_crtc *crtc)
	7560	+{
	7561	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7562	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7563	+ struct vop2 *vop2 = vp->vop2;
	7564	+
	7565	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE) {
	7566	+ VOP_CTRL_SET(vop2, lvds_dual_en, 1);
	7567	+ VOP_CTRL_SET(vop2, lvds_dual_mode, 0);
	7568	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
	7569	+ VOP_CTRL_SET(vop2, lvds_dual_channel_swap, 1);
	7570	+ return;
	7571	+ }
	7572	+
	7573	+ VOP_MODULE_SET(vop2, vp, dual_channel_en, 1);
	7574	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
	7575	+ VOP_MODULE_SET(vop2, vp, dual_channel_swap, 1);
	7576	+
	7577	+ if (vcstate->output_if & VOP_OUTPUT_IF_DP1 &&
	7578	+ !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_DP1))
	7579	+ VOP_CTRL_SET(vop2, dp_dual_en, 1);
	7580	+ else if (vcstate->output_if & VOP_OUTPUT_IF_eDP1 &&
	7581	+ !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_eDP1))
	7582	+ VOP_CTRL_SET(vop2, edp_dual_en, 1);
	7583	+ else if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1 &&
	7584	+ !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_HDMI1))
	7585	+ VOP_CTRL_SET(vop2, hdmi_dual_en, 1);
	7586	+ else if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1 &&
	7587	+ !vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_MIPI1))
	7588	+ VOP_CTRL_SET(vop2, mipi_dual_en, 1);
	7589	+ else if (vcstate->output_if & VOP_OUTPUT_IF_LVDS1) {
	7590	+ VOP_CTRL_SET(vop2, lvds_dual_en, 1);
	7591	+ VOP_CTRL_SET(vop2, lvds_dual_mode, 1);
	7592	+ }
	7593	+}
	7594	+
	7595	+/*
	7596	+ * MIPI port mux on rk3588:
	7597	+ * 0: Video Port2
	7598	+ * 1: Video Port3
	7599	+ * 3: Video Port 1(MIPI1 only)
	7600	+ */
	7601	+static int vop2_get_mipi_port_mux(struct vop2 *vop2, int vp_id)
	7602	+{
	7603	+ if (vop2->version == VOP_VERSION_RK3588) {
	7604	+ if (vp_id == 1)
	7605	+ return 3;
	7606	+ else if (vp_id == 3)
	7607	+ return 1;
	7608	+ else
	7609	+ return 0;
	7610	+ } else {
	7611	+ return vp_id;
	7612	+ }
	7613	+}
	7614	+
	7615	+static u32 vop2_get_hdmi_pol(struct vop2 *vop2, u32 flags)
	7616	+{
	7617	+ u32 val;
	7618	+
	7619	+ if (vop2->version == VOP_VERSION_RK3588) {
	7620	+ val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0;
	7621	+ val \|= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0;
	7622	+ } else {
	7623	+ val = (flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
	7624	+ val \|= (flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
	7625	+ }
	7626	+
	7627	+ return val;
	7628	+}
	7629	+
	7630	+static void vop2_post_color_swap(struct drm_crtc *crtc)
	7631	+{
	7632	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7633	+ struct vop2 *vop2 = vp->vop2;
	7634	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7635	+ u32 output_if = vcstate->output_if;
	7636	+ u32 data_swap = 0;
	7637	+
	7638	+ if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode) \|\|
	7639	+ vop3_output_rb_swap(vcstate->bus_format, vcstate->output_mode))
	7640	+ data_swap = DSP_RB_SWAP;
	7641	+
	7642	+ if (vop2->version == VOP_VERSION_RK3588 &&
	7643	+ (output_if_is_hdmi(output_if) \|\| output_if_is_dp(output_if)) &&
	7644	+ (vcstate->bus_format == MEDIA_BUS_FMT_YUV8_1X24 \|\|
	7645	+ vcstate->bus_format == MEDIA_BUS_FMT_YUV10_1X30))
	7646	+ data_swap \|= DSP_RG_SWAP;
	7647	+
	7648	+ VOP_MODULE_SET(vop2, vp, dsp_data_swap, data_swap);
	7649	+}
	7650	+
	7651	+/*
	7652	+ * For vop3 video port0, if hdr_vivid is not enable, the pipe delay time as follow:
	7653	+ * win_dly + config_win_dly + layer_mix_dly + sdr2hdr_dly + * hdr_mix_dly = config_bg_dly
	7654	+ *
	7655	+ * if hdr_vivid is enable, the hdr layer's pipe delay time as follow:
	7656	+ * win_dly + config_win_dly +hdrvivid_dly + hdr_mix_dly = config_bg_dly
	7657	+ *
	7658	+ * If hdrvivid and sdr2hdr bot enable, the time arrivr hdr_mix should be the same:
	7659	+ * win_dly + config_win_dly0 + hdrvivid_dly = win_dly + config_win_dly1 + laer_mix_dly +
	7660	+ * sdr2hdr_dly
	7661	+ *
	7662	+ * For vop3 video port1, the pipe delay time as follow:
	7663	+ * win_dly + config_win_dly + layer_mix_dly = config_bg_dly
	7664	+ *
	7665	+ * Here, win_dly, layer_mix_dly, sdr2hdr_dly, hdr_mix_dly, hdrvivid_dly is the hardware
	7666	+ * delay cycles. Config_win_dly and config_bg_dly is the register value that we can config.
	7667	+ * Different hdr vivid mode have different hdrvivid_dly. For sdr2hdr_dly, only sde2hdr
	7668	+ * enable, it will delay, otherwise, the sdr2hdr_dly is 0.
	7669	+ *
	7670	+ * For default, the config_win_dly will be 0, it just user to make the pipe to arrive
	7671	+ * hdr_mix at the same time.
	7672	+ */
	7673	+static void vop3_setup_pipe_dly(struct vop2_video_port vp, const struct vop2_zpos vop2_zpos)
	7674	+{
	7675	+ struct vop2 *vop2 = vp->vop2;
	7676	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	7677	+ const struct vop2_zpos *zpos;
	7678	+ struct drm_plane *plane;
	7679	+ struct vop2_plane_state *vpstate;
	7680	+ struct vop2_win *win;
	7681	+ const struct vop2_data *vop2_data = vop2->data;
	7682	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	7683	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7684	+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	7685	+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
	7686	+ int bg_dly = 0x0;
	7687	+ int dly = 0x0;
	7688	+ int hdr_win_dly;
	7689	+ int sdr_win_dly;
	7690	+ int sdr2hdr_dly;
	7691	+ int pre_scan_dly;
	7692	+ int i;
	7693	+
	7694	+ /**
	7695	+ * config bg dly, select the max delay num of hdrvivid and sdr2hdr module
	7696	+ * as the increase value of bg delay num. If hdrvivid and sdr2hdr is not
	7697	+ * work, the default bg_dly is 0x10. and the default win delay num is 0.
	7698	+ */
	7699	+ if ((vp->hdr_en \|\| vp->sdr2hdr_en) &&
	7700	+ (vp->hdrvivid_mode >= 0 && vp->hdrvivid_mode <= SDR2HLG)) {
	7701	+ /* set sdr2hdr_dly to 0 if sdr2hdr is disable */
	7702	+ sdr2hdr_dly = vp->sdr2hdr_en ? vp_data->sdr2hdr_dly : 0;
	7703	+
	7704	+ /* set the max delay pipe's config_win_dly as 0 */
	7705	+ if (vp_data->hdrvivid_dly[vp->hdrvivid_mode] >=
	7706	+ sdr2hdr_dly + vp_data->layer_mix_dly) {
	7707	+ bg_dly = vp_data->win_dly + vp_data->hdrvivid_dly[vp->hdrvivid_mode] +
	7708	+ vp_data->hdr_mix_dly;
	7709	+ hdr_win_dly = 0;
	7710	+ sdr_win_dly = vp_data->hdrvivid_dly[vp->hdrvivid_mode] -
	7711	+ vp_data->layer_mix_dly - sdr2hdr_dly;
	7712	+ } else {
	7713	+ bg_dly = vp_data->win_dly + vp_data->layer_mix_dly + sdr2hdr_dly +
	7714	+ vp_data->hdr_mix_dly;
	7715	+ hdr_win_dly = sdr2hdr_dly + vp_data->layer_mix_dly -
	7716	+ vp_data->hdrvivid_dly[vp->hdrvivid_mode];
	7717	+ sdr_win_dly = 0;
	7718	+ }
	7719	+ } else {
	7720	+ bg_dly = vp_data->win_dly + vp_data->layer_mix_dly + vp_data->hdr_mix_dly;
	7721	+ sdr_win_dly = 0;
	7722	+ }
	7723	+
	7724	+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
	7725	+ pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
	7726	+ VOP_MODULE_SET(vop2, vp, bg_dly, bg_dly);
	7727	+ VOP_MODULE_SET(vop2, vp, pre_scan_htiming, pre_scan_dly);
	7728	+
	7729	+ /**
	7730	+ * config win dly
	7731	+ */
	7732	+ if (!vop2_zpos)
	7733	+ return;
	7734	+
	7735	+ for (i = 0; i < vp->nr_layers; i++) {
	7736	+ zpos = &vop2_zpos[i];
	7737	+ win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
	7738	+ plane = &win->base;
	7739	+ vpstate = to_vop2_plane_state(plane->state);
	7740	+
	7741	+ if ((vp->hdr_en \|\| vp->sdr2hdr_en) &&
	7742	+ (vp->hdrvivid_mode >= 0 && vp->hdrvivid_mode <= SDR2HLG)) {
	7743	+ dly = vpstate->hdr_in ? hdr_win_dly : sdr_win_dly;
	7744	+ }
	7745	+ if (vop2_cluster_window(win))
	7746	+ dly \|= dly << 8;
	7747	+
	7748	+ VOP_CTRL_SET(vop2, win_dly[win->phys_id], dly);
	7749	+ }
	7750	+}
	7751	+
4883	7752	static void vop2_crtc_atomic_enable(struct drm_crtc crtc, struct drm_crtc_state old_state)
4884	7753	{
4885	7754	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7755	+ struct vop2_video_port *splice_vp;
4886	7756	struct vop2 *vop2 = vp->vop2;
4887	7757	const struct vop2_data *vop2_data = vop2->data;
4888	7758	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4889	7759	const struct vop_intr *intr = vp_data->intr;
4890	7760	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4891	7761	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7762	+ struct rockchip_dsc_sink_cap *dsc_sink_cap = &vcstate->dsc_sink_cap;
4892	7763	u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
4893	7764	u16 hdisplay = adjusted_mode->crtc_hdisplay;
4894	7765	u16 htotal = adjusted_mode->crtc_htotal;
..	..	@@ -4900,18 +7771,61 @@
4900	7771	u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
4901	7772	u16 vact_end = vact_st + vdisplay;
4902	7773	bool interlaced = !!(adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
4903		- uint8_t out_mode;
4904	7774	bool dclk_inv, yc_swap = false;
4905	7775	int act_end;
4906	7776	uint32_t val;
	7777	+ char clk_name[32];
	7778	+ struct vop2_clk *if_pixclk = NULL;
	7779	+ struct vop2_clk *if_dclk = NULL;
	7780	+ struct vop2_clk dclk, dclk_out, *dclk_core;
	7781	+ int splice_en = 0;
	7782	+ int port_mux;
	7783	+ int ret;
	7784	+
	7785	+ if (old_state && old_state->self_refresh_active) {
	7786	+ vop2_crtc_atomic_exit_psr(crtc, old_state);
	7787	+
	7788	+ return;
	7789	+ }
4907	7790
4908	7791	vop2->active_vp_mask \|= BIT(vp->id);
4909	7792	vop2_set_system_status(vop2);
4910	7793
4911	7794	vop2_lock(vop2);
4912		- DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
4913		- hdisplay, vdisplay, interlaced ? "i" : "p",
4914		- adjusted_mode->vrefresh, vcstate->output_type, vp->id);
	7795	+ DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x, flag:0x%x) for vp%d dclk: %llu\n",
	7796	+ hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p",
	7797	+ drm_mode_vrefresh(adjusted_mode),
	7798	+ vcstate->output_type, vcstate->output_if, vcstate->output_flags,
	7799	+ vp->id, (unsigned long long)adjusted_mode->crtc_clock * 1000);
	7800	+
	7801	+ if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	7802	+ vcstate->splice_mode = true;
	7803	+ splice_vp = &vop2->vps[vp_data->splice_vp_id];
	7804	+ splice_vp->splice_mode_right = true;
	7805	+ splice_vp->left_vp = vp;
	7806	+ splice_en = 1;
	7807	+ vop2->active_vp_mask \|= BIT(splice_vp->id);
	7808	+ }
	7809	+
	7810	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE)
	7811	+ vcstate->output_flags \|= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
	7812	+
	7813	+ if (vcstate->dsc_enable) {
	7814	+ int k = 1;
	7815	+
	7816	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7817	+ k = 2;
	7818	+
	7819	+ vcstate->dsc_id = vcstate->output_if & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_HDMI0) ? 0 : 1;
	7820	+ vcstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k;
	7821	+ vcstate->dsc_pixel_num = vcstate->dsc_slice_num > 4 ? 4 : vcstate->dsc_slice_num;
	7822	+
	7823	+ vop2_calc_dsc_clk(crtc);
	7824	+ DRM_DEV_INFO(vop2->dev, "Enable DSC%d slice:%dx%d, slice num:%d\n",
	7825	+ vcstate->dsc_id, dsc_sink_cap->slice_width,
	7826	+ dsc_sink_cap->slice_height, vcstate->dsc_slice_num);
	7827	+ }
	7828	+
4915	7829	vop2_initial(crtc);
4916	7830	vcstate->vdisplay = vdisplay;
4917	7831	vcstate->mode_update = vop2_crtc_mode_update(crtc);
..	..	@@ -4922,25 +7836,51 @@
4922	7836	val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
4923	7837	val \|= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
4924	7838
	7839	+ vp->output_if = vcstate->output_if;
	7840	+
4925	7841	if (vcstate->output_if & VOP_OUTPUT_IF_RGB) {
	7842	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7843	+ if (ret < 0)
	7844	+ goto out;
	7845	+
4926	7846	VOP_CTRL_SET(vop2, rgb_en, 1);
4927	7847	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4928		- VOP_GRF_SET(vop2, grf_dclk_inv, dclk_inv);
	7848	+ VOP_CTRL_SET(vop2, rgb_pin_pol, val);
	7849	+ VOP_GRF_SET(vop2, sys_grf, grf_dclk_inv, dclk_inv);
4929	7850	}
4930	7851
4931	7852	if (vcstate->output_if & VOP_OUTPUT_IF_BT1120) {
4932		- VOP_CTRL_SET(vop2, rgb_en, 1);
4933		- VOP_CTRL_SET(vop2, bt1120_en, 1);
	7853	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7854	+ if (ret < 0)
	7855	+ goto out;
	7856	+
	7857	+ if (vop2->version == VOP_VERSION_RK3588) {
	7858	+ VOP_CTRL_SET(vop2, bt1120_en, 3);
	7859	+ } else {
	7860	+ VOP_CTRL_SET(vop2, rgb_en, 1);
	7861	+ VOP_CTRL_SET(vop2, bt1120_en, 1);
	7862	+ }
4934	7863	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4935		- VOP_GRF_SET(vop2, grf_bt1120_clk_inv, !dclk_inv);
	7864	+ VOP_GRF_SET(vop2, sys_grf, grf_bt1120_clk_inv, !dclk_inv);
	7865	+ VOP_CTRL_SET(vop2, bt1120_dclk_pol, !dclk_inv);
4936	7866	yc_swap = vop2_output_yc_swap(vcstate->bus_format);
4937	7867	VOP_CTRL_SET(vop2, bt1120_yc_swap, yc_swap);
4938	7868	}
4939	7869
4940	7870	if (vcstate->output_if & VOP_OUTPUT_IF_BT656) {
4941		- VOP_CTRL_SET(vop2, bt656_en, 1);
	7871	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7872	+ if (ret < 0)
	7873	+ goto out;
	7874	+
	7875	+ if (vop2->version == VOP_VERSION_RK3588) {
	7876	+ VOP_CTRL_SET(vop2, bt656_en, 1);
	7877	+ } else {
	7878	+ VOP_CTRL_SET(vop2, rgb_en, 1);
	7879	+ VOP_CTRL_SET(vop2, bt656_en, 1);
	7880	+ }
4942	7881	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4943		- VOP_GRF_SET(vop2, grf_bt656_clk_inv, !dclk_inv);
	7882	+ VOP_GRF_SET(vop2, sys_grf, grf_bt656_clk_inv, !dclk_inv);
	7883	+ VOP_CTRL_SET(vop2, bt656_dclk_pol, !dclk_inv);
4944	7884	yc_swap = vop2_output_yc_swap(vcstate->bus_format);
4945	7885	VOP_CTRL_SET(vop2, bt656_yc_swap, yc_swap);
4946	7886	}
..	..	@@ -4959,18 +7899,19 @@
4959	7899	VOP_CTRL_SET(vop2, lvds_dclk_pol, dclk_inv);
4960	7900	}
4961	7901
4962		- if (vcstate->output_flags & (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE \|
4963		- ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) {
4964		- VOP_CTRL_SET(vop2, lvds_dual_en, 1);
4965		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
4966		- VOP_CTRL_SET(vop2, lvds_dual_mode, 1);
4967		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
4968		- VOP_CTRL_SET(vop2, lvds_dual_channel_swap, 1);
4969		- }
4970		-
4971	7902	if (vcstate->output_if & VOP_OUTPUT_IF_MIPI0) {
	7903	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_MIPI0, &if_pixclk, &if_dclk);
	7904	+ if (ret < 0)
	7905	+ goto out;
	7906	+ if (if_pixclk)
	7907	+ VOP_CTRL_SET(vop2, mipi0_pixclk_div, if_pixclk->div_val);
	7908	+
	7909	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE)
	7910	+ VOP_CTRL_SET(vop2, mipi0_ds_mode, 1);
	7911	+
	7912	+ port_mux = vop2_get_mipi_port_mux(vop2, vp_data->id);
4972	7913	VOP_CTRL_SET(vop2, mipi0_en, 1);
4973		- VOP_CTRL_SET(vop2, mipi0_mux, vp_data->id);
	7914	+ VOP_CTRL_SET(vop2, mipi0_mux, port_mux);
4974	7915	VOP_CTRL_SET(vop2, mipi_pin_pol, val);
4975	7916	VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
4976	7917	if (vcstate->hold_mode) {
..	..	@@ -4980,8 +7921,19 @@
4980	7921	}
4981	7922
4982	7923	if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1) {
	7924	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_MIPI1, &if_pixclk, &if_dclk);
	7925	+ if (ret < 0)
	7926	+ goto out;
	7927	+ if (if_pixclk)
	7928	+ VOP_CTRL_SET(vop2, mipi1_pixclk_div, if_pixclk->div_val);
	7929	+
	7930	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE)
	7931	+ VOP_CTRL_SET(vop2, mipi1_ds_mode, 1);
	7932	+
	7933	+ port_mux = vop2_get_mipi_port_mux(vop2, vp_data->id);
	7934	+
4983	7935	VOP_CTRL_SET(vop2, mipi1_en, 1);
4984		- VOP_CTRL_SET(vop2, mipi1_mux, vp_data->id);
	7936	+ VOP_CTRL_SET(vop2, mipi1_mux, port_mux);
4985	7937	VOP_CTRL_SET(vop2, mipi_pin_pol, val);
4986	7938	VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
4987	7939	if (vcstate->hold_mode) {
..	..	@@ -4990,41 +7942,79 @@
4990	7942	}
4991	7943	}
4992	7944
4993		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
4994		- VOP_MODULE_SET(vop2, vp, mipi_dual_en, 1);
4995		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
4996		- VOP_MODULE_SET(vop2, vp, mipi_dual_channel_swap, 1);
4997		- }
	7945	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE \|\|
	7946	+ vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE)
	7947	+ vop2_setup_dual_channel_if(crtc);
4998	7948
4999	7949	if (vcstate->output_if & VOP_OUTPUT_IF_eDP0) {
	7950	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP0, &if_pixclk, &if_dclk);
	7951	+ if (ret < 0)
	7952	+ goto out;
	7953	+ if (if_pixclk && if_dclk) {
	7954	+ VOP_CTRL_SET(vop2, edp0_pixclk_div, if_pixclk->div_val);
	7955	+ VOP_CTRL_SET(vop2, edp0_dclk_div, if_dclk->div_val);
	7956	+ }
	7957	+
5000	7958	VOP_CTRL_SET(vop2, edp0_en, 1);
5001	7959	VOP_CTRL_SET(vop2, edp0_mux, vp_data->id);
5002	7960	VOP_CTRL_SET(vop2, edp_pin_pol, val);
5003	7961	VOP_CTRL_SET(vop2, edp_dclk_pol, dclk_inv);
	7962	+ VOP_GRF_SET(vop2, grf, grf_edp0_en, 1);
5004	7963	}
5005	7964
5006	7965	if (vcstate->output_if & VOP_OUTPUT_IF_eDP1) {
	7966	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP1, &if_pixclk, &if_dclk);
	7967	+ if (ret < 0)
	7968	+ goto out;
	7969	+ if (if_pixclk && if_dclk) {
	7970	+ VOP_CTRL_SET(vop2, edp1_pixclk_div, if_pixclk->div_val);
	7971	+ VOP_CTRL_SET(vop2, edp1_dclk_div, if_dclk->div_val);
	7972	+ }
	7973	+
5007	7974	VOP_CTRL_SET(vop2, edp1_en, 1);
5008	7975	VOP_CTRL_SET(vop2, edp1_mux, vp_data->id);
5009	7976	VOP_CTRL_SET(vop2, edp_pin_pol, val);
5010	7977	VOP_CTRL_SET(vop2, edp_dclk_pol, dclk_inv);
	7978	+ VOP_GRF_SET(vop2, grf, grf_edp1_en, 1);
5011	7979	}
5012	7980
5013	7981	if (vcstate->output_if & VOP_OUTPUT_IF_DP0) {
	7982	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_DP0, &if_pixclk, &if_dclk);
	7983	+ if (ret < 0)
	7984	+ goto out;
5014	7985	VOP_CTRL_SET(vop2, dp0_en, 1);
5015	7986	VOP_CTRL_SET(vop2, dp0_mux, vp_data->id);
5016		- VOP_CTRL_SET(vop2, dp_dclk_pol, 0);
5017		- VOP_CTRL_SET(vop2, dp_pin_pol, val);
	7987	+ VOP_CTRL_SET(vop2, dp0_dclk_pol, 0);
	7988	+ VOP_CTRL_SET(vop2, dp0_pin_pol, val);
5018	7989	}
5019	7990
5020	7991	if (vcstate->output_if & VOP_OUTPUT_IF_DP1) {
	7992	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_DP0, &if_pixclk, &if_dclk);
	7993	+ if (ret < 0)
	7994	+ goto out;
	7995	+
5021	7996	VOP_CTRL_SET(vop2, dp1_en, 1);
5022	7997	VOP_CTRL_SET(vop2, dp1_mux, vp_data->id);
5023		- VOP_CTRL_SET(vop2, dp_dclk_pol, 0);
5024		- VOP_CTRL_SET(vop2, dp_pin_pol, val);
	7998	+ VOP_CTRL_SET(vop2, dp1_dclk_pol, 0);
	7999	+ VOP_CTRL_SET(vop2, dp1_pin_pol, val);
5025	8000	}
5026	8001
5027	8002	if (vcstate->output_if & VOP_OUTPUT_IF_HDMI0) {
	8003	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_HDMI0, &if_pixclk, &if_dclk);
	8004	+ if (ret < 0)
	8005	+ goto out;
	8006	+ if (if_pixclk && if_dclk) {
	8007	+ VOP_CTRL_SET(vop2, hdmi0_pixclk_div, if_pixclk->div_val);
	8008	+ VOP_CTRL_SET(vop2, hdmi0_dclk_div, if_dclk->div_val);
	8009	+ }
	8010	+
	8011	+ if (vcstate->dsc_enable)
	8012	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 1);
	8013	+
	8014	+ val = vop2_get_hdmi_pol(vop2, adjusted_mode->flags);
	8015	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 1);
	8016	+ VOP_GRF_SET(vop2, vo1_grf, grf_hdmi0_pin_pol, val);
	8017	+
5028	8018	VOP_CTRL_SET(vop2, hdmi0_en, 1);
5029	8019	VOP_CTRL_SET(vop2, hdmi0_mux, vp_data->id);
5030	8020	VOP_CTRL_SET(vop2, hdmi_pin_pol, val);
..	..	@@ -5032,26 +8022,29 @@
5032	8022	}
5033	8023
5034	8024	if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1) {
	8025	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_HDMI1, &if_pixclk, &if_dclk);
	8026	+ if (ret < 0)
	8027	+ goto out;
	8028	+
	8029	+ if (if_pixclk && if_dclk) {
	8030	+ VOP_CTRL_SET(vop2, hdmi1_pixclk_div, if_pixclk->div_val);
	8031	+ VOP_CTRL_SET(vop2, hdmi1_dclk_div, if_dclk->div_val);
	8032	+ }
	8033	+
	8034	+ if (vcstate->dsc_enable)
	8035	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 1);
	8036	+
	8037	+ val = vop2_get_hdmi_pol(vop2, adjusted_mode->flags);
	8038	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 1);
	8039	+ VOP_GRF_SET(vop2, vo1_grf, grf_hdmi1_pin_pol, val);
	8040	+
5035	8041	VOP_CTRL_SET(vop2, hdmi1_en, 1);
5036	8042	VOP_CTRL_SET(vop2, hdmi1_mux, vp_data->id);
5037	8043	VOP_CTRL_SET(vop2, hdmi_pin_pol, val);
5038	8044	VOP_CTRL_SET(vop2, hdmi_dclk_pol, 1);
5039	8045	}
5040	8046
5041		- if ((vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
5042		- !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) \|\|
5043		- vcstate->output_if & VOP_OUTPUT_IF_BT656)
5044		- out_mode = ROCKCHIP_OUT_MODE_P888;
5045		- else
5046		- out_mode = vcstate->output_mode;
5047		- VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
5048		-
5049		- if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
5050		- VOP_MODULE_SET(vop2, vp, dsp_data_swap, DSP_RB_SWAP);
5051		- else
5052		- VOP_MODULE_SET(vop2, vp, dsp_data_swap, 0);
5053		-
5054		- vop2_dither_setup(crtc);
	8047	+ VOP_MODULE_SET(vop2, vp, splice_en, splice_en);
5055	8048
5056	8049	VOP_MODULE_SET(vop2, vp, htotal_pw, (htotal << 16) \| hsync_len);
5057	8050	val = hact_st << 16;
..	..	@@ -5089,7 +8082,13 @@
5089	8082	VOP_INTR_SET(vop2, intr, line_flag_num[0], act_end);
5090	8083	VOP_INTR_SET(vop2, intr, line_flag_num[1], act_end);
5091	8084
5092		- VOP_MODULE_SET(vop2, vp, vtotal_pw, vtotal << 16 \| vsync_len);
	8085	+ VOP_MODULE_SET(vop2, vp, dsp_vtotal, vtotal);
	8086	+ VOP_MODULE_SET(vop2, vp, dsp_vs_end, vsync_len);
	8087	+ /**
	8088	+ * when display interface support vrr, config vtotal valid immediately
	8089	+ */
	8090	+ if (vcstate->max_refresh_rate && vcstate->min_refresh_rate)
	8091	+ VOP_MODULE_SET(vop2, vp, sw_dsp_vtotal_imd, 1);
5093	8092
5094	8093	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK \|\|
5095	8094	vcstate->output_if & VOP_OUTPUT_IF_BT656)
..	..	@@ -5105,10 +8104,65 @@
5105	8104	VOP_MODULE_SET(vop2, vp, dclk_div2_phase_lock, 0);
5106	8105	}
5107	8106
5108		- clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	8107	+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
	8108	+ dclk_out = vop2_clk_get(vop2, clk_name);
	8109	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	8110	+ dclk_core = vop2_clk_get(vop2, clk_name);
	8111	+ if (dclk_out && dclk_core) {
	8112	+ DRM_DEV_INFO(vop2->dev, "%s div: %d %s div: %d\n",
	8113	+ __clk_get_name(dclk_out->hw.clk), dclk_out->div_val,
	8114	+ __clk_get_name(dclk_core->hw.clk), dclk_core->div_val);
	8115	+ VOP_MODULE_SET(vop2, vp, dclk_src_sel, 0);
	8116	+ VOP_MODULE_SET(vop2, vp, dclk_out_div, dclk_out->div_val);
	8117	+ VOP_MODULE_SET(vop2, vp, dclk_core_div, dclk_core->div_val);
	8118	+ }
5109	8119
5110		- vop2_post_config(crtc);
	8120	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	8121	+ dclk = vop2_clk_get(vop2, clk_name);
	8122	+ if (dclk) {
	8123	+ /*
	8124	+ * use HDMI_PHY_PLL as dclk source under 4K@60 if it is available,
	8125	+ * otherwise use system cru as dclk source.
	8126	+ */
	8127	+ ret = vop2_clk_set_parent_extend(vp, vcstate, true);
	8128	+ if (ret < 0)
	8129	+ goto out;
5111	8130
	8131	+ rockchip_drm_dclk_set_rate(vop2->version, vp->dclk, dclk->rate);
	8132	+ DRM_DEV_INFO(vop2->dev, "set %s to %ld, get %ld\n",
	8133	+ __clk_get_name(vp->dclk), dclk->rate, clk_get_rate(vp->dclk));
	8134	+ } else {
	8135	+ rockchip_drm_dclk_set_rate(vop2->version, vp->dclk,
	8136	+ adjusted_mode->crtc_clock * 1000);
	8137	+ }
	8138	+
	8139	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN)
	8140	+ vop2_post_config(crtc);
	8141	+
	8142	+ VOP_MODULE_SET(vop2, vp, almost_full_or_en, 1);
	8143	+ VOP_MODULE_SET(vop2, vp, line_flag_or_en, 1);
	8144	+ if (vcstate->dsc_enable) {
	8145	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	8146	+ vop2_crtc_enable_dsc(crtc, old_state, 0);
	8147	+ vop2_crtc_enable_dsc(crtc, old_state, 1);
	8148	+ } else {
	8149	+ vop2_crtc_enable_dsc(crtc, old_state, vcstate->dsc_id);
	8150	+ }
	8151	+ }
	8152	+ /* For RK3588, the reset value of background is 0xa0080200,
	8153	+ * which will enable background and output a grey image. But
	8154	+ * the reset value is just valid in first frame and disable
	8155	+ * in follow frames. If the panel backlight is valid before
	8156	+ * follow frames. The screen may flick a grey image. To avoid
	8157	+ * this phenomenon appear, setting black background after
	8158	+ * reset vop
	8159	+ */
	8160	+ if (vop2->version == VOP_VERSION_RK3588)
	8161	+ VOP_MODULE_SET(vop2, vp, dsp_background, 0x80000000);
	8162	+ if (is_vop3(vop2))
	8163	+ vop3_setup_pipe_dly(vp, NULL);
	8164	+
	8165	+ vop2_crtc_csu_set_rate(crtc);
5112	8166	vop2_cfg_done(crtc);
5113	8167
5114	8168	/*
..	..	@@ -5128,14 +8182,49 @@
5128	8182	*/
5129	8183	VOP_MODULE_SET(vop2, vp, standby, 0);
5130	8184
5131		- drm_crtc_vblank_on(crtc);
	8185	+ if (vp->mcu_timing.mcu_pix_total) {
	8186	+ vop3_set_out_mode(crtc, vcstate->output_mode);
	8187	+ vop3_mcu_mode_setup(crtc);
	8188	+ }
5132	8189
	8190	+ if (!vp->loader_protect)
	8191	+ vop2_clk_reset(vp->dclk_rst);
	8192	+ if (vcstate->dsc_enable)
	8193	+ rk3588_vop2_dsc_cfg_done(crtc);
	8194	+ drm_crtc_vblank_on(crtc);
5133	8195	/*
5134	8196	* restore the lut table.
5135	8197	*/
5136		- if (vp->gamma_lut_active)
	8198	+ if (vp->gamma_lut_active) {
5137	8199	vop2_crtc_load_lut(crtc);
	8200	+ vop2_cfg_done(crtc);
	8201	+ vop2_wait_for_fs_by_done_bit_status(vp);
	8202	+ }
5138	8203
	8204	+ /*
	8205	+ * In RK3588 VOP, HDMI1/eDP1 MUX1 module's reset signal should be released
	8206	+ * when PD_VOP turn on. If this reset signal is not be released, the HDMI1
	8207	+ * or eDP1 output interface can't work normally.
	8208	+ * However, If the deassert signal want to transfer to HDMI1/eDP1 MUX1 and
	8209	+ * take effect, it need the video port0 dclk's source clk work a few moment.
	8210	+ * In some cases, the video port0 dclk's source clk is disabled(now only the
	8211	+ * hdmi0/1 phy pll as the dclk source parent will appear) after PD_VOP turn
	8212	+ * on, for example, vidoe port0 dclk source select hdmi phy pll. To fix
	8213	+ * this issue, enable video port0 dclk for a few monent when active a video
	8214	+ * port which attach to eDP1/HDMI1.
	8215	+ */
	8216	+ if (vop2->version == VOP_VERSION_RK3588) {
	8217	+ if (vp->id != 0 && (vp->output_if & (VOP_OUTPUT_IF_eDP1 \| VOP_OUTPUT_IF_HDMI1))) {
	8218	+ struct vop2_video_port *vp0 = &vop2->vps[0];
	8219	+
	8220	+ clk_prepare_enable(vp0->dclk);
	8221	+ if (!clk_get_rate(vp0->dclk))
	8222	+ clk_set_rate(vp0->dclk, 148500000);
	8223	+ udelay(20);
	8224	+ clk_disable_unprepare(vp0->dclk);
	8225	+ }
	8226	+ }
	8227	+out:
5139	8228	vop2_unlock(vop2);
5140	8229	}
5141	8230
..	..	@@ -5153,7 +8242,261 @@
5153	8242	static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
5154	8243	struct drm_crtc_state *crtc_state)
5155	8244	{
	8245	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	8246	+ struct vop2_video_port *splice_vp;
	8247	+ struct vop2 *vop2 = vp->vop2;
	8248	+ const struct vop2_data *vop2_data = vop2->data;
	8249	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	8250	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	8251	+ struct rockchip_crtc_state *new_vcstate = to_rockchip_crtc_state(crtc_state);
	8252	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	8253	+
	8254	+ if (vop2_has_feature(vop2, VOP_FEATURE_SPLICE)) {
	8255	+ if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	8256	+ vcstate->splice_mode = true;
	8257	+ splice_vp = &vop2->vps[vp_data->splice_vp_id];
	8258	+ splice_vp->splice_mode_right = true;
	8259	+ splice_vp->left_vp = vp;
	8260	+ }
	8261	+ }
	8262	+
	8263	+ if ((vcstate->request_refresh_rate != new_vcstate->request_refresh_rate) \|\|
	8264	+ crtc_state->active_changed \|\| crtc_state->mode_changed)
	8265	+ vp->refresh_rate_change = true;
	8266	+ else
	8267	+ vp->refresh_rate_change = false;
	8268	+
5156	8269	return 0;
	8270	+}
	8271	+
	8272	+static void vop3_disable_dynamic_hdr(struct vop2_video_port *vp, uint8_t win_phys_id)
	8273	+{
	8274	+ struct vop2 *vop2 = vp->vop2;
	8275	+ struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
	8276	+ struct drm_plane *plane = &win->base;
	8277	+ struct drm_plane_state *pstate = plane->state;
	8278	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	8279	+
	8280	+ VOP_MODULE_SET(vop2, vp, hdr10_en, 0);
	8281	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, 0);
	8282	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_bypass_en, 0);
	8283	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 0);
	8284	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_en, 0);
	8285	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_path_en, 0);
	8286	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_auto_gating_en, 1);
	8287	+
	8288	+ vp->hdr_en = false;
	8289	+ vp->hdr_in = false;
	8290	+ vp->hdr_out = false;
	8291	+ vp->sdr2hdr_en = false;
	8292	+ vpstate->hdr_in = false;
	8293	+ vpstate->hdr2sdr_en = false;
	8294	+}
	8295	+
	8296	+static void vop3_setup_hdrvivid(struct vop2_video_port *vp, uint8_t win_phys_id)
	8297	+{
	8298	+ struct vop2 *vop2 = vp->vop2;
	8299	+ struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
	8300	+ struct drm_plane *plane = &win->base;
	8301	+ struct drm_plane_state *pstate = plane->state;
	8302	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	8303	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
	8304	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8305	+ unsigned long win_mask = vp->win_mask;
	8306	+ int phys_id;
	8307	+ struct hdrvivid_regs *hdrvivid_data;
	8308	+ struct hdr_extend *hdr_data;
	8309	+ struct rockchip_gem_object *lut_gem_obj;
	8310	+ bool have_sdr_layer = false;
	8311	+ uint32_t hdr_mode;
	8312	+ int i;
	8313	+ u32 *tone_lut_kvaddr;
	8314	+ dma_addr_t tone_lut_mst;
	8315	+
	8316	+ vp->hdr_en = false;
	8317	+ vp->hdr_in = false;
	8318	+ vp->hdr_out = false;
	8319	+ vp->sdr2hdr_en = false;
	8320	+ vpstate->hdr_in = false;
	8321	+ vpstate->hdr2sdr_en = false;
	8322	+
	8323	+ hdr_data = (struct hdr_extend *)vcstate->hdr_ext_data->data;
	8324	+ hdrvivid_data = &hdr_data->hdrvivid_data;
	8325	+
	8326	+ hdr_mode = hdrvivid_data->hdr_mode;
	8327	+
	8328	+ if (hdr_mode > SDR2HLG && hdr_mode != SDR2HDR10_USERSPACE &&
	8329	+ hdr_mode != SDR2HLG_USERSPACE) {
	8330	+ DRM_ERROR("Invalid HDR mode:%d, beyond the mode range\n", hdr_mode);
	8331	+ return;
	8332	+ }
	8333	+
	8334	+ /* adjust userspace hdr mode value to kernel value */
	8335	+ if (hdr_mode == SDR2HDR10_USERSPACE)
	8336	+ hdr_mode = SDR2HDR10;
	8337	+ if (hdr_mode == SDR2HLG_USERSPACE)
	8338	+ hdr_mode = SDR2HLG;
	8339	+
	8340	+ if (hdr_mode <= HDR102SDR && vpstate->eotf != HDMI_EOTF_SMPTE_ST2084 && vpstate->eotf != HDMI_EOTF_BT_2100_HLG) {
	8341	+ DRM_ERROR("Invalid HDR mode:%d, mismatch plane eotf:%d\n", hdr_mode,
	8342	+ vpstate->eotf);
	8343	+ return;
	8344	+ }
	8345	+
	8346	+ vp->hdrvivid_mode = hdr_mode;
	8347	+ vcstate->yuv_overlay = false;
	8348	+
	8349	+ if (hdr_mode <= HDR102SDR) {
	8350	+ vp->hdr_en = true;
	8351	+ vp->hdr_in = true;
	8352	+ vpstate->hdr_in = true;
	8353	+ } else {
	8354	+ vp->sdr2hdr_en = true;
	8355	+ }
	8356	+
	8357	+ /*
	8358	+ * To confirm whether need to enable sdr2hdr.
	8359	+ */
	8360	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	8361	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	8362	+ plane = &win->base;
	8363	+ pstate = plane->state;
	8364	+ vpstate = to_vop2_plane_state(pstate);
	8365	+
	8366	+ /* skip inactive plane */
	8367	+ if (!vop2_plane_active(pstate))
	8368	+ continue;
	8369	+
	8370	+ if (vpstate->eotf != HDMI_EOTF_SMPTE_ST2084 &&
	8371	+ vpstate->eotf != HDMI_EOTF_BT_2100_HLG) {
	8372	+ have_sdr_layer = true;
	8373	+ break;
	8374	+ }
	8375	+ }
	8376	+
	8377	+ if (hdr_mode == PQHDR2SDR_WITH_DYNAMIC \|\| hdr_mode == HLG2SDR_WITH_DYNAMIC \|\|
	8378	+ hdr_mode == HLG2SDR_WITHOUT_DYNAMIC \|\| hdr_mode == HDR102SDR) {
	8379	+ vpstate->hdr2sdr_en = true;
	8380	+ } else {
	8381	+ vp->hdr_out = true;
	8382	+ if (have_sdr_layer)
	8383	+ vp->sdr2hdr_en = true;
	8384	+ }
	8385	+
	8386	+ /**
	8387	+ * Config hdr ctrl registers
	8388	+ */
	8389	+ vop2_writel(vop2, RK3528_SDR2HDR_CTRL, hdrvivid_data->sdr2hdr_ctrl);
	8390	+ vop2_writel(vop2, RK3528_HDRVIVID_CTRL, hdrvivid_data->hdrvivid_ctrl);
	8391	+
	8392	+ VOP_MODULE_SET(vop2, vp, hdr10_en, vp->hdr_en);
	8393	+ if (vp->hdr_en) {
	8394	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, (hdr_mode == HDR_BYPASS) ? 0 : 1);
	8395	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_path_mode,
	8396	+ (hdr_mode == HDR102SDR) ? PQHDR2SDR_WITH_DYNAMIC : hdr_mode);
	8397	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_bypass_en, (hdr_mode == HDR_BYPASS) ? 1 : 0);
	8398	+ } else {
	8399	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, 0);
	8400	+ }
	8401	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_en, vp->sdr2hdr_en);
	8402	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_path_en, vp->sdr2hdr_en);
	8403	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_auto_gating_en, vp->sdr2hdr_en ? 0 : 1);
	8404	+
	8405	+ vop2_writel(vop2, RK3528_SDR_CFG_COE0, hdrvivid_data->sdr2hdr_coe0);
	8406	+ vop2_writel(vop2, RK3528_SDR_CFG_COE1, hdrvivid_data->sdr2hdr_coe1);
	8407	+ vop2_writel(vop2, RK3528_SDR_CSC_COE00_01, hdrvivid_data->sdr2hdr_csc_coe00_01);
	8408	+ vop2_writel(vop2, RK3528_SDR_CSC_COE02_10, hdrvivid_data->sdr2hdr_csc_coe02_10);
	8409	+ vop2_writel(vop2, RK3528_SDR_CSC_COE11_12, hdrvivid_data->sdr2hdr_csc_coe11_12);
	8410	+ vop2_writel(vop2, RK3528_SDR_CSC_COE20_21, hdrvivid_data->sdr2hdr_csc_coe20_21);
	8411	+ vop2_writel(vop2, RK3528_SDR_CSC_COE22, hdrvivid_data->sdr2hdr_csc_coe22);
	8412	+
	8413	+ vop2_writel(vop2, RK3528_HDR_PQ_GAMMA, hdrvivid_data->hdr_pq_gamma);
	8414	+ vop2_writel(vop2, RK3528_HLG_RFIX_SCALEFAC, hdrvivid_data->hlg_rfix_scalefac);
	8415	+ vop2_writel(vop2, RK3528_HLG_MAXLUMA, hdrvivid_data->hlg_maxluma);
	8416	+ vop2_writel(vop2, RK3528_HLG_R_TM_LIN2NON, hdrvivid_data->hlg_r_tm_lin2non);
	8417	+
	8418	+ vop2_writel(vop2, RK3528_HDR_CSC_COE00_01, hdrvivid_data->hdr_csc_coe00_01);
	8419	+ vop2_writel(vop2, RK3528_HDR_CSC_COE02_10, hdrvivid_data->hdr_csc_coe02_10);
	8420	+ vop2_writel(vop2, RK3528_HDR_CSC_COE11_12, hdrvivid_data->hdr_csc_coe11_12);
	8421	+ vop2_writel(vop2, RK3528_HDR_CSC_COE20_21, hdrvivid_data->hdr_csc_coe20_21);
	8422	+ vop2_writel(vop2, RK3528_HDR_CSC_COE22, hdrvivid_data->hdr_csc_coe22);
	8423	+
	8424	+ if (!vp->hdr_lut_gem_obj) {
	8425	+ lut_gem_obj = rockchip_gem_create_object(vop2->drm_dev,
	8426	+ RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH * 4, true, 0);
	8427	+ if (IS_ERR(lut_gem_obj)) {
	8428	+ DRM_ERROR("create hdr lut obj failed\n");
	8429	+ return;
	8430	+ }
	8431	+ vp->hdr_lut_gem_obj = lut_gem_obj;
	8432	+ }
	8433	+
	8434	+ tone_lut_kvaddr = (u32 *)vp->hdr_lut_gem_obj->kvaddr;
	8435	+ tone_lut_mst = vp->hdr_lut_gem_obj->dma_addr;
	8436	+
	8437	+ for (i = 0; i < RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH; i++)
	8438	+ *tone_lut_kvaddr++ = hdrvivid_data->tone_sca_axi_tab[i];
	8439	+
	8440	+ VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid - vp->id);
	8441	+ VOP_MODULE_SET(vop2, vp, hdr_lut_mode, 1);
	8442	+ VOP_MODULE_SET(vop2, vp, hdr_lut_mst, tone_lut_mst);
	8443	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 1);
	8444	+ VOP_CTRL_SET(vop2, lut_dma_en, 1);
	8445	+
	8446	+ for (i = 0; i < RK_HDRVIVID_GAMMA_CURVE_LENGTH; i++)
	8447	+ vop2_writel(vop2, RK3528_HDRGAMMA_CURVE + i * 4, hdrvivid_data->hdrgamma_curve[i]);
	8448	+
	8449	+ for (i = 0; i < RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH; i++)
	8450	+ vop2_writel(vop2, RK3528_HDRGAMMA_MDFVALUE + i * 4,
	8451	+ hdrvivid_data->hdrgamma_mdfvalue[i]);
	8452	+
	8453	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_CURVE_LENGTH; i++)
	8454	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_CURVE + i * 4,
	8455	+ hdrvivid_data->sdrinvgamma_curve[i]);
	8456	+
	8457	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH; i++)
	8458	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_STARTIDX + i * 4,
	8459	+ hdrvivid_data->sdrinvgamma_startidx[i]);
	8460	+
	8461	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH; i++)
	8462	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_CHANGEIDX + i * 4,
	8463	+ hdrvivid_data->sdrinvgamma_changeidx[i]);
	8464	+
	8465	+ for (i = 0; i < RK_SDR2HDR_SMGAIN_LENGTH; i++)
	8466	+ vop2_writel(vop2, RK3528_SDR_SMGAIN + i * 4, hdrvivid_data->sdr_smgain[i]);
	8467	+}
	8468	+
	8469	+static void vop3_setup_dynamic_hdr(struct vop2_video_port *vp, uint8_t win_phys_id)
	8470	+{
	8471	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
	8472	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8473	+ struct hdr_extend *hdr_data;
	8474	+ uint32_t hdr_format;
	8475	+
	8476	+ /* If hdr extend data is null, exit hdr mode */
	8477	+ if (!vcstate->hdr_ext_data) {
	8478	+ vop3_disable_dynamic_hdr(vp, win_phys_id);
	8479	+ return;
	8480	+ }
	8481	+
	8482	+ hdr_data = (struct hdr_extend *)vcstate->hdr_ext_data->data;
	8483	+ hdr_format = hdr_data->hdr_type;
	8484	+
	8485	+ switch (hdr_format) {
	8486	+ case HDR_NONE:
	8487	+ case HDR_HDR10:
	8488	+ case HDR_HLGSTATIC:
	8489	+ case HDR_HDRVIVID:
	8490	+ /*
	8491	+ * hdr module support hdr10, hlg, vividhdr
	8492	+ * sdr2hdr module support hdrnone for sdr2hdr
	8493	+ */
	8494	+ vop3_setup_hdrvivid(vp, win_phys_id);
	8495	+ break;
	8496	+ default:
	8497	+ DRM_DEBUG("unsupprot hdr format:%u\n", hdr_format);
	8498	+ break;
	8499	+ }
5157	8500	}
5158	8501
5159	8502	static void vop2_setup_hdr10(struct vop2_video_port *vp, uint8_t win_phys_id)
..	..	@@ -5161,13 +8504,13 @@
5161	8504	struct vop2 *vop2 = vp->vop2;
5162	8505	struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
5163	8506	struct drm_plane *plane = &win->base;
5164		- struct drm_plane_state *pstate = plane->state;
5165		- struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
5166		- struct drm_crtc_state *cstate = vp->crtc.state;
5167		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8507	+ struct drm_plane_state *pstate;
	8508	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
5168	8509	const struct vop2_data *vop2_data = vop2->data;
5169	8510	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
5170	8511	const struct vop_hdr_table *hdr_table = vp_data->hdr_table;
	8512	+ struct rockchip_crtc_state *vcstate;
	8513	+ struct vop2_plane_state *vpstate;
5171	8514	uint32_t lut_mode = VOP2_HDR_LUT_MODE_AHB;
5172	8515	uint32_t sdr2hdr_r2r_mode = 0;
5173	8516	bool hdr_en = 0;
..	..	@@ -5187,14 +8530,27 @@
5187	8530	return;
5188	8531
5189	8532	/*
	8533	+ * right vp share the same crtc/plane state in splice mode
	8534	+ */
	8535	+ if (vp->splice_mode_right) {
	8536	+ vcstate = to_rockchip_crtc_state(vp->left_vp->rockchip_crtc.crtc.state);
	8537	+ pstate = win->left_win->base.state;
	8538	+ } else {
	8539	+ vcstate = to_rockchip_crtc_state(cstate);
	8540	+ pstate = plane->state;
	8541	+ }
	8542	+
	8543	+ vpstate = to_vop2_plane_state(pstate);
	8544	+
	8545	+ /*
5190	8546	* HDR video plane input
5191	8547	*/
5192		- if (vpstate->eotf == SMPTE_ST2084)
	8548	+ if (vpstate->eotf == HDMI_EOTF_SMPTE_ST2084)
5193	8549	hdr_en = 1;
5194	8550
5195	8551	vp->hdr_en = hdr_en;
5196	8552	vp->hdr_in = hdr_en;
5197		- vp->hdr_out = (vcstate->eotf == SMPTE_ST2084) ? true : false;
	8553	+ vp->hdr_out = (vcstate->eotf == HDMI_EOTF_SMPTE_ST2084) ? true : false;
5198	8554
5199	8555	/*
5200	8556	* only laryer0 support hdr2sdr
..	..	@@ -5212,15 +8568,21 @@
5212	8568	*/
5213	8569	for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
5214	8570	win = vop2_find_win_by_phys_id(vop2, phys_id);
5215		- plane = &win->base;
5216		- pstate = plane->state;
5217		- vpstate = to_vop2_plane_state(pstate);
	8571	+ if (vp->splice_mode_right) {
	8572	+ if (win->left_win)
	8573	+ pstate = win->left_win->base.state;
	8574	+ else
	8575	+ pstate = NULL; /* this win is not activated */
	8576	+ } else {
	8577	+ pstate = win->base.state;
	8578	+ }
5218	8579
5219		- /* skip inactive plane */
	8580	+ vpstate = pstate ? to_vop2_plane_state(pstate) : NULL;
	8581	+
5220	8582	if (!vop2_plane_active(pstate))
5221	8583	continue;
5222	8584
5223		- if (vpstate->eotf != SMPTE_ST2084) {
	8585	+ if (vpstate->eotf != HDMI_EOTF_SMPTE_ST2084) {
5224	8586	have_sdr_layer = true;
5225	8587	break;
5226	8588	}
..	..	@@ -5367,7 +8729,15 @@
5367	8729
5368	8730	if (!sub_win) {
5369	8731	/* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
5370		- plane = &main_win->base;
	8732	+
	8733	+ /*
	8734	+ * right cluster share the same plane state in splice mode
	8735	+ */
	8736	+ if (cluster->splice_mode)
	8737	+ plane = &main_win->left_win->base;
	8738	+ else
	8739	+ plane = &main_win->base;
	8740	+
5371	8741	top_win_vpstate = NULL;
5372	8742	bottom_win_vpstate = to_vop2_plane_state(plane->state);
5373	8743	src_glb_alpha_val = 0;
..	..	@@ -5426,25 +8796,35 @@
5426	8796	uint32_t dst_color_ctrl_offset = vop2->data->ctrl->dst_color_ctrl.offset;
5427	8797	uint32_t src_alpha_ctrl_offset = vop2->data->ctrl->src_alpha_ctrl.offset;
5428	8798	uint32_t dst_alpha_ctrl_offset = vop2->data->ctrl->dst_alpha_ctrl.offset;
	8799	+ unsigned long win_mask = vp->win_mask;
5429	8800	const struct vop2_zpos *zpos;
5430		- struct drm_framebuffer *fb;
	8801	+ struct vop2_plane_state *vpstate;
5431	8802	struct vop2_alpha_config alpha_config;
5432	8803	struct vop2_alpha alpha;
5433	8804	struct vop2_win *win;
5434		- struct drm_plane *plane;
5435		- struct vop2_plane_state *vpstate;
	8805	+ struct drm_plane_state *pstate;
	8806	+ struct drm_framebuffer *fb;
5436	8807	int pixel_alpha_en;
5437		- int premulti_en;
	8808	+ int premulti_en = 1;
5438	8809	int mixer_id;
	8810	+ int phys_id;
5439	8811	uint32_t offset;
5440	8812	int i;
5441	8813	bool bottom_layer_alpha_en = false;
5442	8814	u32 dst_global_alpha = 0xff;
5443	8815
5444		- drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
5445		- struct vop2_win *win = to_vop2_win(plane);
	8816	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	8817	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	8818	+ if (win->splice_mode_right)
	8819	+ pstate = win->left_win->base.state;
	8820	+ else
	8821	+ pstate = win->base.state;
5446	8822
5447		- vpstate = to_vop2_plane_state(plane->state);
	8823	+ vpstate = to_vop2_plane_state(pstate);
	8824	+
	8825	+ if (!vop2_plane_active(pstate))
	8826	+ continue;
	8827	+
5448	8828	if (vpstate->zpos == 0 && vpstate->global_alpha != 0xff &&
5449	8829	!vop2_cluster_window(win)) {
5450	8830	/*
..	..	@@ -5454,19 +8834,33 @@
5454	8834	*/
5455	8835	bottom_layer_alpha_en = true;
5456	8836	dst_global_alpha = vpstate->global_alpha;
	8837	+ if (pstate->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
	8838	+ premulti_en = 1;
	8839	+ else
	8840	+ premulti_en = 0;
	8841	+
5457	8842	break;
5458	8843	}
5459	8844	}
5460	8845
5461	8846	mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
	8847	+
	8848	+ if (vop2->version == VOP_VERSION_RK3588 &&
	8849	+ vp->hdr10_at_splice_mode && vp->id == 0)
	8850	+ mixer_id++;/* fixed path for rk3588: layer1 -> hdr10_1 */
	8851	+
5462	8852	alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
5463	8853	for (i = 1; i < vp->nr_layers; i++) {
5464	8854	zpos = &vop2_zpos[i];
5465	8855	win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
5466		- plane = &win->base;
5467		- vpstate = to_vop2_plane_state(plane->state);
5468		- fb = plane->state->fb;
5469		- if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
	8856	+ if (win->splice_mode_right)
	8857	+ pstate = win->left_win->base.state;
	8858	+ else
	8859	+ pstate = win->base.state;
	8860	+
	8861	+ vpstate = to_vop2_plane_state(pstate);
	8862	+ fb = pstate->fb;
	8863	+ if (pstate->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
5470	8864	premulti_en = 1;
5471	8865	else
5472	8866	premulti_en = 0;
..	..	@@ -5496,29 +8890,27 @@
5496	8890	vop2_writel(vop2, dst_color_ctrl_offset + offset, alpha.dst_color_ctrl.val);
5497	8891	vop2_writel(vop2, src_alpha_ctrl_offset + offset, alpha.src_alpha_ctrl.val);
5498	8892	vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
	8893	+ }
5499	8894
5500		- if (i == 1) {
5501		- if (bottom_layer_alpha_en \|\| vp->hdr_en) {
5502		- /* Transfer pixel alpha to hdr mix */
5503		- alpha_config.src_premulti_en = premulti_en;
5504		- alpha_config.dst_premulti_en = true;
5505		- alpha_config.src_pixel_alpha_en = true;
5506		- alpha_config.src_glb_alpha_value = 0xff;
5507		- alpha_config.dst_glb_alpha_value = 0xff;
5508		- vop2_parse_alpha(&alpha_config, &alpha);
	8895	+ if (bottom_layer_alpha_en \|\| vp->hdr_en) {
	8896	+ /* Transfer pixel alpha to hdr mix */
	8897	+ alpha_config.src_premulti_en = premulti_en;
	8898	+ alpha_config.dst_premulti_en = true;
	8899	+ alpha_config.src_pixel_alpha_en = true;
	8900	+ alpha_config.src_glb_alpha_value = 0xff;
	8901	+ alpha_config.dst_glb_alpha_value = 0xff;
	8902	+ vop2_parse_alpha(&alpha_config, &alpha);
5509	8903
5510		- VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl,
5511		- alpha.src_color_ctrl.val);
5512		- VOP_MODULE_SET(vop2, vp, hdr_dst_color_ctrl,
5513		- alpha.dst_color_ctrl.val);
5514		- VOP_MODULE_SET(vop2, vp, hdr_src_alpha_ctrl,
5515		- alpha.src_alpha_ctrl.val);
5516		- VOP_MODULE_SET(vop2, vp, hdr_dst_alpha_ctrl,
5517		- alpha.dst_alpha_ctrl.val);
5518		- } else {
5519		- VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl, 0);
5520		- }
5521		- }
	8904	+ VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl,
	8905	+ alpha.src_color_ctrl.val);
	8906	+ VOP_MODULE_SET(vop2, vp, hdr_dst_color_ctrl,
	8907	+ alpha.dst_color_ctrl.val);
	8908	+ VOP_MODULE_SET(vop2, vp, hdr_src_alpha_ctrl,
	8909	+ alpha.src_alpha_ctrl.val);
	8910	+ VOP_MODULE_SET(vop2, vp, hdr_dst_alpha_ctrl,
	8911	+ alpha.dst_alpha_ctrl.val);
	8912	+ } else {
	8913	+ VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl, 0);
5522	8914	}
5523	8915
5524	8916	/* Transfer pixel alpha value to next mix */
..	..	@@ -5648,7 +9040,7 @@
5648	9040	vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
5649	9041	}
5650	9042
5651		- if (vp_data->feature & VOP_FEATURE_HDR10) {
	9043	+ if (vp_data->feature & (VOP_FEATURE_HDR10 \| VOP_FEATURE_VIVID_HDR)) {
5652	9044	src_color_ctrl_offset = ovl_regs->hdr_mix_regs->src_color_ctrl.offset;
5653	9045	dst_color_ctrl_offset = ovl_regs->hdr_mix_regs->dst_color_ctrl.offset;
5654	9046	src_alpha_ctrl_offset = ovl_regs->hdr_mix_regs->src_alpha_ctrl.offset;
..	..	@@ -5679,21 +9071,6 @@
5679	9071	VOP_MODULE_SET(vop2, vp, bg_mix_ctrl, bg_alpha_ctrl.val);
5680	9072	}
5681	9073
5682		-static void vop2_setup_port_mux(struct vop2_video_port *vp, uint16_t port_mux_cfg)
5683		-{
5684		- struct vop2 *vop2 = vp->vop2;
5685		-
5686		- spin_lock(&vop2->reg_lock);
5687		- if (vop2->port_mux_cfg != port_mux_cfg) {
5688		- VOP_CTRL_SET(vop2, ovl_port_mux_cfg, port_mux_cfg);
5689		- vp->skip_vsync = true;
5690		- vop2_cfg_done(&vp->crtc);
5691		- vop2->port_mux_cfg = port_mux_cfg;
5692		- vop2_wait_for_port_mux_done(vop2);
5693		- }
5694		- spin_unlock(&vop2->reg_lock);
5695		-}
5696		-
5697	9074	static u32 vop2_layer_cfg_update(struct vop2_layer *layer, u32 old_layer_cfg, u8 win_layer_id)
5698	9075	{
5699	9076	const struct vop_reg *reg = &layer->regs->layer_sel;
..	..	@@ -5716,6 +9093,12 @@
5716	9093	for (i = 0; i < vop2_data->nr_vps - 1; i++) {
5717	9094	prev_vp = &vop2->vps[i];
5718	9095	used_layers += hweight32(prev_vp->win_mask);
	9096	+ if (vop2->version == VOP_VERSION_RK3588) {
	9097	+ if (vop2->vps[0].hdr10_at_splice_mode && i == 0)
	9098	+ used_layers += 1;
	9099	+ if (vop2->vps[0].hdr10_at_splice_mode && i == 1)
	9100	+ used_layers -= 1;
	9101	+ }
5719	9102	/*
5720	9103	* when a window move from vp0 to vp1, or vp0 to vp2,
5721	9104	* it should flow these steps:
..	..	@@ -5741,10 +9124,26 @@
5741	9124	prev_vp->bg_ovl_dly = (vop2_data->nr_mixers - port_mux) << 1;
5742	9125	}
5743	9126
5744		- if (vop2->data->nr_vps >= 1)
5745		- port_mux_cfg \|= 7 << (4 * (vop2->data->nr_vps - 1));
	9127	+ port_mux_cfg \|= 7 << (4 * (vop2->data->nr_vps - 1));
5746	9128
5747	9129	return port_mux_cfg;
	9130	+}
	9131	+
	9132	+static void vop2_setup_port_mux(struct vop2_video_port *vp)
	9133	+{
	9134	+ struct vop2 *vop2 = vp->vop2;
	9135	+ u16 port_mux_cfg;
	9136	+
	9137	+ port_mux_cfg = vop2_calc_bg_ovl_and_port_mux(vp);
	9138	+ spin_lock(&vop2->reg_lock);
	9139	+ if (vop2->port_mux_cfg != port_mux_cfg) {
	9140	+ VOP_CTRL_SET(vop2, ovl_port_mux_cfg, port_mux_cfg);
	9141	+ vp->skip_vsync = true;
	9142	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	9143	+ vop2->port_mux_cfg = port_mux_cfg;
	9144	+ vop2_wait_for_port_mux_done(vop2);
	9145	+ }
	9146	+ spin_unlock(&vop2->reg_lock);
5748	9147	}
5749	9148
5750	9149	static void vop2_setup_layer_mixer_for_vp(struct vop2_video_port *vp,
..	..	@@ -5758,15 +9157,12 @@
5758	9157	struct vop2_win *win;
5759	9158	u8 used_layers = 0;
5760	9159	u8 layer_id, win_phys_id;
5761		- u16 port_mux_cfg;
5762	9160	u32 layer_cfg_reg_offset = layer->regs->layer_sel.offset;
5763	9161	u8 nr_layers = vp->nr_layers;
5764	9162	u32 old_layer_cfg = 0;
5765	9163	u32 new_layer_cfg = 0;
5766	9164	u32 atv_layer_cfg;
5767	9165	int i;
5768		-
5769		- port_mux_cfg = vop2_calc_bg_ovl_and_port_mux(vp);
5770	9166
5771	9167	/*
5772	9168	* Win and layer must map one by one, if a win is selected
..	..	@@ -5782,6 +9178,10 @@
5782	9178
5783	9179	old_layer_cfg = vop2->regsbak[layer_cfg_reg_offset >> 2];
5784	9180	new_layer_cfg = old_layer_cfg;
	9181	+
	9182	+ if (vp->hdr10_at_splice_mode)
	9183	+ nr_layers *= 2;
	9184	+
5785	9185	for (i = 0; i < nr_layers; i++) {
5786	9186	layer = &vop2->layers[used_layers + i];
5787	9187	zpos = &vop2_zpos[i];
..	..	@@ -5795,21 +9195,21 @@
5795	9195	layer = &vop2->layers[layer_id];
5796	9196	win = vop2_find_win_by_phys_id(vop2, win_phys_id);
5797	9197	new_layer_cfg = vop2_layer_cfg_update(layer, new_layer_cfg, win->layer_sel_id[vp->id]);
5798		- win->layer_id = layer->id;
5799	9198	win->layer_id = layer_id;
5800	9199	layer->win_phys_id = win_phys_id;
5801	9200	}
5802	9201
5803	9202	atv_layer_cfg = vop2_read_layer_cfg(vop2);
5804		- if ((new_layer_cfg != old_layer_cfg) &&
5805		- (atv_layer_cfg != old_layer_cfg)) {
	9203	+ if (new_layer_cfg != old_layer_cfg &&
	9204	+ atv_layer_cfg != old_layer_cfg &&
	9205	+ !vp->splice_mode_right) {
5806	9206	dev_dbg(vop2->dev, "wait old_layer_sel: 0x%x\n", old_layer_cfg);
5807	9207	vop2_wait_for_layer_cfg_done(vop2, old_layer_cfg);
5808	9208	}
5809	9209	vop2_writel(vop2, RK3568_OVL_LAYER_SEL, new_layer_cfg);
5810		- VOP_CTRL_SET(vop2, ovl_cfg_done_port, vp->id);
	9210	+ if (new_layer_cfg != old_layer_cfg)
	9211	+ VOP_CTRL_SET(vop2, ovl_cfg_done_port, vp->id);
5811	9212	VOP_CTRL_SET(vop2, ovl_port_mux_cfg_done_imd, 0);
5812		- vop2_setup_port_mux(vp, port_mux_cfg);
5813	9213	}
5814	9214
5815	9215	static void vop3_setup_layer_sel_for_vp(struct vop2_video_port *vp,
..	..	@@ -5852,7 +9252,9 @@
5852	9252	struct vop2 *vop2 = vp->vop2;
5853	9253	const struct vop2_data *vop2_data = vop2->data;
5854	9254	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
5855		- struct drm_crtc *crtc = &vp->crtc;
	9255	+ struct vop2_video_port *left_vp = vp->left_vp;
	9256	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	9257	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
5856	9258	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
5857	9259	u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
5858	9260	u16 hdisplay = adjusted_mode->crtc_hdisplay;
..	..	@@ -5871,13 +9273,30 @@
5871	9273	}
5872	9274	}
5873	9275
5874		- if (!vp->hdr_in)
	9276	+ if (!vp->hdr_in \|\|
	9277	+ (vop2->version == VOP_VERSION_RK3588 && vp->hdr_out))
5875	9278	bg_dly -= vp->bg_ovl_dly;
5876	9279
5877		- pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
5878		- if (vop2->version >= VOP_VERSION_RK3588 && hsync_len < 8)
	9280	+ /*
	9281	+ * right vp share the same crtc state in splice mode
	9282	+ */
	9283	+ if (vp->splice_mode_right) {
	9284	+ vcstate = to_rockchip_crtc_state(left_vp->rockchip_crtc.crtc.state);
	9285	+ adjusted_mode = &left_vp->rockchip_crtc.crtc.state->adjusted_mode;
	9286	+ hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	9287	+ hdisplay = adjusted_mode->crtc_hdisplay;
	9288	+ }
	9289	+
	9290	+ if (vcstate->splice_mode)
	9291	+ pre_scan_dly = bg_dly + (hdisplay >> 2) - 1;
	9292	+ else
	9293	+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
	9294	+
	9295	+ if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8)
5879	9296	hsync_len = 8;
	9297	+
5880	9298	pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
	9299	+
5881	9300	VOP_MODULE_SET(vop2, vp, bg_dly, bg_dly);
5882	9301	VOP_MODULE_SET(vop2, vp, pre_scan_htiming, pre_scan_dly);
5883	9302	}
..	..	@@ -5895,8 +9314,17 @@
5895	9314	for (i = 0; i < vp->nr_layers; i++) {
5896	9315	zpos = &vop2_zpos[i];
5897	9316	win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
5898		- plane = &win->base;
5899		- vpstate = to_vop2_plane_state(plane->state);
	9317	+ /*
	9318	+ * right vp share the same plane state in splice mode
	9319	+ */
	9320	+ if (vp->splice_mode_right) {
	9321	+ plane = &win->left_win->base;
	9322	+ vpstate = to_vop2_plane_state(plane->state);
	9323	+ } else {
	9324	+ plane = &win->base;
	9325	+ vpstate = to_vop2_plane_state(plane->state);
	9326	+ }
	9327	+
5900	9328	if (vp->hdr_in && !vp->hdr_out && !vpstate->hdr_in) {
5901	9329	dly = win->dly[VOP2_DLY_MODE_HISO_S];
5902	9330	dly += vp->bg_ovl_dly;
..	..	@@ -5913,21 +9341,128 @@
5913	9341	}
5914	9342	}
5915	9343
	9344	+static void rk3588_vop2_setup_hdr10_splice_layer_mixer(struct drm_crtc *crtc,
	9345	+ struct vop2_zpos *vop2_zpos,
	9346	+ struct vop2_zpos *vop2_zpos_splice)
	9347	+{
	9348	+ int zpos_id, i;
	9349	+ struct vop2_zpos *vop2_zpos_splice_hdr;
	9350	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9351	+ struct vop2 *vop2 = vp->vop2;
	9352	+
	9353	+ vop2_zpos_splice_hdr = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos),
	9354	+ GFP_KERNEL);
	9355	+ if (!vop2_zpos_splice_hdr)
	9356	+ goto out;
	9357	+
	9358	+ zpos_id = 0;
	9359	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9360	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos[0].win_phys_id;
	9361	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos[0].plane;
	9362	+
	9363	+ zpos_id++;
	9364	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9365	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos_splice[0].win_phys_id;
	9366	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos_splice[0].plane;
	9367	+
	9368	+ for (i = 1; i < vp->nr_layers; i++) {
	9369	+ zpos_id++;
	9370	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9371	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos[i].win_phys_id;
	9372	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos[i].plane;
	9373	+ }
	9374	+
	9375	+ for (i = 1; i < vp->nr_layers; i++) {
	9376	+ zpos_id++;
	9377	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9378	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos_splice[i].win_phys_id;
	9379	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos_splice[i].plane;
	9380	+ }
	9381	+ vop2_setup_layer_mixer_for_vp(vp, vop2_zpos_splice_hdr);
	9382	+
	9383	+out:
	9384	+ kfree(vop2_zpos_splice_hdr);
	9385	+}
	9386	+
	9387	+static void vop2_crtc_update_vrr(struct drm_crtc *crtc)
	9388	+{
	9389	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9390	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9391	+ struct vop2 *vop2 = vp->vop2;
	9392	+ struct drm_display_mode *adjust_mode = &crtc->state->adjusted_mode;
	9393	+
	9394	+ unsigned int vrefresh;
	9395	+ unsigned int new_vtotal, vfp, new_vfp;
	9396	+
	9397	+ if (!vp->refresh_rate_change)
	9398	+ return;
	9399	+
	9400	+ if (!vcstate->min_refresh_rate \|\| !vcstate->max_refresh_rate)
	9401	+ return;
	9402	+
	9403	+ if (vcstate->request_refresh_rate < vcstate->min_refresh_rate \|\|
	9404	+ vcstate->request_refresh_rate > vcstate->max_refresh_rate) {
	9405	+ DRM_ERROR("invalid rate:%d\n", vcstate->request_refresh_rate);
	9406	+ return;
	9407	+ }
	9408	+
	9409	+ vrefresh = drm_mode_vrefresh(adjust_mode);
	9410	+
	9411	+ /* calculate new vfp for new refresh rate */
	9412	+ new_vtotal = adjust_mode->vtotal * vrefresh / vcstate->request_refresh_rate;
	9413	+ vfp = adjust_mode->vsync_start - adjust_mode->vdisplay;
	9414	+ new_vfp = vfp + new_vtotal - adjust_mode->vtotal;
	9415	+
	9416	+ /* config vop2 vtotal register */
	9417	+ VOP_MODULE_SET(vop2, vp, dsp_vtotal, new_vtotal);
	9418	+
	9419	+ /* config dsc vtotal register */
	9420	+ if (vcstate->dsc_enable) {
	9421	+ struct vop2_dsc *dsc;
	9422	+
	9423	+ dsc = &vop2->dscs[vcstate->dsc_id];
	9424	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, new_vtotal);
	9425	+
	9426	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	9427	+ dsc = &vop2->dscs[vcstate->dsc_id ? 0 : 1];
	9428	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, new_vtotal);
	9429	+ }
	9430	+ }
	9431	+
	9432	+ /* config all connectors attach to this crtc */
	9433	+ rockchip_connector_update_vfp_for_vrr(crtc, adjust_mode, new_vfp);
	9434	+}
	9435	+
5916	9436	static void vop2_crtc_atomic_begin(struct drm_crtc crtc, struct drm_crtc_state old_crtc_state)
5917	9437	{
5918	9438	struct vop2_video_port *vp = to_vop2_video_port(crtc);
5919	9439	struct vop2 *vop2 = vp->vop2;
	9440	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	9441	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
5920	9442	struct drm_plane *plane;
5921	9443	struct vop2_plane_state *vpstate;
5922	9444	struct vop2_zpos *vop2_zpos;
	9445	+ struct vop2_zpos *vop2_zpos_splice;
5923	9446	struct vop2_cluster cluster;
5924	9447	uint8_t nr_layers = 0;
	9448	+ uint8_t splice_nr_layers = 0;
	9449	+ bool hdr10_in = false;
	9450	+ bool hdr10_at_splice_mode = false;
5925	9451	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
5926	9452
5927	9453	vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);
5928	9454	vop2_zpos = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos), GFP_KERNEL);
5929	9455	if (!vop2_zpos)
5930	9456	return;
	9457	+ if (vcstate->splice_mode) {
	9458	+ vop2_zpos_splice = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos),
	9459	+ GFP_KERNEL);
	9460	+ if (!vop2_zpos_splice)
	9461	+ goto out;
	9462	+ }
	9463	+
	9464	+ if (vop2->version == VOP_VERSION_RK3588)
	9465	+ vop2_crtc_update_vrr(crtc);
5931	9466
5932	9467	/* Process cluster sub windows overlay. */
5933	9468	drm_atomic_crtc_for_each_plane(plane, crtc) {
..	..	@@ -5937,9 +9472,13 @@
5937	9472	win->two_win_mode = false;
5938	9473	if (!(win->feature & WIN_FEATURE_CLUSTER_SUB))
5939	9474	continue;
	9475	+ if (vcstate->splice_mode)
	9476	+ DRM_ERROR("vp%d %s not supported two win mode at splice mode\n",
	9477	+ vp->id, win->name);
5940	9478	main_win = vop2_find_win_by_phys_id(vop2, win->phys_id);
5941	9479	cluster.main = main_win;
5942	9480	cluster.sub = win;
	9481	+ cluster.splice_mode = false;
5943	9482	win->two_win_mode = true;
5944	9483	main_win->two_win_mode = true;
5945	9484	vop2_setup_cluster_alpha(vop2, &cluster);
..	..	@@ -5951,6 +9490,7 @@
5951	9490
5952	9491	drm_atomic_crtc_for_each_plane(plane, crtc) {
5953	9492	struct vop2_win *win = to_vop2_win(plane);
	9493	+ struct vop2_win *splice_win;
5954	9494	struct vop2_video_port *old_vp;
5955	9495	uint8_t old_vp_id;
5956	9496
..	..	@@ -5970,38 +9510,102 @@
5970	9510	vop2_zpos[nr_layers].win_phys_id = win->phys_id;
5971	9511	vop2_zpos[nr_layers].zpos = vpstate->zpos;
5972	9512	vop2_zpos[nr_layers].plane = plane;
	9513	+
	9514	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "%s active zpos:%d for vp%d from vp%d\n",
	9515	+ win->name, vpstate->zpos, vp->id, old_vp->id);
	9516	+ /* left and right win may have different number */
	9517	+ if (vcstate->splice_mode) {
	9518	+ splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
	9519	+ splice_win->splice_mode_right = true;
	9520	+ splice_win->left_win = win;
	9521	+ win->splice_win = splice_win;
	9522	+
	9523	+ old_vp_id = ffs(splice_win->vp_mask);
	9524	+ old_vp_id = (old_vp_id == 0) ? 0 : old_vp_id - 1;
	9525	+ old_vp = &vop2->vps[old_vp_id];
	9526	+ old_vp->win_mask &= ~BIT(splice_win->phys_id);
	9527	+ splice_vp->win_mask \|= BIT(splice_win->phys_id);
	9528	+ splice_win->vp_mask = BIT(splice_vp->id);
	9529	+ hdr10_in \|= vpstate->eotf == HDMI_EOTF_SMPTE_ST2084 ? true : false;
	9530	+ vop2_zpos_splice[splice_nr_layers].win_phys_id = splice_win->phys_id;
	9531	+ vop2_zpos_splice[splice_nr_layers].zpos = vpstate->zpos;
	9532	+ vop2_zpos_splice[splice_nr_layers].plane = &splice_win->base;
	9533	+ splice_nr_layers++;
	9534	+ DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
	9535	+ splice_win->name, vpstate->zpos, splice_vp->id, old_vp->id);
	9536	+ }
5973	9537	nr_layers++;
5974		- DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
5975		- win->name, vpstate->zpos, vp->id, old_vp->id);
5976	9538	}
5977	9539
5978		- DRM_DEV_DEBUG(vop2->dev, "vp%d: %d windows, active layers %d\n",
5979		- vp->id, hweight32(vp->win_mask), nr_layers);
	9540	+ if (vcstate->splice_mode) {
	9541	+ if (hdr10_in)
	9542	+ hdr10_at_splice_mode = true;
	9543	+
	9544	+ splice_vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
	9545	+ }
	9546	+ vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
	9547	+
	9548	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "vp%d: %d windows, active layers %d\n",
	9549	+ vp->id, hweight32(vp->win_mask), nr_layers);
5980	9550	if (nr_layers) {
5981	9551	vp->nr_layers = nr_layers;
5982	9552
5983	9553	sort(vop2_zpos, nr_layers, sizeof(vop2_zpos[0]), vop2_zpos_cmp, NULL);
5984	9554
5985		- if (is_vop3(vop2))
5986		- vop3_setup_layer_sel_for_vp(vp, vop2_zpos);
5987		- else
5988		- vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
5989		- vop2_setup_hdr10(vp, vop2_zpos[0].win_phys_id);
5990		- if (is_vop3(vop2))
	9555	+ if (!vp->hdr10_at_splice_mode) {
	9556	+ if (is_vop3(vop2)) {
	9557	+ vop3_setup_layer_sel_for_vp(vp, vop2_zpos);
	9558	+ } else {
	9559	+ vop2_setup_port_mux(vp);
	9560	+ vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
	9561	+ }
	9562	+ }
	9563	+
	9564	+ if (is_vop3(vop2)) {
	9565	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	9566	+ vop3_setup_dynamic_hdr(vp, vop2_zpos[0].win_phys_id);
5991	9567	vop3_setup_alpha(vp, vop2_zpos);
5992		- else
	9568	+ vop3_setup_pipe_dly(vp, vop2_zpos);
	9569	+ } else {
	9570	+ vop2_setup_hdr10(vp, vop2_zpos[0].win_phys_id);
5993	9571	vop2_setup_alpha(vp, vop2_zpos);
5994		- vop2_setup_dly_for_vp(vp);
5995		- vop2_setup_dly_for_window(vp, vop2_zpos);
	9572	+ vop2_setup_dly_for_vp(vp);
	9573	+ vop2_setup_dly_for_window(vp, vop2_zpos);
	9574	+ }
	9575	+
	9576	+ if (vcstate->splice_mode) {/* Fixme for VOP3 8K */
	9577	+ splice_vp->nr_layers = splice_nr_layers;
	9578	+
	9579	+ sort(vop2_zpos_splice, splice_nr_layers, sizeof(vop2_zpos_splice[0]),
	9580	+ vop2_zpos_cmp, NULL);
	9581	+
	9582	+ vop2_setup_port_mux(splice_vp);
	9583	+ if (!vp->hdr10_at_splice_mode)
	9584	+ vop2_setup_layer_mixer_for_vp(splice_vp, vop2_zpos_splice);
	9585	+ vop2_setup_hdr10(splice_vp, vop2_zpos_splice[0].win_phys_id);
	9586	+ vop2_setup_alpha(splice_vp, vop2_zpos_splice);
	9587	+ vop2_setup_dly_for_vp(splice_vp);
	9588	+ vop2_setup_dly_for_window(splice_vp, vop2_zpos_splice);
	9589	+
	9590	+ if (vop2->version == VOP_VERSION_RK3588 &&
	9591	+ vp->hdr10_at_splice_mode)
	9592	+ rk3588_vop2_setup_hdr10_splice_layer_mixer(crtc, vop2_zpos, vop2_zpos_splice);
	9593	+ }
5996	9594	} else {
5997		- if (!is_vop3(vop2))
	9595	+ if (!is_vop3(vop2)) {
5998	9596	vop2_calc_bg_ovl_and_port_mux(vp);
5999		- vop2_setup_dly_for_vp(vp);
	9597	+ vop2_setup_dly_for_vp(vp);
	9598	+ if (vcstate->splice_mode)
	9599	+ vop2_setup_dly_for_vp(splice_vp);
	9600	+ } else {
	9601	+ vop3_setup_pipe_dly(vp, NULL);
	9602	+ }
6000	9603	}
6001	9604
6002	9605	/* The pre alpha overlay of Cluster still need process in one win mode. */
6003	9606	drm_atomic_crtc_for_each_plane(plane, crtc) {
6004	9607	struct vop2_win *win = to_vop2_win(plane);
	9608	+ struct vop2_win *splice_win;
6005	9609
6006	9610	if (!(win->feature & WIN_FEATURE_CLUSTER_MAIN))
6007	9611	continue;
..	..	@@ -6009,9 +9613,19 @@
6009	9613	continue;
6010	9614	cluster.main = win;
6011	9615	cluster.sub = NULL;
	9616	+ cluster.splice_mode = false;
6012	9617	vop2_setup_cluster_alpha(vop2, &cluster);
	9618	+ if (vcstate->splice_mode) {
	9619	+ splice_win = win->splice_win;
	9620	+ cluster.main = splice_win;
	9621	+ cluster.splice_mode = true;
	9622	+ vop2_setup_cluster_alpha(vop2, &cluster);
	9623	+ }
6013	9624	}
6014	9625
	9626	+ if (vcstate->splice_mode)
	9627	+ kfree(vop2_zpos_splice);
	9628	+out:
6015	9629	kfree(vop2_zpos);
6016	9630	}
6017	9631
..	..	@@ -6122,6 +9736,171 @@
6122	9736	bcsh_state.cos_hue = cos_hue;
6123	9737
6124	9738	vop2_bcsh_reg_update(vcstate, vp, &bcsh_state);
	9739	+ if (vcstate->splice_mode) {
	9740	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	9741	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	9742	+
	9743	+ vop2_bcsh_reg_update(vcstate, splice_vp, &bcsh_state);
	9744	+ }
	9745	+}
	9746	+
	9747	+static void vop3_post_csc_config(struct drm_crtc crtc, struct post_acm acm, struct post_csc *csc)
	9748	+{
	9749	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9750	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9751	+ struct vop2 *vop2 = vp->vop2;
	9752	+ struct post_csc_coef csc_coef;
	9753	+ bool acm_enable;
	9754	+ bool is_input_yuv = false;
	9755	+ bool is_output_yuv = false;
	9756	+ bool post_r2y_en = false;
	9757	+ bool post_csc_en = false;
	9758	+ int range_type;
	9759	+
	9760	+ if (!acm)
	9761	+ acm_enable = false;
	9762	+ else
	9763	+ acm_enable = acm->acm_enable;
	9764	+
	9765	+ if (acm_enable) {
	9766	+ if (!vcstate->yuv_overlay)
	9767	+ post_r2y_en = true;
	9768	+
	9769	+ /* do y2r in csc module */
	9770	+ if (!is_yuv_output(vcstate->bus_format))
	9771	+ post_csc_en = true;
	9772	+ } else {
	9773	+ if (!vcstate->yuv_overlay && is_yuv_output(vcstate->bus_format))
	9774	+ post_r2y_en = true;
	9775	+
	9776	+ /* do y2r in csc module */
	9777	+ if (vcstate->yuv_overlay && !is_yuv_output(vcstate->bus_format))
	9778	+ post_csc_en = true;
	9779	+ }
	9780	+
	9781	+ if (csc && csc->csc_enable)
	9782	+ post_csc_en = true;
	9783	+
	9784	+ if (vcstate->yuv_overlay \|\| post_r2y_en)
	9785	+ is_input_yuv = true;
	9786	+
	9787	+ if (is_yuv_output(vcstate->bus_format))
	9788	+ is_output_yuv = true;
	9789	+
	9790	+ vcstate->post_csc_mode = vop2_convert_csc_mode(vcstate->color_space, CSC_13BIT_DEPTH);
	9791	+
	9792	+ if (post_csc_en) {
	9793	+ rockchip_calc_post_csc(csc, &csc_coef, vcstate->post_csc_mode, is_input_yuv,
	9794	+ is_output_yuv);
	9795	+
	9796	+ VOP_MODULE_SET(vop2, vp, csc_coe00, csc_coef.csc_coef00);
	9797	+ VOP_MODULE_SET(vop2, vp, csc_coe01, csc_coef.csc_coef01);
	9798	+ VOP_MODULE_SET(vop2, vp, csc_coe02, csc_coef.csc_coef02);
	9799	+ VOP_MODULE_SET(vop2, vp, csc_coe10, csc_coef.csc_coef10);
	9800	+ VOP_MODULE_SET(vop2, vp, csc_coe11, csc_coef.csc_coef11);
	9801	+ VOP_MODULE_SET(vop2, vp, csc_coe12, csc_coef.csc_coef12);
	9802	+ VOP_MODULE_SET(vop2, vp, csc_coe20, csc_coef.csc_coef20);
	9803	+ VOP_MODULE_SET(vop2, vp, csc_coe21, csc_coef.csc_coef21);
	9804	+ VOP_MODULE_SET(vop2, vp, csc_coe22, csc_coef.csc_coef22);
	9805	+ VOP_MODULE_SET(vop2, vp, csc_offset0, csc_coef.csc_dc0);
	9806	+ VOP_MODULE_SET(vop2, vp, csc_offset1, csc_coef.csc_dc1);
	9807	+ VOP_MODULE_SET(vop2, vp, csc_offset2, csc_coef.csc_dc2);
	9808	+
	9809	+ range_type = csc_coef.range_type ? 0 : 1;
	9810	+ range_type <<= is_input_yuv ? 0 : 1;
	9811	+ VOP_MODULE_SET(vop2, vp, csc_mode, range_type);
	9812	+ }
	9813	+
	9814	+ VOP_MODULE_SET(vop2, vp, acm_r2y_en, post_r2y_en ? 1 : 0);
	9815	+ VOP_MODULE_SET(vop2, vp, csc_en, post_csc_en ? 1 : 0);
	9816	+ VOP_MODULE_SET(vop2, vp, acm_r2y_mode, vcstate->post_csc_mode);
	9817	+}
	9818	+
	9819	+static void vop3_post_acm_config(struct drm_crtc crtc, struct post_acm acm)
	9820	+{
	9821	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9822	+ struct vop2 *vop2 = vp->vop2;
	9823	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	9824	+ s16 *lut_y;
	9825	+ s16 *lut_h;
	9826	+ s16 *lut_s;
	9827	+ u32 value;
	9828	+ int i;
	9829	+
	9830	+ writel(0, vop2->acm_regs + RK3528_ACM_CTRL);
	9831	+ VOP_MODULE_SET(vop2, vp, acm_bypass_en, 0);
	9832	+
	9833	+ if (!acm \|\| !acm->acm_enable)
	9834	+ return;
	9835	+
	9836	+ /*
	9837	+ * If acm update parameters, it need disable acm in the first frame,
	9838	+ * then update parameters and enable acm in second frame.
	9839	+ */
	9840	+ vop2_cfg_done(crtc);
	9841	+ readx_poll_timeout(readl, vop2->acm_regs + RK3528_ACM_CTRL, value, !value, 200, 50000);
	9842	+
	9843	+ value = RK3528_ACM_ENABLE + ((adjusted_mode->hdisplay & 0xfff) << 8) +
	9844	+ ((adjusted_mode->vdisplay & 0xfff) << 20);
	9845	+ writel(value, vop2->acm_regs + RK3528_ACM_CTRL);
	9846	+
	9847	+
	9848	+ writel(1, vop2->acm_regs + RK3528_ACM_FETCH_START);
	9849	+
	9850	+ value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) +
	9851	+ ((acm->s_gain << 20) & 0x3ff00000);
	9852	+ writel(value, vop2->acm_regs + RK3528_ACM_DELTA_RANGE);
	9853	+
	9854	+ lut_y = &acm->gain_lut_hy[0];
	9855	+ lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
	9856	+ lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
	9857	+ for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
	9858	+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
	9859	+ ((lut_s[i] << 16) & 0xff0000);
	9860	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
	9861	+ }
	9862	+
	9863	+ lut_y = &acm->gain_lut_hs[0];
	9864	+ lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
	9865	+ lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
	9866	+ for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
	9867	+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
	9868	+ ((lut_s[i] << 16) & 0xff0000);
	9869	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
	9870	+ }
	9871	+
	9872	+ lut_y = &acm->delta_lut_h[0];
	9873	+ lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
	9874	+ lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
	9875	+ for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
	9876	+ value = (lut_y[i] & 0x3ff) + ((lut_h[i] << 12) & 0xff000) +
	9877	+ ((lut_s[i] << 20) & 0x3ff00000);
	9878	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
	9879	+ }
	9880	+
	9881	+ writel(1, vop2->acm_regs + RK3528_ACM_FETCH_DONE);
	9882	+}
	9883	+
	9884	+static void vop3_post_config(struct drm_crtc *crtc)
	9885	+{
	9886	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9887	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9888	+ struct post_acm *acm;
	9889	+ struct post_csc *csc;
	9890	+
	9891	+ csc = vcstate->post_csc_data ? (struct post_csc *)vcstate->post_csc_data->data : NULL;
	9892	+ if (csc && memcmp(&vp->csc_info, csc, sizeof(struct post_csc)))
	9893	+ memcpy(&vp->csc_info, csc, sizeof(struct post_csc));
	9894	+ vop3_post_csc_config(crtc, &vp->acm_info, &vp->csc_info);
	9895	+
	9896	+ acm = vcstate->acm_lut_data ? (struct post_acm *)vcstate->acm_lut_data->data : NULL;
	9897	+
	9898	+ if (acm && memcmp(&vp->acm_info, acm, sizeof(struct post_acm))) {
	9899	+ memcpy(&vp->acm_info, acm, sizeof(struct post_acm));
	9900	+ vop3_post_acm_config(crtc, &vp->acm_info);
	9901	+ } else if (crtc->state->active_changed) {
	9902	+ vop3_post_acm_config(crtc, &vp->acm_info);
	9903	+ }
6125	9904	}
6126	9905
6127	9906	static void vop2_cfg_update(struct drm_crtc *crtc,
..	..	@@ -6130,10 +9909,28 @@
6130	9909	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6131	9910	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6132	9911	struct vop2 *vop2 = vp->vop2;
	9912	+ const struct vop2_data *vop2_data = vop2->data;
	9913	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	9914	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
6133	9915	uint32_t val;
6134	9916	uint32_t r, g, b;
	9917	+ uint8_t out_mode;
6135	9918
6136	9919	spin_lock(&vop2->reg_lock);
	9920	+
	9921	+ if ((vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
	9922	+ !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) \|\|
	9923	+ vcstate->output_if & VOP_OUTPUT_IF_BT656)
	9924	+ out_mode = ROCKCHIP_OUT_MODE_P888;
	9925	+ else
	9926	+ out_mode = vcstate->output_mode;
	9927	+ VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
	9928	+
	9929	+ vop2_post_color_swap(crtc);
	9930	+
	9931	+ vop2_dither_setup(vcstate, crtc);
	9932	+ if (vcstate->splice_mode)
	9933	+ vop2_dither_setup(vcstate, &splice_vp->rockchip_crtc.crtc);
6137	9934
6138	9935	VOP_MODULE_SET(vop2, vp, overlay_mode, vcstate->yuv_overlay);
6139	9936
..	..	@@ -6156,12 +9953,86 @@
6156	9953	}
6157	9954
6158	9955	VOP_MODULE_SET(vop2, vp, dsp_background, val);
	9956	+ if (vcstate->splice_mode) {
	9957	+ VOP_MODULE_SET(vop2, splice_vp, overlay_mode, vcstate->yuv_overlay);
	9958	+ VOP_MODULE_SET(vop2, splice_vp, dsp_background, val);
	9959	+ }
6159	9960
6160	9961	vop2_tv_config_update(crtc, old_crtc_state);
6161	9962
6162		- vop2_post_config(crtc);
	9963	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN)
	9964	+ vop2_post_config(crtc);
6163	9965
6164	9966	spin_unlock(&vop2->reg_lock);
	9967	+
	9968	+ if (vp_data->feature & (VOP_FEATURE_POST_ACM \| VOP_FEATURE_POST_CSC))
	9969	+ vop3_post_config(crtc);
	9970	+}
	9971	+
	9972	+static void vop2_sleep_scan_line_time(struct vop2_video_port *vp, int scan_line)
	9973	+{
	9974	+ struct vop2 *vop2 = vp->vop2;
	9975	+ struct drm_display_mode *mode = &vp->rockchip_crtc.crtc.state->adjusted_mode;
	9976	+
	9977	+ if (scan_line <= 0)
	9978	+ return;
	9979	+
	9980	+ if (IS_ENABLED(CONFIG_HIGH_RES_TIMERS) &&
	9981	+ (!IS_ENABLED(CONFIG_NO_GKI) \|\| (hrtimer_resolution != LOW_RES_NSEC))) {
	9982	+ u16 htotal = VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16;
	9983	+ u32 linedur_ns = div_u64((u64) htotal * 1000000, mode->crtc_clock);
	9984	+ u64 sleep_time = linedur_ns * scan_line;
	9985	+
	9986	+ sleep_time = div_u64((sleep_time + 1000), 1000);
	9987	+ if (sleep_time > 200)
	9988	+ usleep_range(sleep_time, sleep_time);
	9989	+ }
	9990	+}
	9991	+
	9992	+/*
	9993	+ * return scan timing from FS to the assigned wait line
	9994	+ */
	9995	+static void vop2_wait_for_scan_timing_max_to_assigned_line(struct vop2_video_port *vp,
	9996	+ u32 current_line,
	9997	+ u32 wait_line)
	9998	+
	9999	+{
	10000	+ struct vop2 *vop2 = vp->vop2;
	10001	+ u32 vcnt;
	10002	+ int ret;
	10003	+ u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal);
	10004	+ int delta_line = vtotal - current_line;
	10005	+
	10006	+ vop2_sleep_scan_line_time(vp, delta_line);
	10007	+ if (vop2_read_vcnt(vp) < wait_line)
	10008	+ return;
	10009	+
	10010	+ ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt < wait_line, 0, 50 * 1000);
	10011	+ if (ret)
	10012	+ DRM_DEV_ERROR(vop2->dev, "wait scan timing from FS to the assigned wait line: %d, vcnt:%d, ret:%d\n",
	10013	+ wait_line, vcnt, ret);
	10014	+}
	10015	+
	10016	+/*
	10017	+ * return scan timing from the assigned wait line
	10018	+ */
	10019	+static void vop2_wait_for_scan_timing_from_the_assigned_line(struct vop2_video_port *vp,
	10020	+ u32 current_line,
	10021	+ u32 wait_line)
	10022	+{
	10023	+ struct vop2 *vop2 = vp->vop2;
	10024	+ u32 vcnt;
	10025	+ int ret;
	10026	+ int delta_line = wait_line - current_line;
	10027	+
	10028	+ vop2_sleep_scan_line_time(vp, delta_line);
	10029	+ if (vop2_read_vcnt(vp) > wait_line)
	10030	+ return;
	10031	+
	10032	+ ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt > wait_line, 0, 50 * 1000);
	10033	+ if (ret)
	10034	+ DRM_DEV_ERROR(vop2->dev, "wait scan timing from the assigned wait line: %d, vcnt:%d, ret:%d\n",
	10035	+ wait_line, vcnt, ret);
6165	10036	}
6166	10037
6167	10038	static void vop2_crtc_atomic_flush(struct drm_crtc crtc, struct drm_crtc_state old_cstate)
..	..	@@ -6169,11 +10040,26 @@
6169	10040	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6170	10041	struct drm_atomic_state *old_state = old_cstate->state;
6171	10042	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6172		- struct drm_plane_state *old_pstate;
6173	10043	struct vop2 *vop2 = vp->vop2;
	10044	+ struct drm_plane_state *old_pstate;
6174	10045	struct drm_plane *plane;
6175	10046	unsigned long flags;
6176	10047	int i, ret;
	10048	+ struct vop2_wb *wb = &vop2->wb;
	10049	+ struct drm_writeback_connector *wb_conn = &wb->conn;
	10050	+ struct drm_connector_state *conn_state = wb_conn->base.state;
	10051	+
	10052	+ if (conn_state && conn_state->writeback_job && conn_state->writeback_job->fb) {
	10053	+ u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal);
	10054	+ u32 current_line = vop2_read_vcnt(vp);
	10055	+
	10056	+ if (current_line > vtotal * 7 >> 3)
	10057	+ vop2_wait_for_scan_timing_max_to_assigned_line(vp, current_line, vtotal * 7 >> 3);
	10058	+
	10059	+ current_line = vop2_read_vcnt(vp);
	10060	+ if (current_line < vtotal >> 3)
	10061	+ vop2_wait_for_scan_timing_from_the_assigned_line(vp, current_line, vtotal >> 3);
	10062	+ }
6177	10063
6178	10064	vop2_cfg_update(crtc, old_cstate);
6179	10065
..	..	@@ -6199,10 +10085,9 @@
6199	10085	vp->gamma_lut = crtc->state->gamma_lut->data;
6200	10086	vop2_crtc_atomic_gamma_set(crtc, crtc->state);
6201	10087	}
6202		-
6203		- if (crtc->state->cubic_lut \|\| vp->cubic_lut) {
6204		- if (crtc->state->cubic_lut)
6205		- vp->cubic_lut = crtc->state->cubic_lut->data;
	10088	+ if (vcstate->cubic_lut_data \|\| vp->cubic_lut) {
	10089	+ if (vcstate->cubic_lut_data)
	10090	+ vp->cubic_lut = vcstate->cubic_lut_data->data;
6206	10091	vop2_crtc_atomic_cubic_lut_set(crtc, crtc->state);
6207	10092	}
6208	10093	} else {
..	..	@@ -6217,6 +10102,9 @@
6217	10102	spin_lock_irqsave(&vop2->irq_lock, flags);
6218	10103	vop2_wb_commit(crtc);
6219	10104	vop2_cfg_done(crtc);
	10105	+
	10106	+ if (vp->mcu_timing.mcu_pix_total)
	10107	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 0);
6220	10108
6221	10109	spin_unlock_irqrestore(&vop2->irq_lock, flags);
6222	10110
..	..	@@ -6258,6 +10146,7 @@
6258	10146	}
6259	10147
6260	10148	static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
	10149	+ .mode_valid = vop2_crtc_mode_valid,
6261	10150	.mode_fixup = vop2_crtc_mode_fixup,
6262	10151	.atomic_check = vop2_crtc_atomic_check,
6263	10152	.atomic_begin = vop2_crtc_atomic_begin,
..	..	@@ -6298,12 +10187,24 @@
6298	10187	struct rockchip_crtc_state vcstate, old_vcstate;
6299	10188	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6300	10189
	10190	+ if (WARN_ON(!crtc->state))
	10191	+ return NULL;
	10192	+
6301	10193	old_vcstate = to_rockchip_crtc_state(crtc->state);
6302	10194	vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL);
6303	10195	if (!vcstate)
6304	10196	return NULL;
6305	10197
6306	10198	vcstate->vp_id = vp->id;
	10199	+ if (vcstate->hdr_ext_data)
	10200	+ drm_property_blob_get(vcstate->hdr_ext_data);
	10201	+ if (vcstate->acm_lut_data)
	10202	+ drm_property_blob_get(vcstate->acm_lut_data);
	10203	+ if (vcstate->post_csc_data)
	10204	+ drm_property_blob_get(vcstate->post_csc_data);
	10205	+ if (vcstate->cubic_lut_data)
	10206	+ drm_property_blob_get(vcstate->cubic_lut_data);
	10207	+
6307	10208	__drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
6308	10209	return &vcstate->base;
6309	10210	}
..	..	@@ -6314,6 +10215,10 @@
6314	10215	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
6315	10216
6316	10217	__drm_atomic_helper_crtc_destroy_state(&vcstate->base);
	10218	+ drm_property_blob_put(vcstate->hdr_ext_data);
	10219	+ drm_property_blob_put(vcstate->acm_lut_data);
	10220	+ drm_property_blob_put(vcstate->post_csc_data);
	10221	+ drm_property_blob_put(vcstate->cubic_lut_data);
6317	10222	kfree(vcstate);
6318	10223	}
6319	10224
..	..	@@ -6414,25 +10319,54 @@
6414	10319	return 0;
6415	10320	}
6416	10321
6417		- if (property == private->alpha_scale_prop) {
6418		- *val = (vop2->data->feature & VOP_FEATURE_ALPHA_SCALE) ? 1 : 0;
6419		- return 0;
6420		- }
6421		-
6422		- if (property == vop2->aclk_prop) {
	10322	+ if (property == private->aclk_prop) {
6423	10323	/* KHZ, keep align with mode->clock */
6424	10324	*val = clk_get_rate(vop2->aclk) / 1000;
6425	10325	return 0;
6426	10326	}
6427	10327
6428		-
6429		- if (property == vop2->bg_prop) {
	10328	+ if (property == private->bg_prop) {
6430	10329	*val = vcstate->background;
6431	10330	return 0;
6432	10331	}
6433	10332
6434		- if (property == vop2->line_flag_prop) {
	10333	+ if (property == private->line_flag_prop) {
6435	10334	*val = vcstate->line_flag;
	10335	+ return 0;
	10336	+ }
	10337	+
	10338	+ if (property == vp->variable_refresh_rate_prop) {
	10339	+ *val = vcstate->request_refresh_rate;
	10340	+ return 0;
	10341	+ }
	10342	+
	10343	+ if (property == vp->max_refresh_rate_prop) {
	10344	+ *val = vcstate->max_refresh_rate;
	10345	+ return 0;
	10346	+ }
	10347	+
	10348	+ if (property == vp->min_refresh_rate_prop) {
	10349	+ *val = vcstate->min_refresh_rate;
	10350	+ return 0;
	10351	+ }
	10352	+
	10353	+ if (property == vp->hdr_ext_data_prop) {
	10354	+ *val = vcstate->hdr_ext_data ? vcstate->hdr_ext_data->base.id : 0;
	10355	+ return 0;
	10356	+ }
	10357	+
	10358	+ if (property == vp->acm_lut_data_prop) {
	10359	+ *val = vcstate->acm_lut_data ? vcstate->acm_lut_data->base.id : 0;
	10360	+ return 0;
	10361	+ }
	10362	+
	10363	+ if (property == vp->post_csc_data_prop) {
	10364	+ *val = vcstate->post_csc_data ? vcstate->post_csc_data->base.id : 0;
	10365	+ return 0;
	10366	+ }
	10367	+
	10368	+ if (property == private->cubic_lut_prop) {
	10369	+ *val = (vcstate->cubic_lut_data) ? vcstate->cubic_lut_data->base.id : 0;
6436	10370	return 0;
6437	10371	}
6438	10372
..	..	@@ -6441,16 +10375,52 @@
6441	10375	return -EINVAL;
6442	10376	}
6443	10377
	10378	+/* copied from drm_atomic.c */
	10379	+static int
	10380	+vop2_atomic_replace_property_blob_from_id(struct drm_device *dev,
	10381	+ struct drm_property_blob **blob,
	10382	+ uint64_t blob_id,
	10383	+ ssize_t expected_size,
	10384	+ ssize_t expected_elem_size,
	10385	+ bool *replaced)
	10386	+{
	10387	+ struct drm_property_blob *new_blob = NULL;
	10388	+
	10389	+ if (blob_id != 0) {
	10390	+ new_blob = drm_property_lookup_blob(dev, blob_id);
	10391	+ if (new_blob == NULL)
	10392	+ return -EINVAL;
	10393	+
	10394	+ if (expected_size > 0 &&
	10395	+ new_blob->length != expected_size) {
	10396	+ drm_property_blob_put(new_blob);
	10397	+ return -EINVAL;
	10398	+ }
	10399	+ if (expected_elem_size > 0 &&
	10400	+ new_blob->length % expected_elem_size != 0) {
	10401	+ drm_property_blob_put(new_blob);
	10402	+ return -EINVAL;
	10403	+ }
	10404	+ }
	10405	+
	10406	+ *replaced \|= drm_property_replace_blob(blob, new_blob);
	10407	+ drm_property_blob_put(new_blob);
	10408	+
	10409	+ return 0;
	10410	+}
	10411	+
6444	10412	static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc,
6445	10413	struct drm_crtc_state *state,
6446	10414	struct drm_property *property,
6447	10415	uint64_t val)
6448	10416	{
6449	10417	struct drm_device *drm_dev = crtc->dev;
	10418	+ struct rockchip_drm_private *private = drm_dev->dev_private;
6450	10419	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
6451	10420	struct drm_mode_config *mode_config = &drm_dev->mode_config;
6452	10421	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6453		- struct vop2 *vop2 = vp->vop2;
	10422	+ bool replaced = false;
	10423	+ int ret;
6454	10424
6455	10425	if (property == mode_config->tv_left_margin_property) {
6456	10426	vcstate->left_margin = val;
..	..	@@ -6473,14 +10443,66 @@
6473	10443	}
6474	10444
6475	10445
6476		- if (property == vop2->bg_prop) {
	10446	+ if (property == private->bg_prop) {
6477	10447	vcstate->background = val;
6478	10448	return 0;
6479	10449	}
6480	10450
6481		- if (property == vop2->line_flag_prop) {
	10451	+ if (property == private->line_flag_prop) {
6482	10452	vcstate->line_flag = val;
6483	10453	return 0;
	10454	+ }
	10455	+
	10456	+ if (property == vp->variable_refresh_rate_prop) {
	10457	+ vcstate->request_refresh_rate = val;
	10458	+ return 0;
	10459	+ }
	10460	+
	10461	+ if (property == vp->max_refresh_rate_prop) {
	10462	+ vcstate->max_refresh_rate = val;
	10463	+ return 0;
	10464	+ }
	10465	+
	10466	+ if (property == vp->min_refresh_rate_prop) {
	10467	+ vcstate->min_refresh_rate = val;
	10468	+ return 0;
	10469	+ }
	10470	+
	10471	+ if (property == vp->hdr_ext_data_prop) {
	10472	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10473	+ &vcstate->hdr_ext_data,
	10474	+ val,
	10475	+ -1, -1,
	10476	+ &replaced);
	10477	+ return ret;
	10478	+ }
	10479	+
	10480	+ if (property == vp->acm_lut_data_prop) {
	10481	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10482	+ &vcstate->acm_lut_data,
	10483	+ val,
	10484	+ sizeof(struct post_acm), -1,
	10485	+ &replaced);
	10486	+ return ret;
	10487	+ }
	10488	+
	10489	+ if (property == vp->post_csc_data_prop) {
	10490	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10491	+ &vcstate->post_csc_data,
	10492	+ val,
	10493	+ sizeof(struct post_csc), -1,
	10494	+ &replaced);
	10495	+ return ret;
	10496	+ }
	10497	+
	10498	+ if (property == private->cubic_lut_prop) {
	10499	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10500	+ &vcstate->cubic_lut_data,
	10501	+ val,
	10502	+ -1, sizeof(struct drm_color_lut),
	10503	+ &replaced);
	10504	+ state->color_mgmt_changed \|= replaced;
	10505	+ return ret;
6484	10506	}
6485	10507
6486	10508	DRM_ERROR("failed to set vop2 crtc property %s\n", property->name);
..	..	@@ -6509,7 +10531,7 @@
6509	10531	struct vop2_video_port *vp = container_of(work, struct vop2_video_port, fb_unref_work);
6510	10532	struct drm_framebuffer *fb = val;
6511	10533
6512		- drm_crtc_vblank_put(&vp->crtc);
	10534	+ drm_crtc_vblank_put(&vp->rockchip_crtc.crtc);
6513	10535	if (!vp->vop2->skip_ref_fb)
6514	10536	drm_framebuffer_put(fb);
6515	10537	}
..	..	@@ -6580,6 +10602,7 @@
6580	10602	struct vop2_wb *wb = &vop2->wb;
6581	10603
6582	10604	VOP_MODULE_SET(vop2, wb, enable, 0);
	10605	+ VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 0);
6583	10606	vop2_wb_cfg_done(vp);
6584	10607	}
6585	10608
..	..	@@ -6618,6 +10641,43 @@
6618	10641	}
6619	10642	}
6620	10643	spin_unlock_irqrestore(&wb->job_lock, flags);
	10644	+}
	10645	+
	10646	+static void vop2_dsc_isr(struct vop2 *vop2)
	10647	+{
	10648	+ const struct vop2_data *vop2_data = vop2->data;
	10649	+ struct vop2_dsc *dsc;
	10650	+ const struct dsc_error_info *dsc_error_ecw = vop2_data->dsc_error_ecw;
	10651	+ const struct dsc_error_info *dsc_error_buffer_flow = vop2_data->dsc_error_buffer_flow;
	10652	+ u32 dsc_error_status = 0, dsc_ecw = 0;
	10653	+ int i = 0, j = 0;
	10654	+
	10655	+ for (i = 0; i < vop2_data->nr_dscs; i++) {
	10656	+ dsc = &vop2->dscs[i];
	10657	+
	10658	+ if (!dsc->enabled)
	10659	+ continue;
	10660	+
	10661	+ dsc_error_status = VOP_MODULE_GET(vop2, dsc, dsc_error_status);
	10662	+ if (!dsc_error_status)
	10663	+ continue;
	10664	+ dsc_ecw = VOP_MODULE_GET(vop2, dsc, dsc_ecw);
	10665	+
	10666	+ for (j = 0; j < vop2_data->nr_dsc_ecw; j++) {
	10667	+ if (dsc_ecw == dsc_error_ecw[j].dsc_error_val) {
	10668	+ DRM_ERROR("dsc%d %s\n", dsc->id, dsc_error_ecw[j].dsc_error_info);
	10669	+ break;
	10670	+ }
	10671	+ }
	10672	+
	10673	+ if (dsc_ecw == 0x0120ffff) {
	10674	+ u32 offset = dsc->regs->dsc_status.offset;
	10675	+
	10676	+ for (j = 0; j < vop2_data->nr_dsc_buffer_flow; j++)
	10677	+ DRM_ERROR("dsc%d %s:0x%x\n", dsc->id, dsc_error_buffer_flow[j].dsc_error_info,
	10678	+ vop2_readl(vop2, offset + (j << 2)));
	10679	+ }
	10680	+ }
6621	10681	}
6622	10682
6623	10683	static irqreturn_t vop2_isr(int irq, void *data)
..	..	@@ -6674,7 +10734,7 @@
6674	10734
6675	10735	for (i = 0; i < vp_max; i++) {
6676	10736	vp = &vop2->vps[i];
6677		- crtc = &vp->crtc;
	10737	+ crtc = &vp->rockchip_crtc.crtc;
6678	10738	active_irqs = vp_irqs[i];
6679	10739	if (active_irqs & DSP_HOLD_VALID_INTR) {
6680	10740	complete(&vp->dsp_hold_completion);
..	..	@@ -6694,7 +10754,18 @@
6694	10754	ret = IRQ_HANDLED;
6695	10755	}
6696	10756
	10757	+ if (vop2->version == VOP_VERSION_RK3528 && vp->id == 1) {
	10758	+ if (active_irqs & POST_BUF_EMPTY_INTR)
	10759	+ atomic_inc(&vp->post_buf_empty_flag);
	10760	+
	10761	+ if (active_irqs & FS_FIELD_INTR &&
	10762	+ (atomic_read(&vp->post_buf_empty_flag) > 0 \|\|
	10763	+ vp->need_reset_p2i_flag == true))
	10764	+ queue_work(vop2->workqueue, &vop2->post_buf_empty_work);
	10765	+ }
	10766	+
6697	10767	if (active_irqs & FS_FIELD_INTR) {
	10768	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_VSYNC, "vsync_vp%d\n", vp->id);
6698	10769	vop2_wb_handler(vp);
6699	10770	if (likely(!vp->skip_vsync) \|\| (vp->layer_sel_update == false)) {
6700	10771	drm_crtc_handle_vblank(crtc);
..	..	@@ -6726,6 +10797,9 @@
6726	10797	if (active_irqs)
6727	10798	DRM_ERROR("Unknown axi_bus%d IRQs: %02x\n", i, active_irqs);
6728	10799	}
	10800	+
	10801	+ if (vop2->data->nr_dscs)
	10802	+ vop2_dsc_isr(vop2);
6729	10803
6730	10804	vop2_core_clks_disable(vop2);
6731	10805	out:
..	..	@@ -6784,6 +10858,51 @@
6784	10858	return 0;
6785	10859	}
6786	10860
	10861	+static bool vop3_ignore_plane(struct vop2 vop2, struct vop2_win win)
	10862	+{
	10863	+ if (!is_vop3(vop2))
	10864	+ return false;
	10865	+
	10866	+ if (vop2->esmart_lb_mode == VOP3_ESMART_8K_MODE &&
	10867	+ win->phys_id != ROCKCHIP_VOP2_ESMART0)
	10868	+ return true;
	10869	+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_MODE &&
	10870	+ (win->phys_id == ROCKCHIP_VOP2_ESMART1 \|\| win->phys_id == ROCKCHIP_VOP2_ESMART3))
	10871	+ return true;
	10872	+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE &&
	10873	+ win->phys_id == ROCKCHIP_VOP2_ESMART1)
	10874	+ return true;
	10875	+ else
	10876	+ return false;
	10877	+}
	10878	+
	10879	+static u32 vop3_esmart_linebuffer_size(struct vop2 vop2, struct vop2_win win)
	10880	+{
	10881	+ if (!is_vop3(vop2) \|\| vop2_cluster_window(win))
	10882	+ return vop2->data->max_output.width;
	10883	+
	10884	+ if (vop2->esmart_lb_mode == VOP3_ESMART_2K_2K_2K_2K_MODE \|\|
	10885	+ (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE && win->phys_id != ROCKCHIP_VOP2_ESMART0))
	10886	+ return vop2->data->max_output.width / 2;
	10887	+ else
	10888	+ return vop2->data->max_output.width;
	10889	+}
	10890	+
	10891	+static void vop3_init_esmart_scale_engine(struct vop2 *vop2)
	10892	+{
	10893	+ u8 scale_engine_num = 0;
	10894	+ struct drm_plane *plane = NULL;
	10895	+
	10896	+ drm_for_each_plane(plane, vop2->drm_dev) {
	10897	+ struct vop2_win *win = to_vop2_win(plane);
	10898	+
	10899	+ if (win->parent \|\| vop2_cluster_window(win))
	10900	+ continue;
	10901	+
	10902	+ win->scale_engine_num = scale_engine_num++;
	10903	+ }
	10904	+}
	10905	+
6787	10906	static int vop2_plane_init(struct vop2 vop2, struct vop2_win win, unsigned long possible_crtcs)
6788	10907	{
6789	10908	struct rockchip_drm_private *private = vop2->drm_dev->dev_private;
..	..	@@ -6807,6 +10926,10 @@
6807	10926	if (win->feature & WIN_FEATURE_CLUSTER_SUB)
6808	10927	return -EACCES;
6809	10928	}
	10929	+
	10930	+ /* ignore some plane register according vop3 esmart lb mode */
	10931	+ if (vop3_ignore_plane(vop2, win))
	10932	+ return -EACCES;
6810	10933
6811	10934	ret = drm_universal_plane_init(vop2->drm_dev, &win->base, possible_crtcs,
6812	10935	&vop2_plane_funcs, win->formats, win->nformats,
..	..	@@ -6847,7 +10970,7 @@
6847	10970	"INPUT_WIDTH", 0, max_width);
6848	10971	win->input_height_prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE,
6849	10972	"INPUT_HEIGHT", 0, max_height);
6850		- max_width = vop2->data->max_output.width;
	10973	+ max_width = vop3_esmart_linebuffer_size(vop2, win);
6851	10974	max_height = vop2->data->max_output.height;
6852	10975	if (win->feature & WIN_FEATURE_CLUSTER_SUB)
6853	10976	max_width >>= 1;
..	..	@@ -6883,8 +11006,7 @@
6883	11006	return 0;
6884	11007	}
6885	11008
6886		-static struct drm_plane vop2_cursor_plane_init(struct vop2_video_port vp,
6887		- unsigned long possible_crtcs)
	11009	+static struct drm_plane vop2_cursor_plane_init(struct vop2_video_port vp, u32 possible_crtcs)
6888	11010	{
6889	11011	struct vop2 *vop2 = vp->vop2;
6890	11012	struct drm_plane *cursor = NULL;
..	..	@@ -6892,6 +11014,8 @@
6892	11014
6893	11015	win = vop2_find_win_by_phys_id(vop2, vp->cursor_win_id);
6894	11016	if (win) {
	11017	+ if (win->possible_crtcs)
	11018	+ possible_crtcs = win->possible_crtcs;
6895	11019	win->type = DRM_PLANE_TYPE_CURSOR;
6896	11020	win->zpos = vop2->registered_num_wins - 1;
6897	11021	if (!vop2_plane_init(vop2, win, possible_crtcs))
..	..	@@ -6917,7 +11041,7 @@
6917	11041
6918	11042	for (i = 0; i < vop2_data->nr_vps; i++) {
6919	11043	vp = &vop2->vps[i];
6920		- crtc = &vp->crtc;
	11044	+ crtc = &vp->rockchip_crtc.crtc;
6921	11045	if (!crtc->dev)
6922	11046	continue;
6923	11047	vp_data = &vop2_data->vp[vp->id];
..	..	@@ -6925,6 +11049,7 @@
6925	11049	if (!lut_len)
6926	11050	continue;
6927	11051	vp->gamma_lut_len = vp_data->gamma_lut_len;
	11052	+ vp->lut_dma_rid = vp_data->lut_dma_rid;
6928	11053	vp->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vp->lut),
6929	11054	GFP_KERNEL);
6930	11055	if (!vp->lut)
..	..	@@ -6951,27 +11076,6 @@
6951	11076	}
6952	11077
6953	11078	return 0;
6954		-}
6955		-
6956		-static void vop2_cubic_lut_init(struct vop2 *vop2)
6957		-{
6958		- const struct vop2_data *vop2_data = vop2->data;
6959		- const struct vop2_video_port_data *vp_data;
6960		- struct vop2_video_port *vp;
6961		- struct drm_crtc *crtc;
6962		- int i;
6963		-
6964		- for (i = 0; i < vop2_data->nr_vps; i++) {
6965		- vp = &vop2->vps[i];
6966		- crtc = &vp->crtc;
6967		- if (!crtc->dev)
6968		- continue;
6969		- vp_data = &vop2_data->vp[vp->id];
6970		- vp->cubic_lut_len = vp_data->cubic_lut_len;
6971		-
6972		- if (vp->cubic_lut_len)
6973		- drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len);
6974		- }
6975	11079	}
6976	11080
6977	11081	static int vop2_crtc_create_plane_mask_property(struct vop2 *vop2,
..	..	@@ -7009,6 +11113,142 @@
7009	11113	return 0;
7010	11114	}
7011	11115
	11116	+static int vop2_crtc_create_feature_property(struct vop2 vop2, struct drm_crtc crtc)
	11117	+{
	11118	+ const struct vop2_data *vop2_data = vop2->data;
	11119	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11120	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	11121	+ struct drm_property *prop;
	11122	+ u64 feature = 0;
	11123	+
	11124	+ static const struct drm_prop_enum_list props[] = {
	11125	+ { ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE, "ALPHA_SCALE" },
	11126	+ { ROCKCHIP_DRM_CRTC_FEATURE_HDR10, "HDR10" },
	11127	+ { ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR, "NEXT_HDR" },
	11128	+ { ROCKCHIP_DRM_CRTC_FEATURE_VIVID_HDR, "VIVID_HDR" },
	11129	+ };
	11130	+
	11131	+ if (vp_data->feature & VOP_FEATURE_ALPHA_SCALE)
	11132	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE);
	11133	+ if (vp_data->feature & VOP_FEATURE_HDR10)
	11134	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_HDR10);
	11135	+ if (vp_data->feature & VOP_FEATURE_NEXT_HDR)
	11136	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR);
	11137	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	11138	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_VIVID_HDR);
	11139	+
	11140	+ prop = drm_property_create_bitmask(vop2->drm_dev,
	11141	+ DRM_MODE_PROP_IMMUTABLE, "FEATURE",
	11142	+ props, ARRAY_SIZE(props),
	11143	+ 0xffffffff);
	11144	+ if (!prop) {
	11145	+ DRM_DEV_ERROR(vop2->dev, "create FEATURE prop for vp%d failed\n", vp->id);
	11146	+ return -ENOMEM;
	11147	+ }
	11148	+
	11149	+ vp->feature_prop = prop;
	11150	+ drm_object_attach_property(&crtc->base, vp->feature_prop, feature);
	11151	+
	11152	+ prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_WIDTH",
	11153	+ 0, vop2->data->vp[vp->id].max_output.width);
	11154	+ if (!prop) {
	11155	+ DRM_DEV_ERROR(vop2->dev, "create OUTPUT_WIDTH prop for vp%d failed\n", vp->id);
	11156	+ return -ENOMEM;
	11157	+ }
	11158	+ vp->output_width_prop = prop;
	11159	+ drm_object_attach_property(&crtc->base, vp->output_width_prop, 0);
	11160	+
	11161	+ prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_DCLK",
	11162	+ 0, rockchip_drm_get_dclk_by_width(vop2->data->vp[vp->id].max_output.width) * 1000);
	11163	+ if (!prop) {
	11164	+ DRM_DEV_ERROR(vop2->dev, "create OUTPUT_DCLK prop for vp%d failed\n", vp->id);
	11165	+ return -ENOMEM;
	11166	+ }
	11167	+ vp->output_dclk_prop = prop;
	11168	+ drm_object_attach_property(&crtc->base, vp->output_dclk_prop, 0);
	11169	+
	11170	+ return 0;
	11171	+}
	11172	+
	11173	+static int vop2_crtc_create_vrr_property(struct vop2 vop2, struct drm_crtc crtc)
	11174	+{
	11175	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11176	+ struct drm_property *prop;
	11177	+
	11178	+ prop = drm_property_create_range(vop2->drm_dev, 0, "variable refresh rate", 0, 144);
	11179	+ if (!prop) {
	11180	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	11181	+ return -ENOMEM;
	11182	+ }
	11183	+ vp->variable_refresh_rate_prop = prop;
	11184	+ drm_object_attach_property(&crtc->base, vp->variable_refresh_rate_prop, 0);
	11185	+
	11186	+ prop = drm_property_create_range(vop2->drm_dev, 0, "max refresh rate", 0, 144);
	11187	+ if (!prop) {
	11188	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	11189	+ return -ENOMEM;
	11190	+ }
	11191	+ vp->max_refresh_rate_prop = prop;
	11192	+ drm_object_attach_property(&crtc->base, vp->max_refresh_rate_prop, 0);
	11193	+
	11194	+ prop = drm_property_create_range(vop2->drm_dev, 0, "min refresh rate", 0, 144);
	11195	+ if (!prop) {
	11196	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	11197	+ return -ENOMEM;
	11198	+ }
	11199	+ vp->min_refresh_rate_prop = prop;
	11200	+ drm_object_attach_property(&crtc->base, vp->min_refresh_rate_prop, 0);
	11201	+
	11202	+ return 0;
	11203	+}
	11204	+
	11205	+static int vop2_crtc_create_hdr_property(struct vop2 vop2, struct drm_crtc crtc)
	11206	+{
	11207	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11208	+ struct drm_property *prop;
	11209	+
	11210	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "HDR_EXT_DATA", 0);
	11211	+ if (!prop) {
	11212	+ DRM_DEV_ERROR(vop2->dev, "create hdr ext data prop for vp%d failed\n", vp->id);
	11213	+ return -ENOMEM;
	11214	+ }
	11215	+ vp->hdr_ext_data_prop = prop;
	11216	+ drm_object_attach_property(&crtc->base, vp->hdr_ext_data_prop, 0);
	11217	+
	11218	+ return 0;
	11219	+}
	11220	+
	11221	+static int vop2_crtc_create_post_acm_property(struct vop2 vop2, struct drm_crtc crtc)
	11222	+{
	11223	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11224	+ struct drm_property *prop;
	11225	+
	11226	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "ACM_LUT_DATA", 0);
	11227	+ if (!prop) {
	11228	+ DRM_DEV_ERROR(vop2->dev, "create acm lut data prop for vp%d failed\n", vp->id);
	11229	+ return -ENOMEM;
	11230	+ }
	11231	+ vp->acm_lut_data_prop = prop;
	11232	+ drm_object_attach_property(&crtc->base, vp->acm_lut_data_prop, 0);
	11233	+
	11234	+ return 0;
	11235	+}
	11236	+
	11237	+static int vop2_crtc_create_post_csc_property(struct vop2 vop2, struct drm_crtc crtc)
	11238	+{
	11239	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11240	+ struct drm_property *prop;
	11241	+
	11242	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "POST_CSC_DATA", 0);
	11243	+ if (!prop) {
	11244	+ DRM_DEV_ERROR(vop2->dev, "create post csc data prop for vp%d failed\n", vp->id);
	11245	+ return -ENOMEM;
	11246	+ }
	11247	+ vp->post_csc_data_prop = prop;
	11248	+ drm_object_attach_property(&crtc->base, vp->post_csc_data_prop, 0);
	11249	+
	11250	+ return 0;
	11251	+}
7012	11252	#define RK3566_MIRROR_PLANE_MASK (BIT(ROCKCHIP_VOP2_CLUSTER1) \| BIT(ROCKCHIP_VOP2_ESMART1) \| \
7013	11253	BIT(ROCKCHIP_VOP2_SMART1))
7014	11254
..	..	@@ -7021,7 +11261,7 @@
7021	11261	const struct vop2_data *vop2_data = vop2->data;
7022	11262	struct drm_device *drm_dev = vop2->drm_dev;
7023	11263	struct device *dev = vop2->dev;
7024		- struct drm_plane *plane;
	11264	+ struct drm_plane *primary;
7025	11265	struct drm_plane *cursor = NULL;
7026	11266	struct drm_crtc *crtc;
7027	11267	struct device_node *port;
..	..	@@ -7032,12 +11272,13 @@
7032	11272	uint64_t soc_id;
7033	11273	uint32_t registered_num_crtcs = 0;
7034	11274	uint32_t plane_mask = 0;
7035		- char dclk_name[9];
	11275	+ char clk_name[16];
7036	11276	int i = 0, j = 0, k = 0;
7037	11277	int ret = 0;
7038	11278	bool be_used_for_primary_plane = false;
7039	11279	bool find_primary_plane = false;
7040	11280	bool bootloader_initialized = false;
	11281	+ struct rockchip_drm_private *private = drm_dev->dev_private;
7041	11282
7042	11283	/* all planes can attach to any crtc */
7043	11284	possible_crtcs = (1 << vop2_data->nr_vps) - 1;
..	..	@@ -7069,29 +11310,47 @@
7069	11310	vp->id = vp_data->id;
7070	11311	vp->regs = vp_data->regs;
7071	11312	vp->cursor_win_id = -1;
	11313	+ primary = NULL;
	11314	+ cursor = NULL;
	11315	+
7072	11316	if (vop2->disable_win_move)
7073	11317	possible_crtcs = BIT(registered_num_crtcs);
7074	11318
7075	11319	/*
7076		- * we assume a vp with a zere plane_mask(set from dts or bootloader)
	11320	+ * we assume a vp with a zero plane_mask(set from dts or bootloader)
7077	11321	* as unused.
7078	11322	*/
7079		- if (!vp->plane_mask && bootloader_initialized)
	11323	+ if (!vp->plane_mask && bootloader_initialized) {
	11324	+ DRM_DEV_INFO(vop2->dev, "VP%d plane_mask is zero, so ignore register crtc\n", vp->id);
7080	11325	continue;
	11326	+ }
7081	11327
7082	11328	if (vop2_soc_is_rk3566())
7083	11329	soc_id = vp_data->soc_id[1];
7084	11330	else
7085	11331	soc_id = vp_data->soc_id[0];
7086	11332
7087		- snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
7088		- vp->dclk = devm_clk_get(vop2->dev, dclk_name);
	11333	+ snprintf(clk_name, sizeof(clk_name), "dclk_vp%d", vp->id);
	11334	+ vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, clk_name);
	11335	+ if (IS_ERR(vp->dclk_rst)) {
	11336	+ DRM_DEV_ERROR(vop2->dev, "failed to get dclk reset\n");
	11337	+ return PTR_ERR(vp->dclk_rst);
	11338	+ }
	11339	+
	11340	+ vp->dclk = devm_clk_get(vop2->dev, clk_name);
7089	11341	if (IS_ERR(vp->dclk)) {
7090		- DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", dclk_name);
	11342	+ DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", clk_name);
7091	11343	return PTR_ERR(vp->dclk);
7092	11344	}
7093	11345
7094		- crtc = &vp->crtc;
	11346	+ snprintf(clk_name, sizeof(clk_name), "dclk_src_vp%d", vp->id);
	11347	+ vp->dclk_parent = devm_clk_get_optional(vop2->dev, clk_name);
	11348	+ if (IS_ERR(vp->dclk)) {
	11349	+ DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", clk_name);
	11350	+ return PTR_ERR(vp->dclk);
	11351	+ }
	11352	+
	11353	+ crtc = &vp->rockchip_crtc.crtc;
7095	11354
7096	11355	port = of_graph_get_port_by_id(dev->of_node, i);
7097	11356	if (!port) {
..	..	@@ -7116,6 +11375,7 @@
7116	11375	win->type = DRM_PLANE_TYPE_PRIMARY;
7117	11376	}
7118	11377	} else {
	11378	+ j = 0;
7119	11379	while (j < vop2->registered_num_wins) {
7120	11380	be_used_for_primary_plane = false;
7121	11381	win = &vop2->win[j];
..	..	@@ -7157,24 +11417,43 @@
7157	11417	DRM_DEV_ERROR(vop2->dev, "failed to init primary plane\n");
7158	11418	break;
7159	11419	}
7160		- plane = &win->base;
	11420	+ primary = &win->base;
7161	11421	}
7162	11422
7163	11423	/* some times we want a cursor window for some vp */
	11424	+ if (vp->cursor_win_id < 0) {
	11425	+ bool be_used_for_cursor_plane = false;
	11426	+
	11427	+ j = 0;
	11428	+ while (j < vop2->registered_num_wins) {
	11429	+ win = &vop2->win[j++];
	11430	+
	11431	+ if (win->parent \|\| (win->feature & WIN_FEATURE_CLUSTER_SUB))
	11432	+ continue;
	11433	+
	11434	+ if (win->type != DRM_PLANE_TYPE_CURSOR)
	11435	+ continue;
	11436	+
	11437	+ for (k = 0; k < vop2_data->nr_vps; k++) {
	11438	+ if (vop2->vps[k].cursor_win_id == win->phys_id)
	11439	+ be_used_for_cursor_plane = true;
	11440	+ }
	11441	+ if (be_used_for_cursor_plane)
	11442	+ continue;
	11443	+ vp->cursor_win_id = win->phys_id;
	11444	+ }
	11445	+ }
	11446	+
7164	11447	if (vp->cursor_win_id >= 0) {
7165		- if (win->possible_crtcs)
7166		- possible_crtcs = win->possible_crtcs;
7167	11448	cursor = vop2_cursor_plane_init(vp, possible_crtcs);
7168	11449	if (!cursor)
7169	11450	DRM_WARN("failed to init cursor plane for vp%d\n", vp->id);
7170	11451	else
7171	11452	DRM_DEV_INFO(vop2->dev, "%s as cursor plane for vp%d\n",
7172	11453	cursor->name, vp->id);
7173		- } else {
7174		- cursor = NULL;
7175	11454	}
7176	11455
7177		- ret = drm_crtc_init_with_planes(drm_dev, crtc, plane, cursor, &vop2_crtc_funcs,
	11456	+ ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, &vop2_crtc_funcs,
7178	11457	"video_port%d", vp->id);
7179	11458	if (ret) {
7180	11459	DRM_DEV_ERROR(vop2->dev, "crtc init for video_port%d failed\n", i);
..	..	@@ -7189,20 +11468,39 @@
7189	11468	init_completion(&vp->line_flag_completion);
7190	11469	rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
7191	11470	soc_id = vop2_soc_id_fixup(soc_id);
7192		- drm_object_attach_property(&crtc->base, vop2->soc_id_prop, soc_id);
7193		- drm_object_attach_property(&crtc->base, vop2->vp_id_prop, vp->id);
7194		- drm_object_attach_property(&crtc->base, vop2->aclk_prop, 0);
7195		- drm_object_attach_property(&crtc->base, vop2->bg_prop, 0);
7196		- drm_object_attach_property(&crtc->base, vop2->line_flag_prop, 0);
7197		- drm_object_attach_property(&crtc->base,
7198		- drm_dev->mode_config.tv_left_margin_property, 100);
7199		- drm_object_attach_property(&crtc->base,
7200		- drm_dev->mode_config.tv_right_margin_property, 100);
7201		- drm_object_attach_property(&crtc->base,
7202		- drm_dev->mode_config.tv_top_margin_property, 100);
7203		- drm_object_attach_property(&crtc->base,
7204		- drm_dev->mode_config.tv_bottom_margin_property, 100);
7205		- vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask);
	11471	+ drm_object_attach_property(&crtc->base, private->soc_id_prop, soc_id);
	11472	+ drm_object_attach_property(&crtc->base, private->port_id_prop, vp->id);
	11473	+ drm_object_attach_property(&crtc->base, private->aclk_prop, 0);
	11474	+ drm_object_attach_property(&crtc->base, private->bg_prop, 0);
	11475	+ drm_object_attach_property(&crtc->base, private->line_flag_prop, 0);
	11476	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN) {
	11477	+ drm_object_attach_property(&crtc->base,
	11478	+ drm_dev->mode_config.tv_left_margin_property, 100);
	11479	+ drm_object_attach_property(&crtc->base,
	11480	+ drm_dev->mode_config.tv_right_margin_property, 100);
	11481	+ drm_object_attach_property(&crtc->base,
	11482	+ drm_dev->mode_config.tv_top_margin_property, 100);
	11483	+ drm_object_attach_property(&crtc->base,
	11484	+ drm_dev->mode_config.tv_bottom_margin_property, 100);
	11485	+ }
	11486	+ if (plane_mask)
	11487	+ vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask);
	11488	+ vop2_crtc_create_feature_property(vop2, crtc);
	11489	+ vop2_crtc_create_vrr_property(vop2, crtc);
	11490	+
	11491	+ ret = drm_self_refresh_helper_init(crtc);
	11492	+ if (ret)
	11493	+ DRM_DEV_DEBUG_KMS(vop2->dev,
	11494	+ "Failed to init %s with SR helpers %d, ignoring\n",
	11495	+ crtc->name, ret);
	11496	+
	11497	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	11498	+ vop2_crtc_create_hdr_property(vop2, crtc);
	11499	+ if (vp_data->feature & VOP_FEATURE_POST_ACM)
	11500	+ vop2_crtc_create_post_acm_property(vop2, crtc);
	11501	+ if (vp_data->feature & VOP_FEATURE_POST_CSC)
	11502	+ vop2_crtc_create_post_csc_property(vop2, crtc);
	11503	+
7206	11504	registered_num_crtcs++;
7207	11505	}
7208	11506
..	..	@@ -7257,8 +11555,11 @@
7257	11555
7258	11556	ret = vop2_plane_init(vop2, win, possible_crtcs);
7259	11557	if (ret)
7260		- DRM_WARN("failed to init overlay plane %s, ret:%d\n", win->name, ret);
	11558	+ DRM_WARN("failed to init overlay plane %s\n", win->name);
7261	11559	}
	11560	+
	11561	+ if (is_vop3(vop2))
	11562	+ vop3_init_esmart_scale_engine(vop2);
7262	11563
7263	11564	return registered_num_crtcs;
7264	11565	}
..	..	@@ -7266,6 +11567,10 @@
7266	11567	static void vop2_destroy_crtc(struct drm_crtc *crtc)
7267	11568	{
7268	11569	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11570	+
	11571	+ drm_self_refresh_helper_cleanup(crtc);
	11572	+ if (vp->hdr_lut_gem_obj)
	11573	+ rockchip_gem_free_object(&vp->hdr_lut_gem_obj->base);
7269	11574
7270	11575	of_node_put(crtc->port);
7271	11576
..	..	@@ -7277,6 +11582,59 @@
7277	11582	drm_flip_work_cleanup(&vp->fb_unref_work);
7278	11583	}
7279	11584
	11585	+static int vop2_pd_data_init(struct vop2 *vop2)
	11586	+{
	11587	+ const struct vop2_data *vop2_data = vop2->data;
	11588	+ const struct vop2_power_domain_data *pd_data;
	11589	+ struct vop2_power_domain *pd;
	11590	+ int i;
	11591	+
	11592	+ INIT_LIST_HEAD(&vop2->pd_list_head);
	11593	+
	11594	+ for (i = 0; i < vop2_data->nr_pds; i++) {
	11595	+ pd_data = &vop2_data->pd[i];
	11596	+ pd = devm_kzalloc(vop2->dev, sizeof(*pd), GFP_KERNEL);
	11597	+ if (!pd)
	11598	+ return -ENOMEM;
	11599	+ pd->vop2 = vop2;
	11600	+ pd->data = pd_data;
	11601	+ pd->vp_mask = 0;
	11602	+ spin_lock_init(&pd->lock);
	11603	+ list_add_tail(&pd->list, &vop2->pd_list_head);
	11604	+ INIT_DELAYED_WORK(&pd->power_off_work, vop2_power_domain_off_work);
	11605	+ if (pd_data->parent_id) {
	11606	+ pd->parent = vop2_find_pd_by_id(vop2, pd_data->parent_id);
	11607	+ if (!pd->parent) {
	11608	+ DRM_DEV_ERROR(vop2->dev, "no parent pd find for pd%d\n", pd->data->id);
	11609	+ return -EINVAL;
	11610	+ }
	11611	+ }
	11612	+ }
	11613	+
	11614	+ return 0;
	11615	+}
	11616	+
	11617	+static void vop2_dsc_data_init(struct vop2 *vop2)
	11618	+{
	11619	+ const struct vop2_data *vop2_data = vop2->data;
	11620	+ const struct vop2_dsc_data *dsc_data;
	11621	+ struct vop2_dsc *dsc;
	11622	+ int i;
	11623	+
	11624	+ for (i = 0; i < vop2_data->nr_dscs; i++) {
	11625	+ dsc = &vop2->dscs[i];
	11626	+ dsc_data = &vop2_data->dsc[i];
	11627	+ dsc->id = dsc_data->id;
	11628	+ dsc->max_slice_num = dsc_data->max_slice_num;
	11629	+ dsc->max_linebuf_depth = dsc_data->max_linebuf_depth;
	11630	+ dsc->min_bits_per_pixel = dsc_data->min_bits_per_pixel;
	11631	+ dsc->regs = dsc_data->regs;
	11632	+ dsc->attach_vp_id = -1;
	11633	+ if (dsc_data->pd_id)
	11634	+ dsc->pd = vop2_find_pd_by_id(vop2, dsc_data->pd_id);
	11635	+ }
	11636	+}
	11637	+
7280	11638	static int vop2_win_init(struct vop2 *vop2)
7281	11639	{
7282	11640	const struct vop2_data *vop2_data = vop2->data;
..	..	@@ -7284,8 +11642,8 @@
7284	11642	struct drm_prop_enum_list *plane_name_list;
7285	11643	struct vop2_win *win;
7286	11644	struct vop2_layer *layer;
7287		- struct drm_property *prop;
7288	11645	char name[DRM_PROP_NAME_LEN];
	11646	+ char area_name[DRM_PROP_NAME_LEN];
7289	11647	unsigned int num_wins = 0;
7290	11648	uint8_t plane_id = 0;
7291	11649	unsigned int i, j;
..	..	@@ -7313,6 +11671,7 @@
7313	11671	win->dly = win_data->dly;
7314	11672	win->feature = win_data->feature;
7315	11673	win->phys_id = win_data->phys_id;
	11674	+ win->splice_win_id = win_data->splice_win_id;
7316	11675	win->layer_sel_id = win_data->layer_sel_id;
7317	11676	win->win_id = i;
7318	11677	win->plane_id = plane_id++;
..	..	@@ -7322,8 +11681,10 @@
7322	11681	win->axi_id = win_data->axi_id;
7323	11682	win->axi_yrgb_id = win_data->axi_yrgb_id;
7324	11683	win->axi_uv_id = win_data->axi_uv_id;
7325		- win->scale_engine_num = win_data->scale_engine_num;
7326	11684	win->possible_crtcs = win_data->possible_crtcs;
	11685	+
	11686	+ if (win_data->pd_id)
	11687	+ win->pd = vop2_find_pd_by_id(vop2, win_data->pd_id);
7327	11688
7328	11689	num_wins++;
7329	11690
..	..	@@ -7351,18 +11712,20 @@
7351	11712	area->vsd_filter_mode = win_data->vsd_filter_mode;
7352	11713	area->hsd_pre_filter_mode = win_data->hsd_pre_filter_mode;
7353	11714	area->vsd_pre_filter_mode = win_data->vsd_pre_filter_mode;
	11715	+ area->possible_crtcs = win->possible_crtcs;
7354	11716
7355	11717	area->vop2 = vop2;
7356	11718	area->win_id = i;
7357	11719	area->phys_id = win->phys_id;
7358	11720	area->area_id = j + 1;
7359	11721	area->plane_id = plane_id++;
7360		- snprintf(name, min(sizeof(name), strlen(win->name)), "%s", win->name);
7361		- snprintf(name, sizeof(name), "%s%d", name, area->area_id);
	11722	+ snprintf(area_name, min(sizeof(area_name), strlen(win->name)), "%s", win->name);
	11723	+ snprintf(name, sizeof(name), "%s%d", area_name, area->area_id);
7362	11724	area->name = devm_kstrdup(vop2->dev, name, GFP_KERNEL);
7363	11725	num_wins++;
7364	11726	}
7365	11727	}
	11728	+
7366	11729	vop2->registered_num_wins = num_wins;
7367	11730
7368	11731	if (!is_vop3(vop2)) {
..	..	@@ -7390,28 +11753,136 @@
7390	11753
7391	11754	vop2->plane_name_list = plane_name_list;
7392	11755
7393		- prop = drm_property_create_object(vop2->drm_dev,
7394		- DRM_MODE_PROP_ATOMIC \| DRM_MODE_PROP_IMMUTABLE,
7395		- "SOC_ID", DRM_MODE_OBJECT_CRTC);
7396		- vop2->soc_id_prop = prop;
	11756	+ return 0;
	11757	+}
7397	11758
7398		- prop = drm_property_create_object(vop2->drm_dev,
7399		- DRM_MODE_PROP_ATOMIC \| DRM_MODE_PROP_IMMUTABLE,
7400		- "PORT_ID", DRM_MODE_OBJECT_CRTC);
7401		- vop2->vp_id_prop = prop;
	11759	+#include "rockchip_vop2_clk.c"
	11760	+static void post_buf_empty_work_event(struct work_struct *work)
	11761	+{
	11762	+ struct vop2 *vop2 = container_of(work, struct vop2, post_buf_empty_work);
	11763	+ struct rockchip_drm_private *private = vop2->drm_dev->dev_private;
	11764	+ struct vop2_video_port *vp = &vop2->vps[1];
7402	11765
7403		- vop2->aclk_prop = drm_property_create_range(vop2->drm_dev, 0, "ACLK", 0, UINT_MAX);
7404		- vop2->bg_prop = drm_property_create_range(vop2->drm_dev, 0, "BACKGROUND", 0, UINT_MAX);
	11766	+ /*
	11767	+ * For RK3528, VP1 only supports NTSC and PAL mode(both interlace). If
	11768	+ * POST_BUF_EMPTY_INTR comes, it is needed to reset the p2i_en bit, in
	11769	+ * order to update the line parity flag, which ensures the correct order
	11770	+ * of odd and even lines.
	11771	+ */
	11772	+ if (vop2->version == VOP_VERSION_RK3528) {
	11773	+ if (atomic_read(&vp->post_buf_empty_flag) > 0) {
	11774	+ atomic_set(&vp->post_buf_empty_flag, 0);
7405	11775
7406		- vop2->line_flag_prop = drm_property_create_range(vop2->drm_dev, 0, "LINE_FLAG1", 0, UINT_MAX);
	11776	+ mutex_lock(&private->ovl_lock);
	11777	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11778	+ VOP_MODULE_SET(vop2, vp, p2i_en, 0);
	11779	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	11780	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11781	+ mutex_unlock(&private->ovl_lock);
7407	11782
7408		- if (!vop2->soc_id_prop \|\| !vop2->vp_id_prop \|\| !vop2->aclk_prop \|\| !vop2->bg_prop \|\|
7409		- !vop2->line_flag_prop) {
7410		- DRM_DEV_ERROR(vop2->dev, "failed to create soc_id/vp_id/aclk property\n");
7411		- return -ENOMEM;
	11783	+ vp->need_reset_p2i_flag = true;
	11784	+ } else if (vp->need_reset_p2i_flag == true) {
	11785	+ mutex_lock(&private->ovl_lock);
	11786	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11787	+ VOP_MODULE_SET(vop2, vp, p2i_en, 1);
	11788	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	11789	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11790	+ mutex_unlock(&private->ovl_lock);
	11791	+
	11792	+ vp->need_reset_p2i_flag = false;
	11793	+ }
	11794	+ }
	11795	+}
	11796	+
	11797	+static bool vop2_plane_mask_check(struct vop2 *vop2)
	11798	+{
	11799	+ const struct vop2_data *vop2_data = vop2->data;
	11800	+ u32 plane_mask = 0;
	11801	+ int i;
	11802	+
	11803	+ /*
	11804	+ * For RK3568 and RK3588, all windows need to be assigned to
	11805	+ * one of all vps, and two of vps can not share the same window.
	11806	+ */
	11807	+ if (vop2->version != VOP_VERSION_RK3568 && vop2->version != VOP_VERSION_RK3588)
	11808	+ return true;
	11809	+
	11810	+ for (i = 0; i < vop2_data->nr_vps; i++) {
	11811	+ if (plane_mask & vop2->vps[i].plane_mask) {
	11812	+ DRM_WARN("the same window can't be assigned to two vp\n");
	11813	+ return false;
	11814	+ }
	11815	+ plane_mask \|= vop2->vps[i].plane_mask;
7412	11816	}
7413	11817
7414		- return 0;
	11818	+ if (hweight32(plane_mask) != vop2_data->nr_layers \|\|
	11819	+ plane_mask != vop2_data->plane_mask_base) {
	11820	+ DRM_WARN("all windows should be assigned, full plane mask: 0x%x, current plane mask: 0x%x\n",
	11821	+ vop2_data->plane_mask_base, plane_mask);
	11822	+ return false;
	11823	+ }
	11824	+
	11825	+ return true;
	11826	+}
	11827	+
	11828	+static uint32_t vop2_vp_plane_mask_to_bitmap(const struct vop2_vp_plane_mask *vp_plane_mask)
	11829	+{
	11830	+ int layer_phy_id = 0;
	11831	+ int plane_mask = 0;
	11832	+ int i;
	11833	+
	11834	+ for (i = 0; i < vp_plane_mask->attached_layers_nr; i++) {
	11835	+ layer_phy_id = vp_plane_mask->attached_layers[i];
	11836	+ plane_mask \|= BIT(layer_phy_id);
	11837	+ }
	11838	+
	11839	+ return plane_mask;
	11840	+}
	11841	+
	11842	+static bool vop2_get_vp_of_status(struct device_node *vp_node)
	11843	+{
	11844	+ struct device_node *vp_sub_node;
	11845	+ struct device_node *remote_node;
	11846	+ bool vp_enable = false;
	11847	+
	11848	+ for_each_child_of_node(vp_node, vp_sub_node) {
	11849	+ remote_node = of_graph_get_remote_endpoint(vp_sub_node);
	11850	+ vp_enable \|= of_device_is_available(remote_node);
	11851	+ }
	11852	+
	11853	+ return vp_enable;
	11854	+}
	11855	+
	11856	+static void vop2_plane_mask_assign(struct vop2 vop2, struct device_node vop_out_node)
	11857	+{
	11858	+ const struct vop2_data *vop2_data = vop2->data;
	11859	+ const struct vop2_vp_plane_mask *plane_mask;
	11860	+ struct device_node *child;
	11861	+ int active_vp_num = 0;
	11862	+ int vp_id;
	11863	+ int i = 0;
	11864	+
	11865	+ for_each_child_of_node(vop_out_node, child) {
	11866	+ if (vop2_get_vp_of_status(child))
	11867	+ active_vp_num++;
	11868	+ }
	11869	+
	11870	+ if (vop2_soc_is_rk3566() && active_vp_num > 2)
	11871	+ DRM_WARN("RK3566 only support 2 vps\n");
	11872	+ plane_mask = vop2_data->plane_mask;
	11873	+ plane_mask += (active_vp_num - 1) * ROCKCHIP_MAX_CRTC;
	11874	+
	11875	+ for_each_child_of_node(vop_out_node, child) {
	11876	+ of_property_read_u32(child, "reg", &vp_id);
	11877	+ if (vop2_get_vp_of_status(child)) {
	11878	+ vop2->vps[vp_id].plane_mask = vop2_vp_plane_mask_to_bitmap(&plane_mask[i]);
	11879	+ vop2->vps[vp_id].primary_plane_phy_id = plane_mask[i].primary_plane_id;
	11880	+ i++;
	11881	+ } else {
	11882	+ vop2->vps[vp_id].plane_mask = 0;
	11883	+ vop2->vps[vp_id].primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
	11884	+ }
	11885	+ }
7415	11886	}
7416	11887
7417	11888	static int vop2_bind(struct device dev, struct device master, void *data)
..	..	@@ -7426,6 +11897,7 @@
7426	11897	int num_wins = 0;
7427	11898	int registered_num_crtcs;
7428	11899	struct device_node *vop_out_node;
	11900	+ struct device_node *mcu_timing_node;
7429	11901
7430	11902	vop2_data = of_device_get_match_data(dev);
7431	11903	if (!vop2_data)
..	..	@@ -7454,6 +11926,26 @@
7454	11926	vop2->disable_afbc_win = of_property_read_bool(dev->of_node, "disable-afbc-win");
7455	11927	vop2->disable_win_move = of_property_read_bool(dev->of_node, "disable-win-move");
7456	11928	vop2->skip_ref_fb = of_property_read_bool(dev->of_node, "skip-ref-fb");
	11929	+
	11930	+ ret = vop2_pd_data_init(vop2);
	11931	+ if (ret)
	11932	+ return ret;
	11933	+ /*
	11934	+ * esmart lb mode default config at vop2_reg.c vop2_data.esmart_lb_mode,
	11935	+ * you can rewrite at dts vop node:
	11936	+ *
	11937	+ * VOP3_ESMART_8K_MODE = 0,
	11938	+ * VOP3_ESMART_4K_4K_MODE = 1,
	11939	+ * VOP3_ESMART_4K_2K_2K_MODE = 2,
	11940	+ * VOP3_ESMART_2K_2K_2K_2K_MODE = 3,
	11941	+ *
	11942	+ * &vop {
	11943	+ * esmart_lb_mode = /bits/ 8 <2>;
	11944	+ * };
	11945	+ */
	11946	+ ret = of_property_read_u8(dev->of_node, "esmart_lb_mode", &vop2->esmart_lb_mode);
	11947	+ if (ret < 0)
	11948	+ vop2->esmart_lb_mode = vop2->data->esmart_lb_mode;
7457	11949
7458	11950	ret = vop2_win_init(vop2);
7459	11951	if (ret)
..	..	@@ -7488,7 +11980,10 @@
7488	11980	return PTR_ERR(vop2->acm_regs);
7489	11981	}
7490	11982
7491		- vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
	11983	+ vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
	11984	+ vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf");
	11985	+ vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf");
	11986	+ vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
7492	11987
7493	11988	vop2->hclk = devm_clk_get(vop2->dev, "hclk_vop");
7494	11989	if (IS_ERR(vop2->hclk)) {
..	..	@@ -7500,6 +11995,28 @@
7500	11995	DRM_DEV_ERROR(vop2->dev, "failed to get aclk source\n");
7501	11996	return PTR_ERR(vop2->aclk);
7502	11997	}
	11998	+
	11999	+ vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop");
	12000	+ if (IS_ERR(vop2->pclk)) {
	12001	+ DRM_DEV_ERROR(vop2->dev, "failed to get pclk source\n");
	12002	+ return PTR_ERR(vop2->pclk);
	12003	+ }
	12004	+
	12005	+ vop2->ahb_rst = devm_reset_control_get_optional(vop2->dev, "ahb");
	12006	+ if (IS_ERR(vop2->ahb_rst)) {
	12007	+ DRM_DEV_ERROR(vop2->dev, "failed to get ahb reset\n");
	12008	+ return PTR_ERR(vop2->ahb_rst);
	12009	+ }
	12010	+
	12011	+ vop2->axi_rst = devm_reset_control_get_optional(vop2->dev, "axi");
	12012	+ if (IS_ERR(vop2->axi_rst)) {
	12013	+ DRM_DEV_ERROR(vop2->dev, "failed to get axi reset\n");
	12014	+ return PTR_ERR(vop2->axi_rst);
	12015	+ }
	12016	+
	12017	+ vop2->csu_aclk = rockchip_csu_get(dev, "aclk");
	12018	+ if (IS_ERR(vop2->csu_aclk))
	12019	+ vop2->csu_aclk = NULL;
7503	12020
7504	12021	vop2->irq = platform_get_irq(pdev, 0);
7505	12022	if (vop2->irq < 0) {
..	..	@@ -7515,6 +12032,7 @@
7515	12032	u32 plane_mask = 0;
7516	12033	u32 primary_plane_phy_id = 0;
7517	12034	u32 vp_id = 0;
	12035	+ u32 val = 0;
7518	12036
7519	12037	of_property_read_u32(child, "rockchip,plane-mask", &plane_mask);
7520	12038	of_property_read_u32(child, "rockchip,primary-plane", &primary_plane_phy_id);
..	..	@@ -7528,26 +12046,66 @@
7528	12046
7529	12047	vop2->vps[vp_id].xmirror_en = of_property_read_bool(child, "xmirror-enable");
7530	12048
	12049	+ ret = of_clk_set_defaults(child, false);
	12050	+ if (ret) {
	12051	+ DRM_DEV_ERROR(dev, "Failed to set clock defaults %d\n", ret);
	12052	+ return ret;
	12053	+ }
	12054	+
	12055	+ mcu_timing_node = of_get_child_by_name(child, "mcu-timing");
	12056	+ if (mcu_timing_node) {
	12057	+ if (!of_property_read_u32(mcu_timing_node, "mcu-pix-total", &val))
	12058	+ vop2->vps[vp_id].mcu_timing.mcu_pix_total = val;
	12059	+ if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pst", &val))
	12060	+ vop2->vps[vp_id].mcu_timing.mcu_cs_pst = val;
	12061	+ if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pend", &val))
	12062	+ vop2->vps[vp_id].mcu_timing.mcu_cs_pend = val;
	12063	+ if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pst", &val))
	12064	+ vop2->vps[vp_id].mcu_timing.mcu_rw_pst = val;
	12065	+ if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pend", &val))
	12066	+ vop2->vps[vp_id].mcu_timing.mcu_rw_pend = val;
	12067	+ if (!of_property_read_u32(mcu_timing_node, "mcu-hold-mode", &val))
	12068	+ vop2->vps[vp_id].mcu_timing.mcu_hold_mode = val;
	12069	+ }
	12070	+ }
	12071	+
	12072	+ if (!vop2_plane_mask_check(vop2)) {
	12073	+ DRM_WARN("use default plane mask\n");
	12074	+ vop2_plane_mask_assign(vop2, vop_out_node);
	12075	+ }
	12076	+
	12077	+ for (i = 0; i < vop2->data->nr_vps; i++) {
7531	12078	DRM_DEV_INFO(dev, "vp%d assign plane mask: 0x%x, primary plane phy id: %d\n",
7532		- vp_id, vop2->vps[vp_id].plane_mask,
7533		- vop2->vps[vp_id].primary_plane_phy_id);
	12079	+ i, vop2->vps[i].plane_mask,
	12080	+ vop2->vps[i].primary_plane_phy_id);
7534	12081	}
7535	12082	}
7536	12083
	12084	+ vop2_extend_clk_init(vop2);
7537	12085	spin_lock_init(&vop2->reg_lock);
7538	12086	spin_lock_init(&vop2->irq_lock);
7539	12087	mutex_init(&vop2->vop2_lock);
	12088	+
	12089	+ if (vop2->version == VOP_VERSION_RK3528) {
	12090	+ atomic_set(&vop2->vps[1].post_buf_empty_flag, 0);
	12091	+ vop2->workqueue = create_workqueue("post_buf_empty_wq");
	12092	+ INIT_WORK(&vop2->post_buf_empty_work, post_buf_empty_work_event);
	12093	+ }
7540	12094
7541	12095	ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
7542	12096	if (ret)
7543	12097	return ret;
7544	12098
	12099	+ vop2_dsc_data_init(vop2);
	12100	+
7545	12101	registered_num_crtcs = vop2_create_crtc(vop2);
7546	12102	if (registered_num_crtcs <= 0)
7547	12103	return -ENODEV;
	12104	+
7548	12105	ret = vop2_gamma_init(vop2);
7549	12106	if (ret)
7550	12107	return ret;
	12108	+ vop2_clk_init(vop2);
7551	12109	vop2_cubic_lut_init(vop2);
7552	12110	vop2_wb_connector_init(vop2, registered_num_crtcs);
7553	12111	pm_runtime_enable(&pdev->dev);