~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,42 +1,52 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3	4	* Author:Mark Yao <mark.yao@rock-chips.com>
4		- *
5		- * This software is licensed under the terms of the GNU General Public
6		- * License version 2, as published by the Free Software Foundation, and
7		- * may be copied, distributed, and modified under those terms.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6
15	7	#ifndef _ROCKCHIP_DRM_VOP_H
16	8	#define _ROCKCHIP_DRM_VOP_H
	9	+
	10	+#include <drm/drm_plane.h>
	11	+#include <drm/drm_modes.h>
	12	+
17	13	#include "rockchip_drm_drv.h"
18	14
19	15	/*
20	16	* major: IP major version, used for IP structure
21	17	* minor: big feature change under same structure
	18	+ * build: RTL current SVN number
22	19	*/
23	20	#define VOP_VERSION(major, minor) ((major) << 8 \| (minor))
24	21	#define VOP_MAJOR(version) ((version) >> 8)
25	22	#define VOP_MINOR(version) ((version) & 0xff)
26	23
27		-#define VOP_VERSION_RK3528 VOP_VERSION(0x50, 0x17)
28		-#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
29		-#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
	24	+#define VOP2_VERSION(major, minor, build) ((major) << 24 \| (minor) << 16 \| (build))
	25	+#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
	26	+#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
	27	+#define VOP2_BUILD(version) ((version) & 0xffff)
30	28
	29	+#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
	30	+#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
	31	+#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
	32	+#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
	33	+
	34	+/* register one connector */
31	35	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
	36	+/* register one connector */
32	37	#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
33	38	#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
	39	+/* MIPI DSI DataStream(cmd) mode on rk3588 */
	40	+#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
	41	+/* register two connector */
	42	+#define ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE BIT(4)
34	43
35	44	#define AFBDC_FMT_RGB565 0x0
36	45	#define AFBDC_FMT_U8U8U8U8 0x5
37	46	#define AFBDC_FMT_U8U8U8 0x4
38		-#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
39		-#define VOP_FEATURE_AFBDC BIT(1)
	47	+
	48	+#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
	49	+#define VOP_FEATURE_INTERNAL_RGB BIT(1)
40	50	#define VOP_FEATURE_ALPHA_SCALE BIT(2)
41	51	#define VOP_FEATURE_HDR10 BIT(3)
42	52	#define VOP_FEATURE_NEXT_HDR BIT(4)
..	..	@@ -47,12 +57,17 @@
47	57	#define VOP_FEATURE_POST_ACM BIT(8)
48	58	#define VOP_FEATURE_POST_CSC BIT(9)
49	59
	60	+#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
	61	+
	62	+
50	63	#define WIN_FEATURE_HDR2SDR BIT(0)
51	64	#define WIN_FEATURE_SDR2HDR BIT(1)
52	65	#define WIN_FEATURE_PRE_OVERLAY BIT(2)
53	66	#define WIN_FEATURE_AFBDC BIT(3)
54	67	#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
55	68	#define WIN_FEATURE_CLUSTER_SUB BIT(5)
	69	+/* Left win in splice mode */
	70	+#define WIN_FEATURE_SPLICE_LEFT BIT(6)
56	71	/* a mirror win can only get fb address
57	72	* from source win:
58	73	* Cluster1---->Cluster0
..	..	@@ -66,6 +81,15 @@
66	81
67	82
68	83	#define VOP2_SOC_VARIANT 4
	84	+
	85	+#define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
	86	+
	87	+enum vop_vp_id {
	88	+ ROCKCHIP_VOP_VP0 = 0,
	89	+ ROCKCHIP_VOP_VP1,
	90	+ ROCKCHIP_VOP_VP2,
	91	+ ROCKCHIP_VOP_VP3,
	92	+};
69	93
70	94	enum bcsh_out_mode {
71	95	BCSH_OUT_MODE_BLACK,
..	..	@@ -88,7 +112,7 @@
88	112	/*
89	113	* the delay number of a window in different mode.
90	114	*/
91		-enum win_dly_mode {
	115	+enum vop2_win_dly_mode {
92	116	VOP2_DLY_MODE_DEFAULT, /*< default mode /
93	117	VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
94	118	VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
..	..	@@ -101,6 +125,39 @@
101	125	VOP3_ESMART_4K_2K_2K_MODE,
102	126	VOP3_ESMART_2K_2K_2K_2K_MODE,
103	127	};
	128	+
	129	+/*
	130	+ * vop2 dsc id
	131	+ */
	132	+#define ROCKCHIP_VOP2_DSC_8K 0
	133	+#define ROCKCHIP_VOP2_DSC_4K 1
	134	+
	135	+/*
	136	+ * vop2 internal power domain id,
	137	+ * should be all none zero, 0 will be
	138	+ * treat as invalid;
	139	+ */
	140	+#define VOP2_PD_CLUSTER0 BIT(0)
	141	+#define VOP2_PD_CLUSTER1 BIT(1)
	142	+#define VOP2_PD_CLUSTER2 BIT(2)
	143	+#define VOP2_PD_CLUSTER3 BIT(3)
	144	+#define VOP2_PD_DSC_8K BIT(5)
	145	+#define VOP2_PD_DSC_4K BIT(6)
	146	+#define VOP2_PD_ESMART BIT(7)
	147	+
	148	+/*
	149	+ * vop2 submem power gate,
	150	+ * should be all none zero, 0 will be
	151	+ * treat as invalid;
	152	+ */
	153	+#define VOP2_MEM_PG_VP0 BIT(0)
	154	+#define VOP2_MEM_PG_VP1 BIT(1)
	155	+#define VOP2_MEM_PG_VP2 BIT(2)
	156	+#define VOP2_MEM_PG_VP3 BIT(3)
	157	+#define VOP2_MEM_PG_DB0 BIT(4)
	158	+#define VOP2_MEM_PG_DB1 BIT(5)
	159	+#define VOP2_MEM_PG_DB2 BIT(6)
	160	+#define VOP2_MEM_PG_WB BIT(7)
104	161
105	162	#define DSP_BG_SWAP 0x1
106	163	#define DSP_RB_SWAP 0x2
..	..	@@ -139,6 +196,13 @@
139	196	VOP_FMT_YUV420SP = 4,
140	197	VOP_FMT_YUV422SP,
141	198	VOP_FMT_YUV444SP,
	199	+};
	200	+
	201	+enum vop_dsc_interface_mode {
	202	+ VOP_DSC_IF_DISABLE = 0,
	203	+ VOP_DSC_IF_HDMI = 1,
	204	+ VOP_DSC_IF_MIPI_DS_MODE = 2,
	205	+ VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
142	206	};
143	207
144	208	struct vop_reg_data {
..	..	@@ -191,6 +255,7 @@
191	255	struct vop_reg post_scl_factor;
192	256	struct vop_reg post_scl_ctrl;
193	257	struct vop_reg dsp_interlace;
	258	+ struct vop_reg dsp_interlace_pol;
194	259	struct vop_reg global_regdone_en;
195	260	struct vop_reg auto_gate_en;
196	261	struct vop_reg post_lb_mode;
..	..	@@ -236,6 +301,11 @@
236	301	struct vop_reg sw_uv_offset_en;
237	302	struct vop_reg dsp_out_yuv;
238	303	struct vop_reg dsp_data_swap;
	304	+ struct vop_reg dsp_bg_swap;
	305	+ struct vop_reg dsp_rb_swap;
	306	+ struct vop_reg dsp_rg_swap;
	307	+ struct vop_reg dsp_delta_swap;
	308	+ struct vop_reg dsp_dummy_swap;
239	309	struct vop_reg yuv_clip;
240	310	struct vop_reg dsp_ccir656_avg;
241	311	struct vop_reg dsp_black;
..	..	@@ -582,6 +652,7 @@
582	652	struct vop_reg gate;
583	653	struct vop_reg enable;
584	654	struct vop_reg format;
	655	+ struct vop_reg interlace_read;
585	656	struct vop_reg fmt_10;
586	657	struct vop_reg fmt_yuyv;
587	658	struct vop_reg csc_mode;
..	..	@@ -605,6 +676,17 @@
605	676	struct vop_reg global_alpha_val;
606	677	struct vop_reg color_key;
607	678	struct vop_reg color_key_en;
	679	+};
	680	+
	681	+struct vop_win_data {
	682	+ uint32_t base;
	683	+ enum drm_plane_type type;
	684	+ const struct vop_win_phy *phy;
	685	+ const struct vop_win_phy **area;
	686	+ const uint64_t *format_modifiers;
	687	+ const struct vop_csc *csc;
	688	+ unsigned int area_size;
	689	+ u64 feature;
608	690	};
609	691
610	692	struct vop2_cluster_regs {
..	..	@@ -701,7 +783,9 @@
701	783	struct vop_reg pre_scan_htiming;
702	784	struct vop_reg htotal_pw;
703	785	struct vop_reg hact_st_end;
704		- struct vop_reg vtotal_pw;
	786	+ struct vop_reg dsp_vtotal;
	787	+ struct vop_reg sw_dsp_vtotal_imd;
	788	+ struct vop_reg dsp_vs_end;
705	789	struct vop_reg vact_st_end;
706	790	struct vop_reg vact_st_end_f1;
707	791	struct vop_reg vs_st_end_f1;
..	..	@@ -719,8 +803,8 @@
719	803
720	804	struct vop_reg core_dclk_div;
721	805	struct vop_reg p2i_en;
722		- struct vop_reg mipi_dual_en;
723		- struct vop_reg mipi_dual_channel_swap;
	806	+ struct vop_reg dual_channel_en;
	807	+ struct vop_reg dual_channel_swap;
724	808	struct vop_reg dsp_lut_en;
725	809
726	810	struct vop_reg dclk_div2;
..	..	@@ -783,11 +867,37 @@
783	867	struct vop_reg cubic_lut_update_en;
784	868	struct vop_reg cubic_lut_mst;
785	869
	870	+ /* cru */
	871	+ struct vop_reg dclk_core_div;
	872	+ struct vop_reg dclk_out_div;
	873	+ struct vop_reg dclk_src_sel;
	874	+
	875	+ struct vop_reg splice_en;
	876	+
786	877	struct vop_reg edpi_wms_hold_en;
787	878	struct vop_reg edpi_te_en;
788	879	struct vop_reg edpi_wms_fs;
789	880	struct vop_reg gamma_update_en;
790	881	struct vop_reg lut_dma_rid;
	882	+
	883	+ /* MCU output */
	884	+ struct vop_reg mcu_pix_total;
	885	+ struct vop_reg mcu_cs_pst;
	886	+ struct vop_reg mcu_cs_pend;
	887	+ struct vop_reg mcu_rw_pst;
	888	+ struct vop_reg mcu_rw_pend;
	889	+ struct vop_reg mcu_clk_sel;
	890	+ struct vop_reg mcu_hold_mode;
	891	+ struct vop_reg mcu_frame_st;
	892	+ struct vop_reg mcu_rs;
	893	+ struct vop_reg mcu_bypass;
	894	+ struct vop_reg mcu_type;
	895	+ struct vop_reg mcu_rw_bypass_port;
	896	+
	897	+ /* for DCF */
	898	+ struct vop_reg line_flag_or_en;
	899	+ struct vop_reg dsp_hold_or_en;
	900	+ struct vop_reg almost_full_or_en;
791	901
792	902	/* CSC */
793	903	struct vop_reg acm_bypass_en;
..	..	@@ -807,6 +917,58 @@
807	917	struct vop_reg csc_offset0;
808	918	struct vop_reg csc_offset1;
809	919	struct vop_reg csc_offset2;
	920	+
	921	+ /* color bar */
	922	+ struct vop_reg color_bar_en;
	923	+ struct vop_reg color_bar_mode;
	924	+};
	925	+
	926	+struct vop2_power_domain_regs {
	927	+ struct vop_reg pd;
	928	+ struct vop_reg status;
	929	+ struct vop_reg bisr_en_status;
	930	+ struct vop_reg pmu_status;
	931	+};
	932	+
	933	+struct vop2_dsc_regs {
	934	+ /* DSC SYS CTRL */
	935	+ struct vop_reg dsc_port_sel;
	936	+ struct vop_reg dsc_man_mode;
	937	+ struct vop_reg dsc_interface_mode;
	938	+ struct vop_reg dsc_pixel_num;
	939	+ struct vop_reg dsc_pxl_clk_div;
	940	+ struct vop_reg dsc_cds_clk_div;
	941	+ struct vop_reg dsc_txp_clk_div;
	942	+ struct vop_reg dsc_init_dly_mode;
	943	+ struct vop_reg dsc_scan_en;
	944	+ struct vop_reg dsc_halt_en;
	945	+ struct vop_reg rst_deassert;
	946	+ struct vop_reg dsc_flush;
	947	+ struct vop_reg dsc_cfg_done;
	948	+ struct vop_reg dsc_init_dly_num;
	949	+ struct vop_reg scan_timing_para_imd_en;
	950	+ struct vop_reg dsc_htotal_pw;
	951	+ struct vop_reg dsc_hact_st_end;
	952	+ struct vop_reg dsc_vtotal;
	953	+ struct vop_reg dsc_vs_end;
	954	+ struct vop_reg dsc_vact_st_end;
	955	+ struct vop_reg dsc_error_status;
	956	+
	957	+ /* DSC encoder */
	958	+ struct vop_reg dsc_pps0_3;
	959	+ struct vop_reg dsc_en;
	960	+ struct vop_reg dsc_rbit;
	961	+ struct vop_reg dsc_rbyt;
	962	+ struct vop_reg dsc_flal;
	963	+ struct vop_reg dsc_mer;
	964	+ struct vop_reg dsc_epb;
	965	+ struct vop_reg dsc_epl;
	966	+ struct vop_reg dsc_nslc;
	967	+ struct vop_reg dsc_sbo;
	968	+ struct vop_reg dsc_ifep;
	969	+ struct vop_reg dsc_pps_upd;
	970	+ struct vop_reg dsc_status;
	971	+ struct vop_reg dsc_ecw;
810	972	};
811	973
812	974	struct vop2_wb_regs {
..	..	@@ -825,19 +987,39 @@
825	987	struct vop_reg axi_uv_id;
826	988	};
827	989
828		-struct vop_win_data {
829		- uint32_t base;
830		- enum drm_plane_type type;
831		- const struct vop_win_phy *phy;
832		- const struct vop_win_phy **area;
833		- const struct vop_csc *csc;
834		- unsigned int area_size;
835		- u64 feature;
	990	+struct vop2_power_domain_data {
	991	+ uint8_t id;
	992	+ uint8_t parent_id;
	993	+ /*
	994	+ * @module_id_mask: module id of which module this power domain is belongs to.
	995	+ * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
	996	+ */
	997	+ uint32_t module_id_mask;
	998	+
	999	+ const struct vop2_power_domain_regs *regs;
	1000	+};
	1001	+
	1002	+/*
	1003	+ * connector interface(RGB/HDMI/eDP/DP/MIPI) data
	1004	+ */
	1005	+struct vop2_connector_if_data {
	1006	+ u32 id;
	1007	+ const char *clk_src_name;
	1008	+ const char *clk_parent_name;
	1009	+ const char *pixclk_name;
	1010	+ const char *dclk_name;
	1011	+ u32 post_proc_div_shift;
	1012	+ u32 if_div_shift;
	1013	+ u32 if_div_yuv420_shift;
	1014	+ u32 bus_div_shift;
	1015	+ u32 pixel_clk_div_shift;
836	1016	};
837	1017
838	1018	struct vop2_win_data {
839	1019	const char *name;
840	1020	uint8_t phys_id;
	1021	+ uint8_t splice_win_id;
	1022	+ uint8_t pd_id;
841	1023	uint8_t axi_id;
842	1024	uint8_t axi_yrgb_id;
843	1025	uint8_t axi_uv_id;
..	..	@@ -875,6 +1057,24 @@
875	1057	const uint8_t dly[VOP2_DLY_MODE_MAX];
876	1058	};
877	1059
	1060	+struct dsc_error_info {
	1061	+ u32 dsc_error_val;
	1062	+ char dsc_error_info[50];
	1063	+};
	1064	+
	1065	+struct vop2_dsc_data {
	1066	+ uint8_t id;
	1067	+ uint8_t pd_id;
	1068	+ uint8_t max_slice_num;
	1069	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	1070	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	1071	+ const char *dsc_txp_clk_src_name;
	1072	+ const char *dsc_txp_clk_name;
	1073	+ const char *dsc_pxl_clk_name;
	1074	+ const char *dsc_cds_clk_name;
	1075	+ const struct vop2_dsc_regs *regs;
	1076	+};
	1077	+
878	1078	struct vop2_wb_data {
879	1079	uint32_t nformats;
880	1080	const uint32_t *formats;
..	..	@@ -897,11 +1097,13 @@
897	1097
898	1098	struct vop2_video_port_data {
899	1099	char id;
	1100	+ uint8_t splice_vp_id;
900	1101	uint16_t lut_dma_rid;
901	1102	uint32_t feature;
902	1103	uint64_t soc_id[VOP2_SOC_VARIANT];
903	1104	uint16_t gamma_lut_len;
904	1105	uint16_t cubic_lut_len;
	1106	+ unsigned long dclk_max;
905	1107	struct vop_rect max_output;
906	1108	const u8 pre_scan_max_dly[4];
907	1109	const u8 hdrvivid_dly[10];
..	..	@@ -952,6 +1154,14 @@
952	1154	struct vop_reg grf_dclk_inv;
953	1155	struct vop_reg grf_bt1120_clk_inv;
954	1156	struct vop_reg grf_bt656_clk_inv;
	1157	+ struct vop_reg grf_edp0_en;
	1158	+ struct vop_reg grf_edp1_en;
	1159	+ struct vop_reg grf_hdmi0_en;
	1160	+ struct vop_reg grf_hdmi1_en;
	1161	+ struct vop_reg grf_hdmi0_dsc_en;
	1162	+ struct vop_reg grf_hdmi1_dsc_en;
	1163	+ struct vop_reg grf_hdmi0_pin_pol;
	1164	+ struct vop_reg grf_hdmi1_pin_pol;
955	1165	};
956	1166
957	1167	struct vop_data {
..	..	@@ -969,6 +1179,7 @@
969	1179	struct vop_rect max_output;
970	1180	u64 feature;
971	1181	u64 soc_id;
	1182	+ u8 vop_id;
972	1183	};
973	1184
974	1185	struct vop2_ctrl {
..	..	@@ -976,6 +1187,9 @@
976	1187	struct vop_reg wb_cfg_done;
977	1188	struct vop_reg auto_gating_en;
978	1189	struct vop_reg aclk_pre_auto_gating_en;
	1190	+ struct vop_reg dma_finish_mode;
	1191	+ struct vop_reg axi_dma_finish_and_en;
	1192	+ struct vop_reg wb_dma_finish_and_en;
979	1193	struct vop_reg ovl_cfg_done_port;
980	1194	struct vop_reg ovl_port_mux_cfg_done_imd;
981	1195	struct vop_reg ovl_port_mux_cfg;
..	..	@@ -1015,9 +1229,12 @@
1015	1229	struct vop_reg edp_pin_pol;
1016	1230	struct vop_reg mipi_dclk_pol;
1017	1231	struct vop_reg mipi_pin_pol;
1018		- struct vop_reg dp_dclk_pol;
1019		- struct vop_reg dp_pin_pol;
	1232	+ struct vop_reg dp0_dclk_pol;
	1233	+ struct vop_reg dp0_pin_pol;
	1234	+ struct vop_reg dp1_dclk_pol;
	1235	+ struct vop_reg dp1_pin_pol;
1020	1236
	1237	+ /* This will be reference by win_phy_id */
1021	1238	struct vop_reg win_vp_id[16];
1022	1239	struct vop_reg win_dly[16];
1023	1240
..	..	@@ -1038,10 +1255,25 @@
1038	1255	struct vop_reg lvds_dual_mode;
1039	1256	struct vop_reg lvds_dual_channel_swap;
1040	1257
1041		- struct vop_reg cluster0_src_color_ctrl;
1042		- struct vop_reg cluster0_dst_color_ctrl;
1043		- struct vop_reg cluster0_src_alpha_ctrl;
1044		- struct vop_reg cluster0_dst_alpha_ctrl;
	1258	+ struct vop_reg dp_dual_en;
	1259	+ struct vop_reg edp_dual_en;
	1260	+ struct vop_reg hdmi_dual_en;
	1261	+ struct vop_reg mipi_dual_en;
	1262	+
	1263	+ struct vop_reg hdmi0_dclk_div;
	1264	+ struct vop_reg hdmi0_pixclk_div;
	1265	+ struct vop_reg edp0_dclk_div;
	1266	+ struct vop_reg edp0_pixclk_div;
	1267	+
	1268	+ struct vop_reg hdmi1_dclk_div;
	1269	+ struct vop_reg hdmi1_pixclk_div;
	1270	+ struct vop_reg edp1_dclk_div;
	1271	+ struct vop_reg edp1_pixclk_div;
	1272	+
	1273	+ struct vop_reg mipi0_pixclk_div;
	1274	+ struct vop_reg mipi1_pixclk_div;
	1275	+ struct vop_reg mipi0_ds_mode;
	1276	+ struct vop_reg mipi1_ds_mode;
1045	1277
1046	1278	struct vop_reg src_color_ctrl;
1047	1279	struct vop_reg dst_color_ctrl;
..	..	@@ -1051,6 +1283,7 @@
1051	1283	struct vop_reg bt1120_yc_swap;
1052	1284	struct vop_reg bt656_yc_swap;
1053	1285	struct vop_reg gamma_port_sel;
	1286	+ struct vop_reg pd_off_imd;
1054	1287
1055	1288	struct vop_reg otp_en;
1056	1289	struct vop_reg esmart_lb_mode;
..	..	@@ -1065,6 +1298,12 @@
1065	1298	bool enable_state;
1066	1299	};
1067	1300
	1301	+struct vop2_vp_plane_mask {
	1302	+ u8 primary_plane_id;
	1303	+ u8 attached_layers_nr;
	1304	+ u8 attached_layers[ROCKCHIP_MAX_LAYER];
	1305	+};
	1306	+
1068	1307	/**
1069	1308	* VOP2 data structe
1070	1309	*
..	..	@@ -1074,25 +1313,43 @@
1074	1313	struct vop2_data {
1075	1314	uint32_t version;
1076	1315	uint32_t feature;
	1316	+ uint8_t nr_dscs;
	1317	+ uint8_t nr_dsc_ecw;
	1318	+ uint8_t nr_dsc_buffer_flow;
1077	1319	uint8_t nr_vps;
1078	1320	uint8_t nr_mixers;
1079	1321	uint8_t nr_layers;
1080	1322	uint8_t nr_axi_intr;
1081	1323	uint8_t nr_gammas;
	1324	+ uint8_t nr_conns;
	1325	+ uint8_t nr_pds;
	1326	+ uint8_t nr_mem_pgs;
1082	1327	uint8_t esmart_lb_mode;
	1328	+ bool delayed_pd;
1083	1329	const struct vop_intr *axi_intr;
1084	1330	const struct vop2_ctrl *ctrl;
	1331	+ const struct vop2_dsc_data *dsc;
	1332	+ const struct dsc_error_info *dsc_error_ecw;
	1333	+ const struct dsc_error_info *dsc_error_buffer_flow;
1085	1334	const struct vop2_win_data *win;
1086	1335	const struct vop2_video_port_data *vp;
	1336	+ const struct vop2_connector_if_data *conn;
1087	1337	const struct vop2_wb_data *wb;
1088	1338	const struct vop2_layer_data *layer;
	1339	+ const struct vop2_power_domain_data *pd;
	1340	+ const struct vop2_power_domain_data *mem_pg;
1089	1341	const struct vop_csc_table *csc_table;
1090	1342	const struct vop_hdr_table *hdr_table;
1091		- const struct vop_grf_ctrl *grf_ctrl;
	1343	+ const struct vop_grf_ctrl *sys_grf;
	1344	+ const struct vop_grf_ctrl *grf;
	1345	+ const struct vop_grf_ctrl *vo0_grf;
	1346	+ const struct vop_grf_ctrl *vo1_grf;
1092	1347	const struct vop_dump_regs *dump_regs;
1093	1348	uint32_t dump_regs_size;
1094	1349	struct vop_rect max_input;
1095	1350	struct vop_rect max_output;
	1351	+ const struct vop2_vp_plane_mask *plane_mask;
	1352	+ uint32_t plane_mask_base;
1096	1353
1097	1354	unsigned int win_size;
1098	1355	};
..	..	@@ -1169,6 +1426,9 @@
1169	1426	#define ROCKCHIP_OUT_MODE_P565 2
1170	1427	#define ROCKCHIP_OUT_MODE_BT656 5
1171	1428	#define ROCKCHIP_OUT_MODE_S888 8
	1429	+#define ROCKCHIP_OUT_MODE_S666 9
	1430	+#define ROCKCHIP_OUT_MODE_YUV422 9
	1431	+#define ROCKCHIP_OUT_MODE_S565 10
1172	1432	#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
1173	1433	#define ROCKCHIP_OUT_MODE_YUV420 14
1174	1434	/* for use special outface */
..	..	@@ -1285,6 +1545,7 @@
1285	1545	DCLK_INVERT = 3
1286	1546	};
1287	1547
	1548	+
1288	1549	#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
1289	1550	#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
1290	1551	#define SCL_MAX_VSKIPLINES 4
..	..	@@ -1369,7 +1630,6 @@
1369	1630	return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
1370	1631	}
1371	1632
1372		-extern void vop2_standby(struct drm_crtc *crtc, bool standby);
1373	1633	extern const struct component_ops vop_component_ops;
1374	1634	extern const struct component_ops vop2_component_ops;
1375	1635	#endif /* _ROCKCHIP_DRM_VOP_H */