forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920
kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
34 * Author: Chris Zhong <zyw@rock-chips.com>
4
- *
5
- * This software is licensed under the terms of the GNU General Public
6
- * License version 2, as published by the Free Software Foundation, and
7
- * may be copied, distributed, and modified under those terms.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
- * GNU General Public License for more details.
135 */
146
157 #include <linux/clk.h>
....@@ -596,8 +588,8 @@
596588 if (ret)
597589 goto err_get_training_status;
598590
599
- dp->link.rate = status[0];
600
- dp->link.num_lanes = status[1];
591
+ dp->max_rate = status[0];
592
+ dp->max_lanes = status[1];
601593
602594 err_get_training_status:
603595 if (ret)
....@@ -646,9 +638,9 @@
646638 return ret;
647639 }
648640
649
- DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->link.rate,
650
- dp->link.num_lanes);
651
- return 0;
641
+ DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->max_rate,
642
+ dp->max_lanes);
643
+ return ret;
652644 }
653645
654646 int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active)
....@@ -687,7 +679,7 @@
687679 case YCBCR_4_2_0:
688680 val[0] = 5;
689681 break;
690
- };
682
+ }
691683
692684 switch (video->color_depth) {
693685 case 6:
....@@ -705,7 +697,7 @@
705697 case 16:
706698 val[1] = 4;
707699 break;
708
- };
700
+ }
709701
710702 msa_misc = 2 * val[0] + 32 * val[1] +
711703 ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0);
....@@ -725,7 +717,7 @@
725717 bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ?
726718 (video->color_depth * 2) : (video->color_depth * 3);
727719
728
- link_rate = drm_dp_bw_code_to_link_rate(dp->link.rate) / 1000;
720
+ link_rate = drm_dp_bw_code_to_link_rate(dp->max_rate) / 1000;
729721
730722 ret = cdn_dp_reg_write(dp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE);
731723 if (ret)
....@@ -744,15 +736,14 @@
744736 */
745737 do {
746738 tu_size_reg += 2;
747
- symbol = tu_size_reg * mode->clock * bit_per_pix;
748
- do_div(symbol, dp->link.num_lanes * link_rate * 8);
739
+ symbol = (u64)tu_size_reg * mode->clock * bit_per_pix;
740
+ do_div(symbol, dp->max_lanes * link_rate * 8);
749741 rem = do_div(symbol, 1000);
750742 if (tu_size_reg > 64) {
751743 ret = -EINVAL;
752744 DRM_DEV_ERROR(dp->dev,
753745 "tu error, clk:%d, lanes:%d, rate:%d\n",
754
- mode->clock, dp->link.num_lanes,
755
- link_rate);
746
+ mode->clock, dp->max_lanes, link_rate);
756747 goto err_config_video;
757748 }
758749 } while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
....@@ -766,7 +757,7 @@
766757
767758 /* set the FIFO Buffer size */
768759 val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate;
769
- val /= (dp->link.num_lanes * link_rate);
760
+ val /= (dp->max_lanes * link_rate);
770761 val = div_u64(8 * (symbol + 1), bit_per_pix) - val;
771762 val += 2;
772763 ret = cdn_dp_reg_write(dp, DP_VC_TABLE(15), val);
....@@ -787,7 +778,7 @@
787778 case 16:
788779 val = BCS_16;
789780 break;
790
- };
781
+ }
791782
792783 val += video->color_fmt << 8;
793784 ret = cdn_dp_reg_write(dp, DP_FRAMER_PXL_REPR, val);
....@@ -919,7 +910,7 @@
919910 u32 val;
920911
921912 if (audio->channels == 2) {
922
- if (dp->link.num_lanes == 1)
913
+ if (dp->max_lanes == 1)
923914 sub_pckt_num = 2;
924915 else
925916 sub_pckt_num = 4;
....@@ -998,23 +989,13 @@
998989 writel(I2S_DEC_START, dp->regs + AUDIO_SRC_CNTL);
999990 }
1000991
1001
-static void cdn_dp_audio_config_spdif(struct cdn_dp_device *dp,
1002
- struct audio_info *audio)
992
+static void cdn_dp_audio_config_spdif(struct cdn_dp_device *dp)
1003993 {
1004994 u32 val;
1005
- int sub_pckt_num = 1;
1006995
1007
- if (audio->channels == 2) {
1008
- if (dp->link.num_lanes == 1)
1009
- sub_pckt_num = 2;
1010
- else
1011
- sub_pckt_num = 4;
1012
- }
1013996 writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL);
1014997
1015
- val = MAX_NUM_CH(audio->channels);
1016
- val |= AUDIO_TYPE_LPCM;
1017
- val |= CFG_SUB_PCKT_NUM(sub_pckt_num);
998
+ val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4);
1018999 writel(val, dp->regs + SMPL2PKT_CNFG);
10191000 writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL);
10201001
....@@ -1023,24 +1004,6 @@
10231004
10241005 clk_prepare_enable(dp->spdif_clk);
10251006 clk_set_rate(dp->spdif_clk, CDN_DP_SPDIF_CLK);
1026
-}
1027
-
1028
-void cdn_dp_infoframe_set(struct cdn_dp_device *dp, int entry_id,
1029
- u8 *buf, u32 len, int type)
1030
-{
1031
- unsigned int idx;
1032
- u32 *packet = (u32 *)buf;
1033
- u32 length = len / 4;
1034
-
1035
- for (idx = 0; idx < length; idx++)
1036
- writel(cpu_to_le32(*packet++), dp->regs + SOURCE_PIF_DATA_WR);
1037
-
1038
- writel(entry_id, dp->regs + SOURCE_PIF_WR_ADDR);
1039
- writel(HOST_WR, dp->regs + SOURCE_PIF_WR_REQ);
1040
- writel(ACTIVE_IDLE_TYPE(1) | TYPE_VALID |
1041
- PACKET_TYPE(type) | PKT_ALLOC_ADDRESS(entry_id),
1042
- dp->regs + SOURCE_PIF_PKT_ALLOC_REG);
1043
- writel(PKT_ALLOC_WR_EN, dp->regs + SOURCE_PIF_PKT_ALLOC_WR_EN);
10441007 }
10451008
10461009 int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio)
....@@ -1064,7 +1027,7 @@
10641027 if (audio->format == AFMT_I2S)
10651028 cdn_dp_audio_config_i2s(dp, audio);
10661029 else if (audio->format == AFMT_SPDIF)
1067
- cdn_dp_audio_config_spdif(dp, audio);
1030
+ cdn_dp_audio_config_spdif(dp);
10681031
10691032 ret = cdn_dp_reg_write(dp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN);
10701033