add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
..
..
@@ -104,8 +104,13 @@
104
104
 	struct dsi_pll_regs reg_setup;
105
105
 
106
106
 	/* private clocks: */
107
-	struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
108
-	u32 num_hws;
107
+	struct clk_hw *out_div_clk_hw;
108
+	struct clk_hw *bit_clk_hw;
109
+	struct clk_hw *byte_clk_hw;
110
+	struct clk_hw *by_2_bit_clk_hw;
111
+	struct clk_hw *post_out_div_clk_hw;
112
+	struct clk_hw *pclk_mux_hw;
113
+	struct clk_hw *out_dsiclk_hw;
109
114
 
110
115
 	/* clock-provider: */
111
116
 	struct clk_hw_onecell_data *hw_data;
..
..
@@ -631,8 +636,19 @@
631
636
 static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
632
637
 {
633
638
 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
639
+	struct device *dev = &pll_10nm->pdev->dev;
634
640
 
635
641
 	DBG("DSI PLL%d", pll_10nm->id);
642
+	of_clk_del_provider(dev->of_node);
643
+
644
+	clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
645
+	clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
646
+	clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
647
+	clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
648
+	clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
649
+	clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
650
+	clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
651
+	clk_hw_unregister(&pll_10nm->base.clk_hw);
636
652
 }
637
653
 
638
654
 /*
..
..
@@ -653,10 +669,8 @@
653
669
 		.ops = &clk_ops_dsi_pll_10nm_vco,
654
670
 	};
655
671
 	struct device *dev = &pll_10nm->pdev->dev;
656
-	struct clk_hw **hws = pll_10nm->hws;
657
672
 	struct clk_hw_onecell_data *hw_data;
658
673
 	struct clk_hw *hw;
659
-	int num = 0;
660
674
 	int ret;
661
675
 
662
676
 	DBG("DSI%d", pll_10nm->id);
..
..
@@ -674,8 +688,6 @@
674
688
 	if (ret)
675
689
 		return ret;
676
690
 
677
-	hws[num++] = &pll_10nm->base.clk_hw;
678
-
679
691
 	snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
680
692
 	snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);
681
693
 
..
..
@@ -684,10 +696,12 @@
684
696
 				     pll_10nm->mmio +
685
697
 				     REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
686
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 				     0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
687
-	if (IS_ERR(hw))
688
-		return PTR_ERR(hw);
699
+	if (IS_ERR(hw)) {
700
+		ret = PTR_ERR(hw);
701
+		goto err_base_clk_hw;
702
+	}
689
703
 
690
-	hws[num++] = hw;
704
+	pll_10nm->out_div_clk_hw = hw;
691
705
 
692
706
 	snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
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 	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
..
..
@@ -699,10 +713,12 @@
699
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 				     REG_DSI_10nm_PHY_CMN_CLK_CFG0,
700
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 				     0, 4, CLK_DIVIDER_ONE_BASED,
701
715
 				     &pll_10nm->postdiv_lock);
702
-	if (IS_ERR(hw))
703
-		return PTR_ERR(hw);
716
+	if (IS_ERR(hw)) {
717
+		ret = PTR_ERR(hw);
718
+		goto err_out_div_clk_hw;
719
+	}
704
720
 
705
-	hws[num++] = hw;
721
+	pll_10nm->bit_clk_hw = hw;
706
722
 
707
723
 	snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
708
724
 	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
..
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@@ -710,10 +726,12 @@
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 	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
711
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 	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
712
728
 					  CLK_SET_RATE_PARENT, 1, 8);
713
-	if (IS_ERR(hw))
714
-		return PTR_ERR(hw);
729
+	if (IS_ERR(hw)) {
730
+		ret = PTR_ERR(hw);
731
+		goto err_bit_clk_hw;
732
+	}
715
733
 
716
-	hws[num++] = hw;
734
+	pll_10nm->byte_clk_hw = hw;
717
735
 	hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
718
736
 
719
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 	snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
..
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@@ -721,20 +739,24 @@
721
739
 
722
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 	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
723
741
 					  0, 1, 2);
724
-	if (IS_ERR(hw))
725
-		return PTR_ERR(hw);
742
+	if (IS_ERR(hw)) {
743
+		ret = PTR_ERR(hw);
744
+		goto err_byte_clk_hw;
745
+	}
726
746
 
727
-	hws[num++] = hw;
747
+	pll_10nm->by_2_bit_clk_hw = hw;
728
748
 
729
749
 	snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
730
750
 	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
731
751
 
732
752
 	hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
733
753
 					  0, 1, 4);
734
-	if (IS_ERR(hw))
735
-		return PTR_ERR(hw);
754
+	if (IS_ERR(hw)) {
755
+		ret = PTR_ERR(hw);
756
+		goto err_by_2_bit_clk_hw;
757
+	}
736
758
 
737
-	hws[num++] = hw;
759
+	pll_10nm->post_out_div_clk_hw = hw;
738
760
 
739
761
 	snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);
740
762
 	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
..
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@@ -743,15 +765,17 @@
743
765
 	snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
744
766
 
745
767
 	hw = clk_hw_register_mux(dev, clk_name,
746
-				 (const char *[]){
768
+				 ((const char *[]){
747
769
 				 parent, parent2, parent3, parent4
748
-				 }, 4, 0, pll_10nm->phy_cmn_mmio +
770
+				 }), 4, 0, pll_10nm->phy_cmn_mmio +
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 				 REG_DSI_10nm_PHY_CMN_CLK_CFG1,
750
772
 				 0, 2, 0, NULL);
751
-	if (IS_ERR(hw))
752
-		return PTR_ERR(hw);
773
+	if (IS_ERR(hw)) {
774
+		ret = PTR_ERR(hw);
775
+		goto err_post_out_div_clk_hw;
776
+	}
753
777
 
754
-	hws[num++] = hw;
778
+	pll_10nm->pclk_mux_hw = hw;
755
779
 
756
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 	snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
757
781
 	snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
..
..
@@ -762,13 +786,13 @@
762
786
 					REG_DSI_10nm_PHY_CMN_CLK_CFG0,
763
787
 				     4, 4, CLK_DIVIDER_ONE_BASED,
764
788
 				     &pll_10nm->postdiv_lock);
765
-	if (IS_ERR(hw))
766
-		return PTR_ERR(hw);
789
+	if (IS_ERR(hw)) {
790
+		ret = PTR_ERR(hw);
791
+		goto err_pclk_mux_hw;
792
+	}
767
793
 
768
-	hws[num++] = hw;
794
+	pll_10nm->out_dsiclk_hw = hw;
769
795
 	hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
770
-
771
-	pll_10nm->num_hws = num;
772
796
 
773
797
 	hw_data->num = NUM_PROVIDED_CLKS;
774
798
 	pll_10nm->hw_data = hw_data;
..
..
@@ -776,11 +800,30 @@
776
800
 	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
777
801
 				     pll_10nm->hw_data);
778
802
 	if (ret) {
779
-		dev_err(dev, "failed to register clk provider: %d\n", ret);
780
-		return ret;
803
+		DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
804
+		goto err_dsiclk_hw;
781
805
 	}
782
806
 
783
807
 	return 0;
808
+
809
+err_dsiclk_hw:
810
+	clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
811
+err_pclk_mux_hw:
812
+	clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
813
+err_post_out_div_clk_hw:
814
+	clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
815
+err_by_2_bit_clk_hw:
816
+	clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
817
+err_byte_clk_hw:
818
+	clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
819
+err_bit_clk_hw:
820
+	clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
821
+err_out_div_clk_hw:
822
+	clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
823
+err_base_clk_hw:
824
+	clk_hw_unregister(&pll_10nm->base.clk_hw);
825
+
826
+	return ret;
784
827
 }
785
828
 
786
829
 struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
..
..
@@ -788,9 +831,6 @@
788
831
 	struct dsi_pll_10nm *pll_10nm;
789
832
 	struct msm_dsi_pll *pll;
790
833
 	int ret;
791
-
792
-	if (!pdev)
793
-		return ERR_PTR(-ENODEV);
794
834
 
795
835
 	pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
796
836
 	if (!pll_10nm)
..
..
@@ -804,13 +844,13 @@
804
844
 
805
845
 	pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
806
846
 	if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
807
-		dev_err(&pdev->dev, "failed to map CMN PHY base\n");
847
+		DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");
808
848
 		return ERR_PTR(-ENOMEM);
809
849
 	}
810
850
 
811
851
 	pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
812
852
 	if (IS_ERR_OR_NULL(pll_10nm->mmio)) {
813
-		dev_err(&pdev->dev, "failed to map PLL base\n");
853
+		DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");
814
854
 		return ERR_PTR(-ENOMEM);
815
855
 	}
816
856
 
..
..
@@ -829,7 +869,7 @@
829
869
 
830
870
 	ret = pll_10nm_register(pll_10nm);
831
871
 	if (ret) {
832
-		dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
872
+		DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
833
873
 		return ERR_PTR(ret);
834
874
 	}
835
875