add lvds1024*800

hc

2024-01-31 f70575805708cabdedea7498aaa3f710fde4d920

 kernel/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
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..
@@ -1,14 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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5
 
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 #include "dsi_phy.h"
..
..
@@ -47,14 +39,9 @@
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 		DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
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 }
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41
 
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-static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
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+static void dsi_28nm_phy_regulator_enable_dcdc(struct msm_dsi_phy *phy)
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 {
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 	void __iomem *base = phy->reg_base;
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-
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-	if (!enable) {
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-		dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
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-		return;
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-	}
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45
 
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 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0);
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 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1);
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@@ -64,6 +51,39 @@
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 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9);
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 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7);
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 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);
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+	dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00);
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+}
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+
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+static void dsi_28nm_phy_regulator_enable_ldo(struct msm_dsi_phy *phy)
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+{
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+	void __iomem *base = phy->reg_base;
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+
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+	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0);
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+	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
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+	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0x7);
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+	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0);
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+	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x1);
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+	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1);
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+	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);
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+
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+	if (phy->cfg->type == MSM_DSI_PHY_28NM_LP)
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+		dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x05);
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+	else
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+		dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x0d);
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+}
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+
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+static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
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+{
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+	if (!enable) {
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+		dsi_phy_write(phy->reg_base +
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+			      REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
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+		return;
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+	}
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+
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+	if (phy->regulator_ldo_mode)
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+		dsi_28nm_phy_regulator_enable_ldo(phy);
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+	else
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+		dsi_28nm_phy_regulator_enable_dcdc(phy);
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 }
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 static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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@@ -76,7 +96,7 @@
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 	DBG("");
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 	if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
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-		dev_err(&phy->pdev->dev,
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+		DRM_DEV_ERROR(&phy->pdev->dev,
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 			"%s: D-PHY timing calculation failed\n", __func__);
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 		return -EINVAL;
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 	}
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@@ -84,8 +104,6 @@
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 	dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff);
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 	dsi_28nm_phy_regulator_ctrl(phy, true);
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-
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-	dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00);
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 	dsi_28nm_dphy_set_timing(phy, timing);
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..
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@@ -150,6 +168,24 @@
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 	.num_dsi_phy = 2,
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 };
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170
 
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+const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
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+	.type = MSM_DSI_PHY_28NM_HPM,
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+	.src_pll_truthtable = { {true, true}, {false, true} },
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+	.reg_cfg = {
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+		.num = 1,
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+		.regs = {
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+			{"vddio", 100000, 100},
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+		},
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+	},
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+	.ops = {
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+		.enable = dsi_28nm_phy_enable,
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+		.disable = dsi_28nm_phy_disable,
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+		.init = msm_dsi_phy_init_common,
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+	},
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+	.io_start = { 0x1a94400, 0x1a96400 },
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+	.num_dsi_phy = 2,
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+};
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+
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 const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
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 	.type = MSM_DSI_PHY_28NM_LP,
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 	.src_pll_truthtable = { {true, true}, {true, true} },